kicad-developers team mailing list archive

[Chris Pavlina <pavlina.chris@xxxxxxxxx>]

Hard to say which has the most, I've got a bunch of PCBs and they all have
some. Here's one I'm working on now that has quite a few errors at the current
clearance setting: https://misc.c4757p.com/xmega.kicad_pcb

Thinking a bit more, I'm not sure adding a small margin is a good idea either.
Suppose someone is using 0.2mm clearance, 0.2mm traces, and an 0.4mm-pitch
footprint - that should be routable, but as the limits are critical any margin
will spoil it. I've _done_ a board with those exact measurements, it did work
as is. I think we're going to have a lot of people complaining about that,
especially since it's an "invisible" margin.

Hrm. This doesn't strike me as a particularly easy problem to solve.


On Sat, Mar 19, 2016 at 11:21:01PM +0100, Tomasz Wlostowski wrote:
> On 19.03.2016 19:11, Chris Pavlina wrote:
> > Hey, just wondering about something. PNS has had slightly different rounding
> > behavior than DRC since the beginning - when I use PNS heavily on a board, I
> > usually have to decrease my clearance very slightly (say from 0.2mm to 0.199mm)
> > to make DRC pass. Is this a known issue among the devs working on GAL/PNS, and
> > is there any plan to do something about it? I suppose it's probably quite
> > difficult to make PNS perfectly emulate the behavior DRC uses - maybe we could
> > do something like applying a very small error margin to the clearance in PNS so
> > it doesn't route things *exactly* to the clearance?
> >
> 
> Hi Chris,
> 
> We know about it, the DRC calculates clearances in a completely
> different way than P&S, so rounding errors are to be expected. Your idea
> with applying a small margin looks OK to me. BTW - could you send me the
> PCB design which shows most of P&S-caused DRC errors?
> 
> Cheers,
> Tom
>