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Message #27618
Re: [PATCH] eeschema: invisible pin connection
> On Feb 7, 2017, at 8:16 AM, Nox <noxfiregalaxy@xxxxxxxxx> wrote:
>
> From a user point of perspective I would claim that the issue only raises because there is the possibility to make pins invisible. Maybe someone can explain to me the semantically need of invisible pins in general (beside the fact that kicad needs it to solve n pads: 1 pin and global label issues)? Would be changing the "invisible" flag to a "hide-if-stacked" flag feasable?
Professional electronics engineers and experienced layout people agree: invisible pins are a stupid idea and they should be banished. If you haven’t been screwed by invisible pins on a schematic, it’s only a matter of time.
I suppose that the original idea for invisible pins began back in the days of SSI and MSI logic, where everything had one power rail called VCC and also a ground rail, and to avoid cluttering up the schematic, it was convenient to make the power pins on each part hidden and give them appropriate net names.
Of course, that’s an immediate fail, as TTL has a +5V rail, and 4000-series CMOS parts could have whatever rail (within reason) the designer deemed appropriate.
Nowadays, with multiple rails on even simple designs, simply calling a power pin VCC and giving it the netname VCC and hiding it doesn’t work.
And I see in this thread that there’s a use case — stacking power pins and hiding all but one, so when a wire is added to that one visible power pin it is added to all of them. That one can make a connection to an invisible pin baffles me.
Also, consider the technician who is bringing up a new board, or is trying to repair something. S/he wants to see power pins on the schematic, otherwise how can anyone begin to start debugging?
I understand the desire to avoid cluttering up a schematic by hiding pins. I mean, we deal with monster FPGAs and CPUs here, and generally there’s a page on the schematic just for FPGA power connections (and the decoupling caps and all that). But hiding those pins has zero benefit and increases the chances of an expensive screwup.
By all means, leave the capability for invisible pins in Kicad. But the standard libraries should never use them (for reasons Chris has mentioned) and their general use should be discouraged.
-a
Follow ups
References
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[PATCH] eeschema: invisible pin connection
From: Oliver Walters, 2017-02-07
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Re: [PATCH] eeschema: invisible pin connection
From: Kristoffer Ödmark, 2017-02-07
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Re: [PATCH] eeschema: invisible pin connection
From: Oliver Walters, 2017-02-07
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Re: [PATCH] eeschema: invisible pin connection
From: Kristoffer Ödmark, 2017-02-07
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Re: [PATCH] eeschema: invisible pin connection
From: Chris Pavlina, 2017-02-07
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Re: [PATCH] eeschema: invisible pin connection
From: Kristoffer Ödmark, 2017-02-07
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Re: [PATCH] eeschema: invisible pin connection
From: Chris Pavlina, 2017-02-07
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Re: [PATCH] eeschema: invisible pin connection
From: Kristoffer Ödmark, 2017-02-07
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Re: [PATCH] eeschema: invisible pin connection
From: Chris Pavlina, 2017-02-07
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Re: [PATCH] eeschema: invisible pin connection
From: Kristoffer Ödmark, 2017-02-07
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Re: [PATCH] eeschema: invisible pin connection
From: Chris Pavlina, 2017-02-07
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Re: [PATCH] eeschema: invisible pin connection
From: Nox, 2017-02-07