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Re: [RFC] new connectivity algorithm - testers needed
Maciej Sumiński <maciej.suminski@xxxxxxx>
Fri, 23 Jun 2017 19:01:25 +0200
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After a long testing period, it is time to commit the new connectivity
algorithm. We have neither received any new bug reports, nor we could
find any defects ourselves.
Effectively it means:
- long awaited stitching vias are at your service
- ratsnest calculations should be much faster
- ratsnest for imported Eagle boards is calculated correctly (due to
- manual via stitching tool
Enjoy! Thank you Tom!
@Developers: There is more thing: please have a look at the attached
patch. The new connectivity algorithm does not calculate links count, so
I would remove it from .kicad_pcb files as well. Not to mention that it
is not even parsed, so there is no point in saving it.
Is it ok to remove them from the file format? This change is backward
seems to be backward compatible, so I do not think it is required to
bump the file format version.
While discussing this topic, I suggest also removing unconnected nodes
count and board bounding box, as they are also computed on the fly.
On 04/25/2017 05:23 PM, Tomasz Wlostowski wrote:
> Hi all,
> I've pushed the branch  containing a rewrite of the pcbnew's
> connectivity algorithm. By this algorithm, I mean:
> - computing the ratsnest and checking if all connections are complete
> - propagating net codes from the pads to the tracks/vias
> - removing unconnected copper islands in zones
> Compared to the old algorithm, it introduces several new
> - no limitations in via/zone connections - you can have loose (stitching
> vias), overlapping copper zones or zones connecting pads/vias without
> direct track connections.
> - items no longer loose their nets when not connected to any pad.
> connecting to a new pad causes automatic net code propagation.
> - the algorithm makes zero assumptions about connectivity of the items,
> vias in particular. This removes another obstacle importing designs from
> other tools (neither Eagle nor Altium make difference between stitching
> and 'ordinary' vias).
> - ratsnest can be calculated between any sort of copper items (not only
> pads). This is a must-have if we want to have copper arcs or arbitrary
> copper shapes in the future.
> - show local ratsnest works for the GAL
> - marking missing connections between overlapping objects on different
> - free via placement tool
> The branch also contains a bit of refactoring of the base pcbnew code:
> - hidden DLISTS behind iterators. Now you can use ordinary C++11 range
> based for to iterate over board's primitives. This is the first step
> towards cleanin up the storage model.
> As with all new stuff, there are some still some issues to sort out:
> - the legacy autorouter is currently disabled, as it relies a lot on the
> old connectivity algorithm's data model. We're working to migrate it to
> the new one alongside porting it to the GAL canvas.
> - there's no automated via stitching tool yet. I'm waiting to review
> Heikki's patches for the automagic via stitcher.
> - the message panel does no longer show the 'links' and 'nodes' counters
> as the new ratsnest has no direct counterpart for these. Is there any
> purpose for these counters other than diagnostics/debug?
> - some code formatting/cleanup may still be necessary
> @Heikki - once again, the sooner you'll publish your entire via
> stitching code, the higher the chance you'll get it integrated in Kicad.
> We can help with that.
> I encourage you to check out the branch, build it and test with your
> designs. In particular, if you tried zone stitching with single-pad
> components, try replacing them with vias and check if the board
> connectivity is correctly resolved and there are no DRC errors.
> I'll send some boards demonstrating the new features soon.
> Your feedback will be greatly appreciated!
>  https://github.com/twlostow/kicad-dev/tree/tom-connectivity-apr24
> PS. The final branch will also support per-net rat line visibility and
> colors as a bonus ;-)
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From dab6df44b3e7e27224bc4d24e7caf520222c56bb Mon Sep 17 00:00:00 2001
From: Maciej Suminski <maciej.suminski@xxxxxxx>
Date: Fri, 23 Jun 2017 18:32:56 +0200
Subject: [PATCH] pcbnew: Do not save 'links' information
It is not parsed anyway and the new connectivity algorithm
does not calculate it.
pcbnew/connectivity.cpp | 7 -------
pcbnew/connectivity.h | 2 --
pcbnew/kicad_plugin.cpp | 1 -
3 files changed, 10 deletions(-)
diff --git a/pcbnew/connectivity.cpp b/pcbnew/connectivity.cpp
index c7bd4c1ed..62137e8b6 100644
@@ -427,13 +427,6 @@ const
-unsigned int CONNECTIVITY_DATA::GetLinksCount() const
- return 0;
- assert( false );
unsigned int CONNECTIVITY_DATA::GetNodeCount( int aNet ) const
int sum = 0;
diff --git a/pcbnew/connectivity.h b/pcbnew/connectivity.h
index 0b5b86a65..9eb1df14e 100644
@@ -155,8 +155,6 @@ public:
unsigned int GetUnconnectedCount() const;
- unsigned int GetLinksCount() const;
unsigned int GetNodeCount( int aNet = -1 ) const;
unsigned int GetPadCount( int aNet = -1 ) const;
diff --git a/pcbnew/kicad_plugin.cpp b/pcbnew/kicad_plugin.cpp
index c76316809..1c41d467e 100644
@@ -534,7 +534,6 @@ void PCB_IO::format( BOARD* aBoard, int aNestLevel ) const
m_out->Print( 0, "\n" );
m_out->Print( aNestLevel, "(general\n" );
- m_out->Print( aNestLevel+1, "(links %d)\n", aBoard->GetConnectivity()->GetLinksCount() );
m_out->Print( aNestLevel+1, "(no_connects %d)\n", aBoard->GetConnectivity()->GetUnconnectedCount() );
// Write Bounding box info
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