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Re: [RFC] new connectivity algorithm - testers needed


On 6/23/2017 1:01 PM, Maciej Sumiński wrote:
> Hi,
> After a long testing period, it is time to commit the new connectivity
> algorithm. We have neither received any new bug reports, nor we could
> find any defects ourselves.
> Effectively it means:
> - long awaited stitching vias are at your service
> - ratsnest calculations should be much faster
> - ratsnest for imported Eagle boards is calculated correctly (due to
> stitching vias)
> - manual via stitching tool
> Enjoy! Thank you Tom!
> @Developers: There is more thing: please have a look at the attached
> patch. The new connectivity algorithm does not calculate links count, so
> I would remove it from .kicad_pcb files as well. Not to mention that it
> is not even parsed, so there is no point in saving it.
> Is it ok to remove them from the file format? This change is backward
> seems to be backward compatible, so I do not think it is required to
> bump the file format version.

I'm OK with this.  I don't see the links keyword being parsed anywhere
so I'm guessing I missed this when I wrote the parser.  I don't think
there is any need to bump the file format version.  Just make sure that
it doesn't break on v4.  VCS users may be unhappy with the change.

> While discussing this topic, I suggest also removing unconnected nodes
> count and board bounding box, as they are also computed on the fly.

I'm not sure the unconnected nodes count should go away.  I use this
quite often to make sure I have all of my nets routed before I run a
DRC.  I like the connection status information in the message panel.
I'm OK with not calculating the board board box on the fly if it's not
required for anything.

> Regards,
> Orson
> On 04/25/2017 05:23 PM, Tomasz Wlostowski wrote:
>> Hi all,
>> I've pushed the branch [1] containing a rewrite of the pcbnew's
>> connectivity algorithm. By this algorithm, I mean:
>> - computing the ratsnest and checking if all connections are complete
>> - propagating net codes from the pads to the tracks/vias
>> - removing unconnected copper islands in zones
>> Compared to the old algorithm, it introduces several new
>> features/improvements:
>> - no limitations in via/zone connections - you can have loose (stitching
>> vias), overlapping copper zones or zones connecting pads/vias without
>> direct track connections.
>> - items no longer loose their nets when not connected to any pad.
>> connecting to a new pad causes automatic net code propagation.
>> - the algorithm makes zero assumptions about connectivity of the items,
>> vias in particular. This removes another obstacle importing designs from
>> other tools (neither Eagle nor Altium make difference between stitching
>> and 'ordinary' vias).
>> - ratsnest can be calculated between any sort of copper items (not only
>> pads). This is a must-have if we want to have copper arcs or arbitrary
>> copper shapes in the future.
>> - show local ratsnest works for the GAL
>> - marking missing connections between overlapping objects on different
>> layers
>> - free via placement tool
>> The branch also contains a bit of refactoring of the base pcbnew code:
>> - hidden DLISTS behind iterators. Now you can use ordinary C++11 range
>> based for to iterate over board's primitives. This is the first step
>> towards cleanin up the storage model.
>> As with all new stuff, there are some still some issues to sort out:
>> - the legacy autorouter is currently disabled, as it relies a lot on the
>> old connectivity algorithm's data model. We're working to migrate it to
>> the new one alongside porting it to the GAL canvas.
>> - there's no automated via stitching tool yet. I'm waiting to review
>> Heikki's patches for the automagic via stitcher.
>> - the message panel does no longer show the 'links' and 'nodes' counters
>> as the new ratsnest has no direct counterpart for these. Is there any
>> purpose for these counters other than diagnostics/debug?
>> - some code formatting/cleanup may still be necessary
>> @Heikki - once again, the sooner you'll publish your entire via
>> stitching code, the higher the chance you'll get it integrated in Kicad.
>> We can help with that.
>> I encourage you to check out the branch, build it and test with your
>> designs. In particular, if you tried zone stitching with single-pad
>> components, try replacing them with vias and check if the board
>> connectivity is correctly resolved and there are no DRC errors.
>> I'll send some boards demonstrating the new features soon.
>> Your feedback will be greatly appreciated!
>> Cheers,
>> Tom
>> [1] https://github.com/twlostow/kicad-dev/tree/tom-connectivity-apr24
>> PS. The final branch will also support per-net rat line visibility and
>> colors as a bonus ;-)
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