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Re: [RFC] new connectivity algorithm - testers needed

 

On 29.06.2017 18:36, Heikki Pulkkinen wrote:
> Hi
> 
> Just start implementing my tools to new connectivity algorithm, and
> noticed that via stitchin chain needs to as many copper pour fills as
> there are chain links. Videos show what I mean.
> 

Hi Heikki,

Can you send us the board that you have on this video? It would let me
debug the problem much faster...

Tom
> regards
> 
> Heikki
> 
> new: https://youtu.be/ZV4AMstIdQY
> old: https://youtu.be/QGr2p6M6Su0
> 
> On Tue, Apr 25, 2017 at 6:23 PM, Tomasz Wlostowski
> <tomasz.wlostowski@xxxxxxx <mailto:tomasz.wlostowski@xxxxxxx>> wrote:
> 
> 
>     Hi all,
> 
>     I've pushed the branch [1] containing a rewrite of the pcbnew's
>     connectivity algorithm. By this algorithm, I mean:
>     - computing the ratsnest and checking if all connections are complete
>     - propagating net codes from the pads to the tracks/vias
>     - removing unconnected copper islands in zones
> 
>     Compared to the old algorithm, it introduces several new
>     features/improvements:
>     - no limitations in via/zone connections - you can have loose (stitching
>     vias), overlapping copper zones or zones connecting pads/vias without
>     direct track connections.
>     - items no longer loose their nets when not connected to any pad.
>     connecting to a new pad causes automatic net code propagation.
>     - the algorithm makes zero assumptions about connectivity of the items,
>     vias in particular. This removes another obstacle importing designs from
>     other tools (neither Eagle nor Altium make difference between stitching
>     and 'ordinary' vias).
>     - ratsnest can be calculated between any sort of copper items (not only
>     pads). This is a must-have if we want to have copper arcs or arbitrary
>     copper shapes in the future.
>     - show local ratsnest works for the GAL
>     - marking missing connections between overlapping objects on different
>     layers
>     - free via placement tool
> 
>     The branch also contains a bit of refactoring of the base pcbnew code:
>     - hidden DLISTS behind iterators. Now you can use ordinary C++11 range
>     based for to iterate over board's primitives. This is the first step
>     towards cleanin up the storage model.
> 
>     As with all new stuff, there are some still some issues to sort out:
>     - the legacy autorouter is currently disabled, as it relies a lot on the
>     old connectivity algorithm's data model. We're working to migrate it to
>     the new one alongside porting it to the GAL canvas.
>     - there's no automated via stitching tool yet. I'm waiting to review
>     Heikki's patches for the automagic via stitcher.
>     - the message panel does no longer show the 'links' and 'nodes' counters
>     as the new ratsnest has no direct counterpart for these. Is there any
>     purpose for these counters other than diagnostics/debug?
>     - some code formatting/cleanup may still be necessary
> 
>     @Heikki - once again, the sooner you'll publish your entire via
>     stitching code, the higher the chance you'll get it integrated in Kicad.
>     We can help with that.
> 
>     I encourage you to check out the branch, build it and test with your
>     designs. In particular, if you tried zone stitching with single-pad
>     components, try replacing them with vias and check if the board
>     connectivity is correctly resolved and there are no DRC errors.
> 
>     I'll send some boards demonstrating the new features soon.
> 
>     Your feedback will be greatly appreciated!
> 
>     Cheers,
>     Tom
> 
>     [1]
>     https://github.com/twlostow/kicad-dev/tree/tom-connectivity-apr24
>     <https://github.com/twlostow/kicad-dev/tree/tom-connectivity-apr24>
> 
>     PS. The final branch will also support per-net rat line visibility and
>     colors as a bonus ;-)
> 
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> 
> 
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