kicad-developers team mailing list archive

[Maciej Suminski <maciej.suminski@xxxxxxx>]

Hi Clemens,

On 12/14/2017 12:43 PM, Clemens Koller wrote:
> Hello, Jon!
> 
> Thank you for your work! I just watched your video and want to give you some feedback:
> 
> I would prefer not to use the term "Bus Vector". A bus is simply a list (or a collection) of arbitrarily named nets. A bus group would be - in my understanding - a group of (different) busses.
> 
> I like your syntax to represent the list (or collection) {} as well as an array of nets [].
> You first had a bus containing arbitrary nets: MEMORY{A{7..0] D[15..0] OE WE} and you refer to single nets as i.e. MEMORY.A3 or MEMORY.OE - fine.
> 
> But when you add aliases I run into troubles to keep things separate/clear:
> {RAM} appears to me as an unnamed bus containing the net RAM. WTF is that?

I accept you might not like it, but this comment is not really respectful.

> MEMORY{RAM} appears as a bus named MEMORY containing the single net RAM.
> I would expect to access that net via MEMORY.RAM - Oops.
> 
> I am definitely irritated by a net MEMORY.OE pulled out of an bus named MEMORY{RAM}. 8-(
> It's impossible to distinguish bus aliases from nets of a bus.

You are not enforced to use the aliases, they are only for convenience.
You can either use an alias or the full list of signals, it is up to you.

> Idea: It might be nice to virtually allow folding/unfolding of the net collection contained in a bus, i.e. by showing MEMORY{*} or MEMORY{..} or MEMORY{+}, whereas the '*' or '..' or '+' is shown in a different colour. If that's still to long, I would not mind renaming the bus to MEM{..} or even M{..}.
> A simple mouseover M{..} could pop-up to show all nets and arrays the bus contains.

I do not fully get the idea. MEMORY in this case stands for a bus
instance, so you can have several buses of the same type without
shorting them together. How does */../+ relate to that?

Regards,
Orson

> Side note: For big designs, table-based design entry (as well as design entry by importing tons of generated connections) seems to get more and more important. It might be wise to consider how busses (and collections of <something>) are represented there as well.
> 
> Just my five cents,
> 
> Clemens
> 
> On 2017-12-14 05:15, Jon Evans wrote:
>> Hi all,
>>
>> As some of you know, I've been working on some new features for Eeschema that expand the capabilities of buses.
>> These features are not yet complete, but I wanted to share my progress to get early feedback.
>>
>> Since there are a number of things, I have made a ~4 minute demo video, in which I walk through them and discuss:
>>
>> https://youtu.be/z6x0xiKgDIc
>>
>> In case you don't want to watch the video, here are the new features:
>>
>>   * The existing style of bus is now referred to as a Bus Vector (for example: "A[7..0]")
>>   * New concept: Bus Groups, for adding arbitrary nets to a bus
>>       o Defined in a list, separated by spaces, enclosed in curly braces. For example: "{DP DM}"
>>       o Can contain bus vectors as well as plain nets, for example "{A[7..0] D[7..0] OE WE}"
>>       o Can have an optional name in front, like "MEMORY{A[7..0] D[7..0]}"
>>       o If you add a name, the resulting nets will have the name prefixed on the front, like "MEMORY.A7"
>>   * New concept: Bus Aliases
>>       o You can use aliases to define shortcuts for bus groups.
>>       o For example, you could create an alias called "USB" that refers to the nets "DP" and "DM"
>>       o Then, you can define a bus group as "{USB}" which will contain both of those nets.
>>       o You can also add a label, like "USB1{USB}" which will result in nets "USB1.DP" and "USB1.DM <http://USB1.DM>"
>>       o Bus Aliases are editable through a new dialog, and saved with the schematic file.
>>   * New tool: Bus Unfolding
>>       o Right click on a bus, and you can easily break out any of its members into a bus entry, label, and wire.
>>       o You place the label (and set the bus entry orientation) with the first click, and then can continue wiring.
>>
>> In order to support this work, I am also working on a new connectivity algorithm for Eeschema.
>> This algorithm stores the resulting connectivity information with the graphical objects on the schematic, meaning that it's quite easy to look up what net any particular object is part of.  The new algorithm is also significantly (i.e. an order of magnitude) faster at generating connectivity than the current netlisting algorithm in my testing so far.  It will support partial updates of the connectivity when editing the schematic, so the net information will always be in sync when adding/removing/editing items in the schematic.
>>
>> The combination of a faster algorithm and caching of the connectivity results in dramatic speedups when working with large designs.
>> For example, Chris' motherboard project (which is a great benchmark, by the way!) takes several seconds to highlight nets in the current master branch, and with my changes, you can highlight any net instantaneously.
>>
>> Although it is not yet far enough along to demonstrate this, I plan to use this new connectivity algorithm to generate netlists for export, and replace the existing algorithm entirely.
>>
>> You can check out the code in my branch here, but be warned that it is not yet complete, so I am not yet proposing that anyone do exhaustive testing of it and report bugs (because I already know about many of the bugs you will find :-)
>>
>> https://github.com/craftyjon/kicad/tree/bus_upgrades
>>
>> Thanks,
>> Jon
>>
>>
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> 
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