← Back to team overview

kicad-developers team mailing list archive

Re: [RFC] Symbols and Pin mapping in v6 - Proposal


Hello Ian,

I can see your point, and it has merit.  But its a design choice.  As is the design choice to lay out the schematic by function.  For complex MCU's (and lets face it, these days all MCU's are complex with regard to functionality).  I think that really they should just be defined as pins, and the selectable functions of those pins, and said attributes.  Then how they get arranged and laid out be left up to the designer. I also believe that information like THIS pin is powered by VCC2 is also useful, as well as the current limits (pin/group).  How that gets exposed on the schematic, or what information it supplies to the PCB design is a different matter. I firmly agree that I don't think hard defining functional units is a good idea.

I often do stuff like take a part of one functional unit, lets say the SPI.  Now i don't need its clock, or its input pin, but I can use its output pin, and then use the SPI hardware to generate waveforms at a particular rate. Or the Uarts, I don't need TX, but i will use RX. Or i will mux RX and TX onto the same pin and go half duplex.  The breakdown into functional units is non-trivial, they shouldn't be encoded, more than just PIN 6, I2C2, SDA or something like that.  Its also valid for a lot of chips to have the same functional output on multiple pins.  Or to have multiple functional unit inputs simultaneously active on one pin.

Not all chips even break the io down into different power domains, or if they do the designer sets them all to 3.3V anyway, and they aren't driving any significant load, so the load characteristics become non important.  This is something only the designer knows and the part definition shouldn't be limited just because power loads may be important to some designers.

If i want to draw a schematic, and have a SPI page, that's got the SPI port pins I use, and the hardware it attaches to, i should be able to draw that.  I can now, but i have to redraw/redefine the MCU to accommodate it.

Further, port power domain information isn't (in any serious way) captured by kicad schematics now.  The MCU's are rather simplistic.  Take (a random example) the LPC2142FBD64.  Its got 3 x VDD, 1 x VDDA and VBAT.  How are they connected to the io pins, who knows.  They are just arranged along the top of the big long MCU box.  Sure, the part has P0 down the left and P1 on the right, but it doesn't even define what those pins are. Let alone what power domains they belong to.  P0 has 32 IO, its quite possible they are in multiple power domains.  There is nothing that says P0 MUST all share the same power domain. I am guessing these pins have a lot of functionality, its not exposed by the part at all.  Maybe there are parts that do show power domains for ports, i just haven't seen any.

If a designer wants to organise by function they should have that flexibility.  If the designer wants to organise by port/power domain, that should also be supported. Neither should require the MCU part to be graphically defined umpteen times, just to suit a particular layout. The tool should be flexible enough to do it, and be not artificially limited to one particular design preference.  Schematics are, after all, artworks and what is attractive to some of us will not appeal to others, and vice versa.


On 17/9/19 5:03 pm, Ian McInerney wrote:
Unfortunately, no I don't agree that the grouping should be by peripheral. The purpose of a schematic is to capture the electrical connections of a circuit, and allow the designer to reason about it. On most chips, the electrical specifications of the same peripheral type can differ between instances (e.g. I2C0 has different specs than I2C1 because they use different pins).

The most useful grouping for capturing these differences are the ports (since those map to the raw pins). The electrical characteristics are usually defined on a per-port basis (so all pins of a port will usually share the same Vcc, contribute to a per-port current limitation, have the same voltage tolerance, etc). If you abstract the IC into the peripheral functions, it becomes a lot harder to analyze the electrical characteristics when doing a proper design. For instance, say you want to use the STM32F413ZH. This chip has multiple SPI ports, but one of them (SPI1) has pins that are not 5v tolerant, and are only 3.3v tolerant. It becomes easier to analyze and work with when you group by port/pins because the datasheet doesn't tell you that SPI1 as a whole is not 5v tolerant only that pins PA4/PA5 (which it uses) are not 5v tolerant. This limitation is also present for all other peripherals that share those pins.

This same reasoning also applies to FPGAs, and I think it is better to keep the same reasoning across device types so people don't have to learn multiple ways of using the symbols and analyzing the design.

As for the generation of pin constraints to map into the embedded software, I have been thinking of ways to do that but I haven't had time to write up a full RFC for it. I am approaching it from an FPGA viewpoint first though, since those pin constraint maps can be very tedious to write and it would be nice to ensure there is consistency between the schematic and the options (such as pull-up/down status, CMOS voltage level, etc). Initially I am thinking of just introducing text fields the user fills in, but I am also going to investigate if we can define a new properties field type for selecting values from a discrete set. Then the symbol can define the valid field values and the user can choose from them. This will be a long time in development, since it will rely on the new file format and also Eeschema Python bindings for generating the constraint files.


On Mon, Sep 16, 2019 at 7:51 PM Andy Peters <devel@xxxxxxxxx <mailto:devel@xxxxxxxxx>> wrote:

    > On Sep 16, 2019, at 6:12 AM, Clemens Koller <cko@xxxxxxxxx
    <mailto:cko@xxxxxxxxx>> wrote:
    > Hello, Tim!
    > I agree that in the near future, the demand for (I'd call it)
    "Table Based Design Entry" will rise tremendously,
    > when we reach pincounts in the high hundreds and thousands.
    > It is a lot of work to draw and maintain complex MCUs/SoCs/FPGAs
    in some schematic when pins can have 8 different functions which
    might change during product development. A current example: i.MX8
    [1] with i.e. 625 pins.
    > So, it might not even be sufficient to be able to import (and
    export) .CSVs. It might be a good idea to prepare for some
    automatism to be able to update and version control pin
    multiplexing changes!

    How about this?

    We can all agree that grouping MCU pins by peripheral makes the
    most sense. So rather than having a big box symbol (or symbols)
    with pins in a default order, why not have each part of a
    component be a peripheral? Instead of having a multisymbol part
    with one or two or three boxes for my EFM32GG11B820F2408GL192 in
    the library, instead of EFM32GG11B820F2048GL192 as the part name
    and within the part have all of the valid peripherals for that

    Here’s the cool thing. This device has, say, I2C0, I2C1, I2C2,
    UART0, UART1, USART0, USART1, TIMER0, TIMER1, all of it, and there
    are a fixed number of peripherals for a given device. Each
    peripheral is a symbol (a sub-part of the device) you can place on
    your schematic. Need a UART? Place the EFM32GG11_UART0 symbol on
    the schematic. Since this particular chip family gives you several
    choices for each pin, the symbols are “Smart” and have a drop-down
    menu you use to assign the pin. Those assignments also
    automatically set pin direction and the other ERC stuff. For
    peripherals which have one location for their pins obviously this
    drop-down doesn’t exist.

    Cool, right? It can be better. Any pin not explicitly designated
    for a peripheral that can be used as GPIO gets enabled in the GPIO
    symbol. In that symbol then you set the direction, etc after you
    place it on the schematic.

    Since all of the ARM vendors these days have some kind of software
    tool that handles peripheral setup including pin assignments,
    having the ability to read that output (whatever it is) and then
    parse it and set up the individual blocks would be very cool.

    Right now I just rely on sensible net names to keep my MCU pinouts
    straight. I used to make a custom symbol for each MCU in a design
    but that got to be too much.

    FPGAs are a different can of worms.

    Mailing list: https://launchpad.net/~kicad-developers
    Post to     : kicad-developers@xxxxxxxxxxxxxxxxxxx
    Unsubscribe : https://launchpad.net/~kicad-developers
    More help   : https://help.launchpad.net/ListHelp

Mailing list: https://launchpad.net/~kicad-developers
Post to     : kicad-developers@xxxxxxxxxxxxxxxxxxx
Unsubscribe : https://launchpad.net/~kicad-developers
More help   : https://help.launchpad.net/ListHelp