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Re: [PATCH] Eeschema: simulator: use dotted traces for current and phase.

 

On 11/21/19 1:15 PM, Kymatica wrote:
> Sure, I can make it configurable. Where should this setting be available? In the main preferences? (Perhaps a new Simulator section there?)

I would think the simulator will over time have enough user (not
simulation control) configuration settings that it would have it's own
preferences dialog and that the settings would be saved in a separate
configuration file.  I think at the moment the config settings are saved
in the eeschema config file.

> 
> /Jonatan 
> 
>> 21 nov. 2019 kl. 18:26 skrev Wayne Stambaugh <stambaughw@xxxxxxxxx>:
>>
>> Hi Jonatan,
>>
>> I just tested this and it seems to work as expected although I'm
>> thinking it might be a good idea to make this a configuration option
>> rather than the only behavior.  Users might not find this desirable.
>> Anyone else have any thoughts on this?  For future reference, when you
>> are going to make behavioral changes to KiCad, please ping the dev
>> mailing list first for feedback.  I would have made the option
>> suggestion before you began coding.
>>
>> Cheers,
>>
>> Wayne
>>
>>> On 11/19/19 11:30 AM, Jonatan Liljedahl wrote:
>>> This patch makes it easier to visually keep apart traces for current
>>> vs voltage and phase vs magnitude, by using dotted line style for
>>> current and phase traces.
>>>
>>> To get the dotted style drawn correctly, I had to switch from drawing
>>> each trace line segment individually to creating an array and then
>>> using DrawLines() on it, so that the whole trace is one continuous
>>> line.
>>>
>>>
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>>
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