kicad-developers team mailing list archive

[Andrew Zonenberg <azonenberg@xxxxxxxxxxxxxxx>]

Hi,

Kicad's DXF export seems to be broken, causing many tools (such as the
Sonnet field solver, example attached) to not import layouts correctly.
I contacted Sonnet support and they did some digging; it seems like
KiCAD is producing malformed DXFs that have non-closed polygons in them.

I've also encountered two other problems getting KiCAD designs into Sonnet:

1) Sonnet's DXF import expects a *single* DXF, with one drawing layer
per PCB/via layer. KiCAD generates one DXF per layer and I don't think
there is currently a way to do a multilayer export. This isn't a fatal
problem as I can just do multiple imports, but it's annoying.

2) More seriously, There does not seem to be any way to get via drill
*outlines* in DXF format. The "drill map" file just has an X at each via
location which is useless when trying to import layout into an external
tool.

Anybody have suggestions on how to proceed, or interested in helping to
fix this? I'm not super familiar with the DXF file format although back
in the v4.x days I did do some work on the microvia/blind via Excellon
drill export code so I've done at least a little bit of work there.

(kicad_pcb (version 20171130) (host pcbnew "(5.1.4)")

  (general
    (thickness 1.6)
    (drawings 13)
    (tracks 349)
    (zones 0)
    (modules 11)
    (nets 6)
  )

  (page A4)
  (layers
    (0 F.Cu signal)
    (1 In1.Cu signal)
    (2 In2.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )

  (setup
    (last_trace_width 0.31)
    (user_trace_width 0.125)
    (user_trace_width 0.31)
    (user_trace_width 0.5)
    (user_trace_width 1)
    (trace_clearance 0.1)
    (zone_clearance 0.15)
    (zone_45_only no)
    (trace_min 0.125)
    (via_size 0.5)
    (via_drill 0.3)
    (via_min_size 0.4)
    (via_min_drill 0.3)
    (user_via 0.5 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (edge_width 0.05)
    (segment_width 0.2)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.12)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 4.8 1.4)
    (pad_drill 0)
    (pad_to_mask_clearance 0.05)
    (solder_mask_min_width 0.05)
    (aux_axis_origin 0 0)
    (visible_elements FFFFFF7F)
    (pcbplotparams
      (layerselection 0x210f8_ffffffff)
      (usegerberextensions false)
      (usegerberattributes false)
      (usegerberadvancedattributes false)
      (creategerberjobfile false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15.000000)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 0)
      (scaleselection 1)
      (outputdirectory "output/"))
  )

  (net 0 "")
  (net 1 /GND)
  (net 2 "Net-(R1-Pad1)")
  (net 3 "Net-(R2-Pad1)")
  (net 4 "Net-(J1-Pad1)")
  (net 5 "Net-(J2-Pad1)")

  (net_class Default "This is the default net class."
    (clearance 0.1)
    (trace_width 1)
    (via_dia 0.5)
    (via_drill 0.3)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net /GND)
    (add_net "Net-(J1-Pad1)")
    (add_net "Net-(J2-Pad1)")
    (add_net "Net-(R1-Pad1)")
    (add_net "Net-(R2-Pad1)")
  )

  (module azonenberg_pcb:EIA_0402_RES_NOSILK_FLIPCHIP (layer F.Cu) (tedit 5F4B5CE7) (tstamp 5E096C1E)
    (at 87.4 24 180)
    (path /5D098F11)
    (solder_paste_margin -0.06)
    (fp_text reference R3 (at 0 1.5) (layer F.SilkS) hide
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text value FC0402E2000BTT0 (at 0 3.5) (layer F.SilkS) hide
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (pad 2 smd rect (at 0.5 0 180) (size 0.5 0.5) (layers F.Cu F.Paste F.Mask)
      (net 3 "Net-(R2-Pad1)"))
    (pad 1 smd rect (at -0.5 0 180) (size 0.5 0.5) (layers F.Cu F.Paste F.Mask)
      (net 5 "Net-(J2-Pad1)"))
    (model /nfs4/home/azonenberg/kicad-libs/3rdparty/walter/smd_resistors/r_0402.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )

  (module azonenberg_pcb:EIA_0402_RES_NOSILK_FLIPCHIP (layer F.Cu) (tedit 5F4B5CE7) (tstamp 5E096C18)
    (at 86.3 24 180)
    (path /5D097CEB)
    (solder_paste_margin -0.06)
    (fp_text reference R2 (at 0 1.5) (layer F.SilkS) hide
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text value FC0402E2000BTT0 (at 0 3.5) (layer F.SilkS) hide
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (pad 2 smd rect (at 0.5 0 180) (size 0.5 0.5) (layers F.Cu F.Paste F.Mask)
      (net 2 "Net-(R1-Pad1)"))
    (pad 1 smd rect (at -0.5 0 180) (size 0.5 0.5) (layers F.Cu F.Paste F.Mask)
      (net 3 "Net-(R2-Pad1)"))
    (model /nfs4/home/azonenberg/kicad-libs/3rdparty/walter/smd_resistors/r_0402.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )

  (module azonenberg_pcb:EIA_0402_RES_NOSILK_FLIPCHIP (layer F.Cu) (tedit 5F4B5CE7) (tstamp 5E096C12)
    (at 85.2 24 180)
    (path /5CB66BBA)
    (solder_paste_margin -0.06)
    (fp_text reference R1 (at 0 1.5) (layer F.SilkS) hide
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text value FC0402E50R0BTT0 (at 0 3.5) (layer F.SilkS) hide
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (pad 2 smd rect (at 0.5 0 180) (size 0.5 0.5) (layers F.Cu F.Paste F.Mask)
      (net 4 "Net-(J1-Pad1)"))
    (pad 1 smd rect (at -0.5 0 180) (size 0.5 0.5) (layers F.Cu F.Paste F.Mask)
      (net 2 "Net-(R1-Pad1)"))
    (model /nfs4/home/azonenberg/kicad-libs/3rdparty/walter/smd_resistors/r_0402.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )

  (module azonenberg_pcb:CONN_MILLMAX_0339_EDGELAUNCH (layer F.Cu) (tedit 5E639D6C) (tstamp 5EDDBF23)
    (at 90.75 26.5)
    (path /5EDDBD80)
    (fp_text reference J4 (at -0.05 2.975) (layer F.SilkS) hide
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text value PROBETIP (at -0.025 1.575) (layer F.Fab) hide
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (pad 1 smd rect (at 0 0) (size 4.8 1.4) (layers F.Cu F.Paste F.Mask)
      (net 1 /GND))
    (model :datasheets:Mill-Max/pin-socket-0339.step
      (offset (xyz -2.1 0 0.65))
      (scale (xyz 1 1 1))
      (rotate (xyz 180 90 0))
    )
  )

  (module azonenberg_pcb:CONN_SMA_EDGE_AMPHENOL_901_10511_3 (layer F.Cu) (tedit 5EC13C71) (tstamp 5EC1259D)
    (at 17.8 24)
    (path /5CB67590)
    (fp_text reference J1 (at 0 6.1) (layer F.SilkS) hide
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text value 901-10511-3 (at 0 7.5) (layer F.Fab) hide
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_line (start -2.8 -3.65) (end -2.8 3.65) (layer Dwgs.User) (width 0.05))
    (pad ~ smd rect (at -2.05 0) (size 1.5 0.3) (layers F.Paste))
    (pad 2 smd rect (at 0 1.98) (size 5.6 3.35) (layers F.Cu F.Paste F.Mask)
      (net 1 /GND))
    (pad 2 smd rect (at 0 -1.98) (size 5.6 3.35) (layers F.Cu F.Paste F.Mask)
      (net 1 /GND))
    (pad 1 smd rect (at 0 0) (size 5.6 0.3) (layers F.Cu F.Mask)
      (net 4 "Net-(J1-Pad1)"))
    (model :datasheets:Amphenol/SMA/901-10511-3.step
      (offset (xyz -12 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 90 0 0))
    )
  )

  (module azonenberg_pcb:LONGTHING-1200DPI locked (layer B.Cu) (tedit 54B4A826) (tstamp 5E8F33CC)
    (at 45 19 180)
    (fp_text reference G*** (at 3 2) (layer B.SilkS) hide
      (effects (font (size 1.524 1.524) (thickness 0.3)) (justify mirror))
    )
    (fp_text value LOGO (at 5 0) (layer B.SilkS) hide
      (effects (font (size 1.524 1.524) (thickness 0.3)) (justify mirror))
    )
    (fp_poly (pts (xy -1.121833 1.55575) (xy -1.138776 1.527688) (xy -1.153583 1.524) (xy -1.181645 1.540944)
      (xy -1.185333 1.55575) (xy -1.16839 1.583813) (xy -1.153583 1.5875) (xy -1.125521 1.570557)
      (xy -1.121833 1.55575)) (layer B.SilkS) (width 0.1))
    (fp_poly (pts (xy -1.7357���q�^u���b�