kicad-lib-committers team mailing list archive

[Carl Poirier <carl.poirier.2@xxxxxxxxx>]

I was also thinking about C), but discussing it is a good idea.

As for the appropriate measurement, let's make sure we all agree. What
about the courtyard clearance being measured from the edge of the
silkscreen to the center of the courtyard line? There should thus be no
overlap.

Also, THT components and connectors can be at 0.5mm clearance.

Any comments?

On Sat, Jan 10, 2015 at 4:18 PM, nnn <nnn4000@xxxxx> wrote:

> The rule 6.6 is not clear for me.
>
> It's clear that for most of smd components the courtyard should be 0.25 mm
> from pads.
> What rules aplly when courtyard isn't determined by pads?
> a) should it be 0.25 mm from silkscreen?
> b) should it only enclose silkscreen?
> c) should it be 0.25 mm from package body and then enlarged to enclose
> silkscreen (if necessary)?
> I think the c) is best but it's not defined in convention.
> In cases b) and c) courtyard will be very close to silkscreen. Should it
> be allowed that centre of courtyard line lay on boundary of silkscreen line
> (0.025 overlap)? Courtyard is area limited by the line, so it seems that
> the 0.025 mm overlap should be allowed, but it may look bad.
>
> Line width for courtyard (0.05) should be defined in convention.
>
> The same clearance for 0204 SMD resistor and 5 W THT resistor is probably
> bad idea, exactly that electrolytic capacitors has bigger courtyard because
> of bigger placement tolerances. Is there any reason for using bigger
> courtyard for THT electrolytic capacitor than for eg THT radial chockes?
> Why connectors should have bigger courtyard than eg mechanical switches?
> In document: http://www.dnu.no/arkiv1/The%20CAD%20Library%20of%20the%
> 20Future.pdf
> in chapter 10.3 it's suggested that it's difficult to determine courtyard
> for THT.
>
>
>
> W dniu 09.01.2015 o 20:21, John Beard pisze:
>
>  On Fri, 2015-01-09 at 17:54 +0100, nnn wrote:
>>
>>> There is no information about courtyard line width in kicad library
>>> convention.
>>> Can it be 0.05 mm as suggested in:
>>> http://www.pcblibraries.com/downloads/temp/PCB_Design_
>>> Optimization_Starts_in_the_CAD_Library_8685831.pdf
>>> ? I used 0.05 eg in Housings_SSOP, so you can check if it looks ok.
>>>
>> Sounds very sensible to me. Since the guy who wrote that is also one of
>> the people on the committee that approved IPC-7351, this is presumably
>> consistent with that standard.
>>
>>  Can overlaping courtyard with silkscreen be allowed? It may look bad,
>>> but it's not specified in rule 6.6.
>>>
>> As the "IPC" way now is to draw the main silk screen lines at the
>> maximum material position for alignment verification purposes, and the
>> courtyard by definition is outside that, I think it would make sense to
>> at least say that all silk should be contained within the courtyard?
>> Otherwise it could be obscured by other components. If the silk extends
>> up to or outside the courtyard, that may indicate that the courtyard is
>> too tight.
>>
>> Cheers,
>>
>> John
>>
>>
>>
>>
>>
>
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