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Message #00020
[PATCH] ports-r4: clean machine code in eitent-start.S
From: Du Huanpeng <u74147@xxxxxxxxx>
there are gpio irq code in the eitent.S, these routines
are *registered* in system.c.
this commit added a machine named acd2, for acd2,
these routines are replaced with LOCAL dummy in system.c.
add variable MACH to Makefile.
Signed-off-by: Du Huanpeng <u74147@xxxxxxxxx>
---
tkernel_source/monitor/Makefile | 5 +-
tkernel_source/monitor/Makefile.obj | 24 +-
tkernel_source/monitor/Makefile.src | 24 +-
.../monitor/hwdepend/arm/cpu/eitent-start.S | 17 +-
tkernel_source/monitor/hwdepend/arm/lib/monitor.ld | 2 +-
.../monitor/hwdepend/arm/mach-acd2/chkaddr.c | 136 +++++
.../monitor/hwdepend/arm/mach-acd2/config.c | 669 +++++++++++++++++++++
.../monitor/hwdepend/arm/mach-acd2/cpuctrl.c | 82 +++
.../monitor/hwdepend/arm/mach-acd2/diskio.c | 250 ++++++++
.../hwdepend/arm/mach-acd2/eitent-interrupts.c | 0
.../monitor/hwdepend/arm/mach-acd2/eitproc.c | 132 ++++
.../monitor/hwdepend/arm/mach-acd2/hwdepend.h | 63 ++
.../monitor/hwdepend/arm/mach-acd2/hwinfo.c | 147 +++++
.../arm/mach-acd2/include/mach/cpudepend.h | 96 +++
.../hwdepend/arm/mach-acd2/include/mach/em1d512.h | 464 ++++++++++++++
.../monitor/hwdepend/arm/mach-acd2/memattr.S | 129 ++++
.../monitor/hwdepend/arm/mach-acd2/misc.c | 46 ++
.../monitor/hwdepend/arm/mach-acd2/setup_em1d512.h | 47 ++
.../monitor/hwdepend/arm/mach-acd2/sio.c | 80 +++
.../monitor/hwdepend/arm/mach-acd2/startup.c | 92 +++
.../monitor/hwdepend/arm/mach-acd2/sysdepend.h | 43 ++
.../monitor/hwdepend/arm/mach-acd2/system.c | 307 ++++++++++
.../monitor/hwdepend/arm/mach-acd2/waitusec.c | 112 ++++
23 files changed, 2934 insertions(+), 33 deletions(-)
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/chkaddr.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/config.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/cpuctrl.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/diskio.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/eitent-interrupts.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/eitproc.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/hwdepend.h
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/hwinfo.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/include/mach/cpudepend.h
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/include/mach/em1d512.h
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/memattr.S
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/misc.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/setup_em1d512.h
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/sio.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/startup.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/sysdepend.h
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/system.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/waitusec.c
diff --git a/tkernel_source/monitor/Makefile b/tkernel_source/monitor/Makefile
index c397dac..41c70a1 100644
--- a/tkernel_source/monitor/Makefile
+++ b/tkernel_source/monitor/Makefile
@@ -1,3 +1,4 @@
+MACH := mach-acd2
include Makefile.src
include Makefile.obj
@@ -5,10 +6,10 @@ CC := arm-none-eabi-gcc
LDS := "hwdepend/arm/lib/monitor.ld"
INCLUDE = \
- -Ihwdepend/arm/mach-em1d/include \
+ -Ihwdepend/arm/$(MACH)/include \
-Ihwdepend/arm/include \
-Iinclude \
- -Ihwdepend/arm/mach-em1d \
+ -Ihwdepend/arm/$(MACH) \
-I../include \
-Icmdsvc
diff --git a/tkernel_source/monitor/Makefile.obj b/tkernel_source/monitor/Makefile.obj
index 06f938d..edbd88b 100644
--- a/tkernel_source/monitor/Makefile.obj
+++ b/tkernel_source/monitor/Makefile.obj
@@ -1,17 +1,17 @@
-OBJ := hwdepend/arm/mach-em1d/startup.o
-OBJ += hwdepend/arm/mach-em1d/hwinfo.o
-OBJ += hwdepend/arm/mach-em1d/sio.o
-OBJ += hwdepend/arm/mach-em1d/diskio.o
-OBJ += hwdepend/arm/mach-em1d/eitproc.o
-OBJ += hwdepend/arm/mach-em1d/cpuctrl.o
-OBJ += hwdepend/arm/mach-em1d/misc.o
+OBJ := hwdepend/arm/$(MACH)/startup.o
+OBJ += hwdepend/arm/$(MACH)/hwinfo.o
+OBJ += hwdepend/arm/$(MACH)/sio.o
+OBJ += hwdepend/arm/$(MACH)/diskio.o
+OBJ += hwdepend/arm/$(MACH)/eitproc.o
+OBJ += hwdepend/arm/$(MACH)/cpuctrl.o
+OBJ += hwdepend/arm/$(MACH)/misc.o
OBJ += hwdepend/arm/cpu/eitent-start.o
OBJ += hwdepend/arm/cpu/reset-lowlevel.o
-OBJ += hwdepend/arm/mach-em1d/system.o
-OBJ += hwdepend/arm/mach-em1d/waitusec.o
-OBJ += hwdepend/arm/mach-em1d/config.o
+OBJ += hwdepend/arm/$(MACH)/system.o
+OBJ += hwdepend/arm/$(MACH)/waitusec.o
+OBJ += hwdepend/arm/$(MACH)/config.o
OBJ += hwdepend/arm/cpu/cpuctrl2.o
-OBJ += hwdepend/arm/mach-em1d/memattr.o
+OBJ += hwdepend/arm/$(MACH)/memattr.o
OBJ += cmdsvc/command.o
OBJ += cmdsvc/helpmsg.o
OBJ += cmdsvc/svc.o
@@ -22,7 +22,7 @@ OBJ += cmdsvc/boot.o
OBJ += lib/string.o
OBJ += hwdepend/arm/cpu/monhdr.o
OBJ += hwdepend/arm/monent.o
-OBJ += hwdepend/arm/mach-em1d/chkaddr.o
+OBJ += hwdepend/arm/$(MACH)/chkaddr.o
OBJ += hwdepend/arm/cpu/register.o
OBJ += hwdepend/arm/cpu/break.o
OBJ += hwdepend/arm/cpu/disassemble.o
diff --git a/tkernel_source/monitor/Makefile.src b/tkernel_source/monitor/Makefile.src
index ef2c32b..94e52d4 100644
--- a/tkernel_source/monitor/Makefile.src
+++ b/tkernel_source/monitor/Makefile.src
@@ -1,17 +1,17 @@
-SRC := hwdepend/arm/mach-em1d/startup.c
-SRC += hwdepend/arm/mach-em1d/hwinfo.c
-SRC += hwdepend/arm/mach-em1d/sio.c
-SRC += hwdepend/arm/mach-em1d/diskio.c
-SRC += hwdepend/arm/mach-em1d/eitproc.c
-SRC += hwdepend/arm/mach-em1d/cpuctrl.c
-SRC += hwdepend/arm/mach-em1d/misc.c
+SRC := hwdepend/arm/$(MACH)/startup.c
+SRC += hwdepend/arm/$(MACH)/hwinfo.c
+SRC += hwdepend/arm/$(MACH)/sio.c
+SRC += hwdepend/arm/$(MACH)/diskio.c
+SRC += hwdepend/arm/$(MACH)/eitproc.c
+SRC += hwdepend/arm/$(MACH)/cpuctrl.c
+SRC += hwdepend/arm/$(MACH)/misc.c
SRC += hwdepend/arm/cpu/eitent-start.S
SRC += hwdepend/arm/cpu/reset-lowlevel.S
-SRC += hwdepend/arm/mach-em1d/system.c
-SRC += hwdepend/arm/mach-em1d/waitusec.c
-SRC += hwdepend/arm/mach-em1d/config.c
+SRC += hwdepend/arm/$(MACH)/system.c
+SRC += hwdepend/arm/$(MACH)/waitusec.c
+SRC += hwdepend/arm/$(MACH)/config.c
SRC += hwdepend/arm/cpu/cpuctrl2.S
-SRC += hwdepend/arm/mach-em1d/memattr.S
+SRC += hwdepend/arm/$(MACH)/memattr.S
SRC += cmdsvc/command.c
SRC += cmdsvc/helpmsg.c
SRC += cmdsvc/svc.c
@@ -22,7 +22,7 @@ SRC += cmdsvc/boot.c
SRC += lib/string.c
SRC += hwdepend/arm/cpu/monhdr.S
SRC += hwdepend/arm/monent.c
-SRC += hwdepend/arm/mach-em1d/chkaddr.c
+SRC += hwdepend/arm/$(MACH)/chkaddr.c
SRC += hwdepend/arm/cpu/register.c
SRC += hwdepend/arm/cpu/break.c
SRC += hwdepend/arm/cpu/disassemble.c
diff --git a/tkernel_source/monitor/hwdepend/arm/cpu/eitent-start.S b/tkernel_source/monitor/hwdepend/arm/cpu/eitent-start.S
index e196182..d5088eb 100644
--- a/tkernel_source/monitor/hwdepend/arm/cpu/eitent-start.S
+++ b/tkernel_source/monitor/hwdepend/arm/cpu/eitent-start.S
@@ -16,6 +16,9 @@
* eitentry.S
*
* EM1D512 (ARM1176JZF-S) exception branch handling
+ *
+ * eitent-start.S
+ * Startup Code (reset vector)
*/
#define _in_asm_source_
@@ -39,13 +42,13 @@
.global _start
_start:
b startup_entry // 00 : reset
- b undef_entry // 04 : undefined instruction exception
- b svc_entry // 08 : supervisor call (SVC)
+ b undef_entry // 04 : undefined instruction
+ b svc_entry // 08 : software interrupt
b iabort_entry // 0C : prefetch abort
b dabort_entry // 10 : data abort
- nop // 14 : (reserved)
- b irq_entry // 18 : interrupt
-fiq_entry: // 1C : fast interrupt
+ nop // 14 : reserved
+ b irq_entry // 18 : IRQ
+fiq_entry: // 1C : FIQ
/*
* fast interrupt
* calls the handler defined at FIQ interrupt vector unconditionally.
@@ -105,6 +108,7 @@ irq_entry:
bxne lr
b default_entry
+#ifdef CONFIG_MACH_EM1D
/*
* GPIO interrupt
* Interrupt obtained by means of input port interrupt maskable status register (GIO_MST)
@@ -122,7 +126,7 @@ irq_entry:
* +---------------+
* registers upon handler invocation
* ip = vector table address
- * lr = indeterminate
+ * lr = indeterminate (return address?)
*/
.macro gio_e reg, vec
ldr lr, =base(\reg)
@@ -182,6 +186,7 @@ Csym(_gio7Hdr): gio_o GIO_MST(GIO_HHH), EITVEC(EIT_GPIO(127))
cmp lr, #0
bxne lr
b default_entry
+#endif
/*
* undefined instruction
diff --git a/tkernel_source/monitor/hwdepend/arm/lib/monitor.ld b/tkernel_source/monitor/hwdepend/arm/lib/monitor.ld
index 0f5bbdd..4f2e9d5 100644
--- a/tkernel_source/monitor/hwdepend/arm/lib/monitor.ld
+++ b/tkernel_source/monitor/hwdepend/arm/lib/monitor.ld
@@ -30,7 +30,7 @@ ENTRY(_start)
SECTIONS {
__loadaddr = .;
- _start = .;
+
.eitbra _start : AT(__loadaddr) {
__eitbra_start = .;
*(EITBRA)
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/chkaddr.c b/tkernel_source/monitor/hwdepend/arm/mach-acd2/chkaddr.c
new file mode 100644
index 0000000..e41a69f
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-acd2/chkaddr.c
@@ -0,0 +1,136 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * chkaddr.c
+ *
+ * Check address
+ */
+
+#include <cmdsvc.h>
+
+LOCAL UW validLA; /* valid logical start address */
+LOCAL UW validSz; /* valid logical address size */
+LOCAL UW mmuStat; /* MMU state */
+
+/*
+ Initialize address check data (executed upon monitor entry)
+*/
+EXPORT void initChkAddr(void)
+{
+ validLA = validSz = 0; /* clear the previous effective addresses */
+ mmuStat = getCP15(1, 0); /* MMU state */
+}
+/*
+ Check memory address
+ return contiguous range <= len (0 means illegal value)
+ * pa physical address to access
+*/
+EXPORT W chkMemAddr(UW addr, UW *pa, W len, W rw)
+{
+ const MEMSEG *mp;
+ UW n;
+
+ if (mmuStat & 0x1) { /* MMU is enabled */
+ /* if the prevous check range doesn't include the address, */
+ /* if the address is a valid existing address is checked by looking at page table. */
+ if (addr < validLA || addr >= validLA + validSz) {
+ UW pte, *ppte;
+
+ /* Depending on the valid rage of TTBR0 described in TTBCR */
+ /* TTBR0/TTBR1(=TopPageTable) is switched */
+ pte = 0xfe000000 << (7 - (getCP15(2, 2) & 0x07));
+ /* TTBCR */
+ ppte = (addr & pte) ? TopPageTable :
+ (UW *)(getCP15(2, 0) & ~0x7f); /* TTBR0 */
+ pte = ppte[addr >> 20];
+
+ validSz = 0;
+ switch(pte & 0x3) {
+ case 0x2: /* Section Entry */
+ pte &= 0xFFF00000; /* Section Address */
+ if (rw && AddrMatchMemArea(pte,
+ MSA_ROM|MSA_FROM) != NULL)
+ errinfo = E_ROM;
+ else validSz = 0x100000; /* 1 MB */
+ break;
+ case 0x1: /* Page Table Entry */
+ pte &= 0xFFFFFC00; /* Page Table Address */
+ pte = *((UW*)(pte + ((addr >>(12-2))& 0x3FC)));
+ switch(pte & 0x3) {
+ case 0x1: /* Large Page : 16 KB x 4 */
+ validSz = 0x10000; /* 64 KB */
+ break;
+ case 0x2: /* Small Page : 1 KB x 4 */
+ case 0x3: /* Small Page with XN */
+ validSz = 0x1000; /* 4 KB */
+ break;
+ }
+ break;
+ case 0x3: /* Fine Page Table Entry */
+ break; /* unsupported */
+ }
+ validLA = (validSz) ? (addr & ~(validSz - 1)) : 0;
+ }
+
+ n = (validSz) ? (validLA + validSz - addr) : 0;
+
+ } else { /* MMU is disabled, the unmodified address is used */
+ mp = AddrMatchMemArea(addr, MSA_HW);
+ if ( mp != NULL ) {
+ if ( rw && (mp->attr & (MSA_ROM|MSA_FROM)) != 0 ) {
+ n = 0;
+ errinfo = E_ROM;
+ } else {
+ n = mp->end - addr;
+ }
+ } else {
+ n = 0;
+ }
+ }
+ *pa = addr; /* access by logical address */
+ return (len > n) ? n : len;
+}
+/*
+ I/O address check & conversion to physical address
+ return contiguous range <= len (0 means illegal value)
+ * pa I/O address to access
+*/
+EXPORT W chkIOAddr(UW addr, UW *pa, W len)
+{
+ const MEMSEG *mp;
+ UW n;
+
+ mp = AddrMatchMemArea(addr, MSA_IO);
+ n = ( mp != NULL )? mp->end - addr: 0;
+
+ *pa = addr; /* access by logical address */
+ return (len > n) ? n : len;
+}
+/*
+ Validate PC
+ return 0: OK, -1: illegal
+*/
+EXPORT W invalidPC(UW addr)
+{
+ /* memory range check is not performed */
+ /* an odd address needs to be regarded as THUMB, and so nothing is done here. */
+ return 0;
+}
+EXPORT W invalidPC2(UW addr)
+{
+ /* memory range check is not performed */
+ /* PC of an ARM instruction is always on WORD-boundary */
+ return (addr & 0x03) ? -1 : 0;
+}
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/config.c b/tkernel_source/monitor/hwdepend/arm/mach-acd2/config.c
new file mode 100644
index 0000000..5b96651
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-acd2/config.c
@@ -0,0 +1,669 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by T-Engine Forum at 2011/09/08.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * config.c
+ *
+ * system-related processing / system configuration information
+ *
+ * target: T-Engine/EM1D-512
+ */
+
+#include "sysdepend.h"
+#include <mach/em1d512.h>
+
+/* used device driver */
+IMPORT ER initSIO_ns16550(SIOCB *, const CFGSIO *, W speed);
+IMPORT ER initMemDisk(DISKCB *, const CFGDISK *);
+
+/* memory region definition */
+EXPORT MEMSEG MemSeg[] = {
+ /* Bank1/2/3 */
+ {0x10000000, 0x30000000, MSA_IO, PGA_RW|PGA_D |PGA_S|PGA_XN},
+ /* DDR2 SDRAM, 64Mbyte */
+ {0x30000000, 0x40000000, MSA_RAM, PGA_RW|PGA_C},
+ /* EM1 internal device (1) */
+ {0x40000000, 0x70000000, MSA_IO, PGA_RW|PGA_D |PGA_S|PGA_XN},
+ /* Bank0 */
+ {0x70000000, 0x72000000, MSA_FROM, PGA_RO|PGA_C |0x90000000},
+ /* EM1 internal SRAM */
+ {0xa0000000, 0xb0000000, MSA_SRAM, PGA_RW|PGA_NC},
+ /* EM1 internal device (2) */
+ {0xb0000000, 0xd0000000, MSA_IO, PGA_RW|PGA_D |PGA_S|PGA_XN},
+ /* EM1 internal Boot ROM */
+ {0xf0000000, 0xffffffff, MSA_ROM, PGA_RO|PGA_NC},
+
+ {0x70000000, 0x70020000, MSA_MON, 0},
+ {0x70030000, 0x72000000, MSA_RDA, 0},
+ {0x30006000, 0x34000000, MSA_OS, 0},
+};
+
+EXPORT W N_MemSeg = sizeof(MemSeg) / sizeof(MEMSEG);
+
+/* unused memory region definition */
+EXPORT MEMSEG NoMemSeg[] = {
+ {0x00000000, 0x10000000, 0, 0},
+ {0x72000000, 0xa0000000, 0, 0},
+ {0xd0000000, 0xf0000000, 0, 0},
+};
+
+EXPORT W N_NoMemSeg = sizeof(NoMemSeg) / sizeof(MEMSEG);
+
+/*
+ * serial port configuration definition
+ * list in the order of port number
+ */
+EXPORT const CFGSIO ConfigSIO[] = {
+ {initSIO_ns16550, 0},
+};
+
+EXPORT const W N_ConfigSIO = sizeof(ConfigSIO) / sizeof(CFGSIO);
+
+
+/*
+ * disk drive configuration definition
+ * list in the order of port number
+ */
+EXPORT const CFGDISK ConfigDisk[] = {
+ {"rda", DA_RONLY, initMemDisk, 0}, /* FlashROM */
+};
+
+EXPORT const W N_ConfigDisk = sizeof(ConfigDisk) / sizeof(CFGDISK);
+
+/* boot information */
+EXPORT const UH BootSignature = 0xe382; /* signature */
+EXPORT UB * const PBootAddr = (UB *)0x30200000; /* primary boot loader address */
+
+/* ------------------------------------------------------------------------ */
+
+#define IICC_IICE (1 << 7)
+#define IICC_WREL (1 << 5)
+#define IICC_WTIM (1 << 3)
+#define IICC_ACKE (1 << 2)
+#define IICC_STT (1 << 1)
+#define IICC_SPT (1 << 0)
+
+#define IICCL_SMC (1 << 3)
+#define IICCL_DFC (1 << 2)
+
+#define IICSE_MSTS (1 << 15)
+#define IICSE_ALD (1 << 14)
+#define IICSE_ACKD (1 << 10)
+#define IICSE_SPD (1 << 8)
+
+#define IICF_IICBSY (1 << 6)
+#define IICF_STCEN (1 << 1)
+#define IICF_IICRSV (1 << 0)
+
+#define IIC_TOPDATA (1 << 11)
+#define IIC_LASTDATA (1 << 10)
+
+#define TIMEOUT 1000000 /* microsec */
+
+#define IIC2_IRQ 39
+#define IRQbit(x) (1 << ((x) % 32))
+
+/* wait for register state information */
+LOCAL ER wait_state(UW addr, UW mask, UW value)
+{
+ W i;
+
+ for (i = TIMEOUT; i > 0; i--) {
+ waitUsec(1);
+ if ((in_w(addr) & mask) == value) break;
+ }
+
+ return i ? E_OK : E_TMOUT;
+}
+
+/* interrupt Raw status / clear */
+LOCAL void clear_int(void)
+{
+ out_w(IT0_IIR, IRQbit(IIC2_IRQ)); /* IRQ39 clear */
+ return;
+}
+
+/* interrupt Raw status / useable */
+LOCAL void setup_int(void)
+{
+ out_w(IT_PINV_CLR1, IRQbit(IIC2_IRQ));
+ out_w(IT0_IENS1, IRQbit(IIC2_IRQ));
+ clear_int();
+ return;
+}
+
+/* wait for interrupt Raw status */
+LOCAL ER wait_int(void)
+{
+ ER er;
+
+ er = wait_state(IT0_RAW1, IRQbit(IIC2_IRQ), IRQbit(IIC2_IRQ));
+ clear_int();
+
+ return er;
+}
+
+/* start / restart */
+LOCAL ER send_start(UB addr)
+{
+ ER er;
+ UW sts;
+
+ /* generate start condition */
+ out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) & ~IICC_ACKE);
+ out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_STT);
+
+ /* wait for reserving a master */
+ er = wait_state(IIC_IICSE(IIC2), IICSE_MSTS, IICSE_MSTS);
+ if (er < E_OK) goto fin0;
+
+ /* slave address / communication mode transmission */
+ out_w(IIC_IIC(IIC2), addr);
+ er = wait_int();
+ if (er < E_OK) goto fin0;
+
+ /* error check */
+ sts = in_w(IIC_IICSE(IIC2));
+ if ((sts & IICSE_ALD) || !(sts & IICSE_ACKD)) {
+ er = E_IO;
+ goto fin0;
+ }
+
+ er = E_OK;
+fin0:
+ return er;
+}
+
+/* stop */
+LOCAL ER send_stop(void)
+{
+ ER er;
+
+ /* generate stop condition */
+ out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_SPT);
+
+ /* wait for sending STOP bit(s) */
+ er = wait_state(IIC_IICSE(IIC2), IICSE_SPD, IICSE_SPD);
+
+ return er;
+}
+
+/* data transmission */
+LOCAL ER send_data(UB data)
+{
+ ER er;
+ UW sts;
+
+ /* data transmission */
+ out_w(IIC_IIC(IIC2), data);
+ er = wait_int();
+ if (er < E_OK) goto fin0;
+
+ /* NAK check */
+ sts = in_w(IIC_IICSE(IIC2));
+ if (!(sts & IICSE_ACKD)) {
+ er = E_IO;
+ goto fin0;
+ }
+
+ er = E_OK;
+fin0:
+ return er;
+}
+
+/* data receive */
+LOCAL W recv_data(W attr)
+{
+ W er;
+
+ /* when the first data is received, switch to receive mode */
+ if (attr & IIC_TOPDATA) {
+ out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) & ~IICC_WTIM);
+ out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_ACKE);
+ }
+
+ /* instruct the reception of data */
+ out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_WREL);
+ er = wait_int();
+ if (er < E_OK) goto fin0;
+
+ /* read data */
+ er = in_w(IIC_IIC(IIC2)) & 0xff;
+fin0:
+ /* when an error occurs, or the last byte is seen, then perform the post processing */
+ if ((attr & IIC_LASTDATA) || er < E_OK) {
+ out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_WTIM);
+ out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) & ~IICC_ACKE);
+ out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_WREL);
+ wait_int();
+ }
+
+ return er;
+}
+
+/* start IIC send/receive */
+LOCAL ER iic_start(void)
+{
+ ER er;
+
+ /* initialization default */
+ out_w(IIC_IICC(IIC2), 0); /* stop completely */
+ out_w(IIC_IICCL(IIC2), IICCL_SMC | IICCL_DFC); /* fast mode + filter */
+ out_w(IIC_IICF(IIC2), IICF_STCEN | IICF_IICRSV);/* forcibly start transmission */
+ out_w(IIC_IICC(IIC2), IICC_IICE | IICC_WTIM); /* IIC mode, 9bit mode */
+ clear_int();
+
+ /* wait for bus to become available (since there is only one master, the bus is supposed to be unoccupied) */
+ er = wait_state(IIC_IICF(IIC2), IICF_IICBSY, 0);
+
+ return er;
+}
+
+/* stop IIC send/receive */
+LOCAL void iic_finish(void)
+{
+ out_w(IIC_IICC(IIC2), 0); /* stop completely */
+ return;
+}
+
+/* read IIC-GPIO */
+LOCAL W IICGPIORead(W addr)
+{
+ W dat;
+
+ setup_int();
+
+ iic_start();
+ send_start(addr);
+ dat = recv_data(IIC_TOPDATA | IIC_LASTDATA);
+ send_stop();
+ iic_finish();
+
+ clear_int();
+
+ return dat;
+}
+
+/* IIC-GPIO write */
+LOCAL void IICGPIOWrite(W addr, W dat)
+{
+ setup_int();
+
+ iic_start();
+ send_start(addr);
+ send_data(dat);
+ send_stop();
+ iic_finish();
+
+ clear_int();
+
+ return;
+}
+
+/* ------------------------------------------------------------------------ */
+
+IMPORT W pmicRead(W reg);
+IMPORT W pmicWrite(W reg, W dat);
+#define pmicDelay(x) waitUsec(4) /* about 16msec */
+#define USBPowerOn 0xe0 /* GPIO13(OD), High * power is supplied to A connector only */
+#define USBPowerOff 0xe0 /* GPIO13(OD), High */
+
+/* obtain DipSw status */
+EXPORT UW DipSwStatus(void)
+{
+ UW d;
+
+ /* read data from read port */
+ d = IICGPIORead(0xd9);
+
+ /* unnecessary bits are masked and then invert logic. */
+ d = (d ^ SW_MON) & SW_MON;
+
+ /* check abort switch */
+ if (in_w(GIO_I(GIO_L)) & 0x00000100) d |= SW_ABT;
+
+ return d;
+}
+
+/* USB power control */
+EXPORT void usbPower(BOOL power)
+{
+ pmicWrite(27, (pmicRead(27) & 0x0f) |
+ (power ? USBPowerOn : USBPowerOff));
+ pmicDelay();
+}
+
+/* power off */
+EXPORT void powerOff(void)
+{
+ W i;
+
+ for (i = 10; i < 14; i++) pmicWrite(i, 0xff); /* IRQ_MASK_A-D (mask) */
+ pmicDelay();
+
+ for (i = 5 ; i < 9; i++) pmicWrite(i, 0xff); /* EVENT_A-D (clear) */
+ pmicDelay();
+
+ while (1) {
+ pmicWrite(15, 0x60); /* DEEP_SLEEP */
+ pmicDelay();
+ }
+}
+
+/* reset start*/
+EXPORT void resetStart(void)
+{
+ while (1) {
+ /* reset */
+ pmicWrite(15, 0xac); /* SHUTDOWN */
+ pmicDelay();
+ }
+}
+
+/* initialize hardware peripherals (executed only during reset) */
+EXPORT void initHardware(void)
+{
+ /* enable abort switch interrupt */
+ out_w(GIO_IDT1(GIO_L), 0x00000008); /* asynchronous leading-edge high interrupt */
+ out_w(GIO_IIR(GIO_L), 0x00000100);
+ out_w(GIO_IIA(GIO_L), 0x00000100);
+ out_w(GIO_IEN(GIO_L), 0x00000100);
+
+ return;
+}
+
+/* LED on/off */
+EXPORT void cpuLED(UW v)
+{
+ UB m, d, r, c;
+
+ m = ~((v >> 16) | 0xf0); /* mask (0:unmodified 1:modify) */
+ d = ~((v >> 0) | 0xf0); /* set value (0:on 1:off) */
+ r = IICGPIORead(0xb9);
+ c = (r ^ d) & m; /* modify flag (0:unmodified 1:modify) */
+ IICGPIOWrite(0xb8, r ^ c);
+}
+
+/*
+ * machine-dependent interrupt processing
+ * vec interrupt vector number
+ * return value 0: unsupported target
+ * 1: for the supported target, processing was performed. (monitor still continues)
+ * 2: for the supported target, proceesing was performed (interrupt handler is exited)
+ */
+EXPORT W procHwInt(UW vec)
+{
+ /* only abort switch (GPIO(P8)) is supported */
+ if (vec != EIT_GPIO(8)) return 0;
+
+ /* clear interrupt */
+ out_w(GIO_IIR(GIO_L), 0x00000100);
+
+ DSP_S("Abort Switch (SW1) Pressed");
+ return 1;
+}
+
+/* ------------------------------------------------------------------------ */
+
+/*
+ configure GPIO pin multiplexer
+
+ * : used functions
+
+ pin name function 0(00) function1(01) function2(10) function3(11)
+ GIO_P0 GIO_P0*
+ GIO_P1 GIO_P1* USB_WAKEUP USB_PWR_FAULT
+ GIO_P2 GIO_P2*
+ GIO_P3 GIO_P3*
+ GIO_P4 GIO_P4* NAND_RB1
+ GIO_P5 GIO_P5 NAND_RB2 CAM_SCLK*
+ GIO_P6 GIO_P6* NAND_RB3
+ GIO_P7 GIO_P7* NAND_CE0
+ GIO_P8 GIO_P8* NAND_CE1
+ GIO_P9 GIO_P9* NAND_CE2
+ GIO_P10 GIO_P10* NAND_CE3
+ AB0_CLK GIO_P11 AB0_CLK* NTS_CLK
+ AB0_AD0 GIO_P12 AB0_AD0*
+ AB0_AD1 GIO_P13 AB0_AD1*
+ AB0_AD2 GIO_P14 AB0_AD2*
+ AB0_AD3 GIO_P15 AB0_AD3*
+
+ pin name function 0(00) function1(01) function2(10) function3(11)
+ AB0_AD4 GIO_P16 AB0_AD4*
+ AB0_AD5 GIO_P17 AB0_AD5*
+ AB0_AD6 GIO_P18 AB0_AD6*
+ AB0_AD7 GIO_P19 AB0_AD7*
+ AB0_AD8 GIO_P20 AB0_AD8*
+ AB0_AD9 GIO_P21 AB0_AD9*
+ AB0_AD10 GIO_P22 AB0_AD10*
+ AB0_AD11 GIO_P23 AB0_AD11*
+ AB0_AD12 GIO_P24 AB0_AD12*
+ AB0_AD13 GIO_P25 AB0_AD13*
+ AB0_AD14 GIO_P26 AB0_AD14*
+ AB0_AD15 GIO_P27 AB0_AD15*
+ AB0_A17 GIO_P28 AB0_A17*
+ AB0_A18 GIO_P29 AB0_A18*
+ AB0_A19 GIO_P30 AB0_A19*
+ AB0_A20 GIO_P31 AB0_A20*
+
+ pin name function 0(00) function1(01) function2(10) function3(11)
+ AB0_A21 GIO_P32 AB0_A21*
+ AB0_A22 GIO_P33 AB0_A22*
+ AB0_A23 GIO_P34 AB0_A23*
+ AB0_A24 GIO_P35 AB0_A24*
+ AB0_A25 GIO_P36* AB0_A25
+ AB0_A26 GIO_P37* AB0_A26
+ AB0_ADV GIO_P38 AB0_ADV*
+ AB0_RDB GIO_P39 AB0_RDB* NTS_DATA3
+ AB0_WRB GIO_P40 AB0_WRB* NTS_DATA4
+ AB0_WAIT GIO_P41 AB0_WAIT* NTS_DATA5
+ AB0_CSB0 GIO_P42 AB0_CSB0* NTS_DATA6
+ AB0_CSB1 GIO_P43 AB0_CSB1* NTS_DATA7
+ AB0_CSB2 GIO_P44* AB0_CSB2 NTS_VS
+ AB0_CSB3 GIO_P45 AB0_CSB3* NTS_HS
+ AB0_BEN0 GIO_P46 AB0_BEN0*
+ AB0_BEN1 GIO_P47 AB0_BEN1*
+
+ pin name function 0(00) function1(01) function2(10) function3(11)
+ SP0_CS1 GIO_P48 SP0_CS1*
+ SP0_CS2 GIO_P49 SP0_CS2*
+ LCD_PXCLK GIO_P50 LCD_PXCLK*
+ LCD_R0 GIO_P51 LCD_R0*
+ LCD_R1 GIO_P52 LCD_R1*
+ LCD_R2 GIO_P53 LCD_R2*
+ LCD_R3 GIO_P54 LCD_R3*
+ LCD_R4 GIO_P55 LCD_R4*
+ LCD_R5 GIO_P56 LCD_R5*
+ LCD_G0 GIO_P57 LCD_G0*
+ LCD_G1 GIO_P58 LCD_G1*
+ LCD_G2 GIO_P59 LCD_G2*
+ LCD_G3 GIO_P60 LCD_G3*
+ LCD_G4 GIO_P61 LCD_G4*
+ LCD_G5 GIO_P62 LCD_G5*
+ LCD_B0 GIO_P63 LCD_B0*
+
+ pin name function 0(00) function1(01) function2(10) function3(11)
+ LCD_B1 GIO_P64 LCD_B1*
+ LCD_B2 GIO_P65 LCD_B2*
+ LCD_B3 GIO_P66 LCD_B3*
+ LCD_B4 GIO_P67 LCD_B4*
+ LCD_B5 GIO_P68 LCD_B5*
+ LCD_HSYNC GIO_P69 LCD_HSYNC*
+ LCD_VSYNC GIO_P70 LCD_VSYNC*
+ LCD_ENABLE GIO_P71 LCD_ENABLE*
+ NTS_CLK GIO_P72* NTS_CLK PM1_CLK
+ NTS_VS GIO_P73* NTS_VS SP1_CLK
+ NTS_HS GIO_P74* NTS_HS SP1_SI
+ NTS_DATA0 GIO_P75 NTS_DATA0 SP1_SO CAM_YUV0*
+ NTS_DATA1 GIO_P76 NTS_DATA1 SP1_CS0 CAM_YUV1*
+ NTS_DATA2 GIO_P77 NTS_DATA2 SP1_CS1 CAM_YUV2*
+ NTS_DATA3 GIO_P78 NTS_DATA3 SP1_CS2 CAM_YUV3*
+ NTS_DATA4 GIO_P79 NTS_DATA4 SP1_CS3 CAM_YUV4*
+
+ pin name function 0(00) function1(01) function2(10) function3(11)
+ NTS_DATA5 GIO_P80* NTS_DATA5 SP1_CS4 PM1_SEN
+ NTS_DATA6 GIO_P81* NTS_DATA6 SP1_CS5 PM1_SI
+ NTS_DATA7 GIO_P82* NTS_DATA7 PM1_SO
+ IIC_SCL GIO_P83 IIC_SCL*
+ IIC_SDA GIO_P84 IIC_SDA*
+ URT0_CTSB GIO_P85 URT0_CTSB URT1_SRIN*
+ URT0_RTSB GIO_P86 URT0_RTSB URT1_SOUT*
+ PM0_SI GIO_P87 PM0_SI*
+ SD0_DATA1 GIO_P88 SD0_DATA1*
+ SD0_DATA2 GIO_P89 SD0_DATA2*
+ SD0_DATA3 GIO_P90 SD0_DATA3*
+ SD0_CKI GIO_P91 SD0_CKI*
+ SD1_CKI GIO_P92 SD1_CKI CAM_CLKI*
+ SD2_CKI GIO_P93 SD2_CKI* NAND_OE
+ PWM0 GIO_P94* PWM0
+ PWM1 GIO_P95* PWM1
+
+ pin name function 0(00) function1(01) function2(10) function3(11)
+ USB_CLK GIO_P96 USB_CLK*
+ USB_DATA0 GIO_P97 USB_DATA0*
+ USB_DATA1 GIO_P98 USB_DATA1*
+ USB_DATA2 GIO_P99 USB_DATA2*
+ USB_DATA3 GIO_P100 USB_DATA3*
+ USB_DATA4 GIO_P101 USB_DATA4*
+ USB_DATA5 GIO_P102 USB_DATA5*
+ USB_DATA6 GIO_P103 USB_DATA6*
+ USB_DATA7 GIO_P104 USB_DATA7*
+ USB_DIR GIO_P105 USB_DIR*
+ USB_STP GIO_P106 USB_STP*
+ USB_NXT GIO_P107 USB_NXT*
+ URT2_SRIN GIO_P108 URT2_SRIN*
+ URT2_SOUT GIO_P109 URT2_SOUT*
+ URT2_CTSB GIO_P110 URT2_CTSB*
+ URT2_RTSB GIO_P111 URT2_RTSB*
+
+ pin name function 0(00) function1(01) function2(10) function3(11)
+ SD2_CKO GIO_P112 SD2_CKO* NAND_D2
+ SD2_CMD GIO_P113 SD2_CMD* NAND_D3
+ SD2_DATA0 GIO_P114 SD2_DATA0* NAND_D4
+ SD2_DATA1 GIO_P115 SD2_DATA1* NAND_D5
+ SD2_DATA2 GIO_P116 SD2_DATA2* NAND_D6
+ SD2_DATA3 GIO_P117 SD2_DATA3* NAND_D7
+*/
+EXPORT const UW GPIOConfig[] __attribute__((section(".startup"))) = {
+ CHG_PINSEL_G(0),
+ 0x55400C00, /* AB0_CLK,AB0_AD3-0,CAM_SCLK */
+ CHG_PINSEL_G(16),
+ 0x55555555, /* AB0_AD15-4,AB0_A20-17 */
+ CHG_PINSEL_G(32),
+ 0x54555055, /* AB0_BEN1-0,AB0_CSB3,AB0_CSB1-0, */
+ /* AB0_WAIT,AB0_WRB,AB0_RDB,AB0_ADV, */
+ /* AB0_A24-21 */
+
+ CHG_CTRL_AB0_BOOT, /* AB0(AsyncBus0) pin: */
+ 0x00000001, /* configured by PINSEL */
+
+ CHG_PINSEL_G(48),
+ 0x55555555, /* LCD,SP0_CS2-1 */
+ CHG_PINSEL_G(64),
+ 0xffc05555, /* CAM_YUV4-0,LCD */
+ CHG_PINSEL_G(80),
+ 0x06556940, /* SD2_CKI,CAM_CLKI,SD0_CKI,SD0_DATA3-1, */
+ /* PM0,URT1,IIC */
+ CHG_PINSEL_G(96),
+ 0x55555555, /* URT2,USB */
+ CHG_PINSEL_G(112),
+ 0x00000555, /* SD2 */
+ CHG_PINSEL_SP0,
+ 0x00000000,
+ CHG_PINSEL_DTV,
+ 0x00000001,
+ CHG_PINSEL_SD0,
+ 0x00000000,
+ CHG_PINSEL_SD1,
+ 0x00000002,
+ CHG_PINSEL_IIC2,
+ 0x00000000,
+ CHG_PULL_G(0),
+ 0x55055005, /* P7,P6,P4,P3,P0: IN, pull-up/down dis */
+ CHG_PULL_G(8),
+ 0x00000005, /* P8: IN, pull-up/down dis */
+ CHG_PULL_G(16),
+ 0x00000000, /* (default) */
+ CHG_PULL_G(24),
+ 0x00000000, /* (default) */
+ CHG_PULL_G(32),
+ 0x00550000, /* P37,36: IN, pull-up/down dis */
+ CHG_PULL_G(40),
+ 0x00050000, /* P44: IN, pull-up/down dis */
+ CHG_PULL_G(48),
+ 0x11111111, /* (default) */
+ CHG_PULL_G(56),
+ 0x11111111, /* (default) */
+ CHG_PULL_G(64),
+ 0x11111111, /* (default) */
+ CHG_PULL_G(72),
+ 0x00000005, /* P72: IN, pull-up/down dis */
+ CHG_PULL_G(80),
+ 0x00400050, /* P81: IN, pull-up/down dis */
+ /* URT1_SRIN: IN, pull-down */
+ CHG_PULL_G(88),
+ 0x55000444, /* P95,94: IN, pull-up/down dis */
+ /* SD0_DATA3-1: IN, pull-down */
+ CHG_PULL_G(96),
+ 0x44444444, /* USB signals: IN, pull-down */
+ CHG_PULL_G(104),
+ 0x04044444, /* USB signals: IN, pull-down */
+ /* URT2_CTSB,URT2_SRIN: IN, pull-down */
+ CHG_PULL_G(112),
+ 0x00000000, /* (default) */
+ CHG_PULL_G(120),
+ 0x00000000, /* (default) */
+
+ CHG_PULL(0),
+ 0x50000004, /* URT0_SRIN: IN, pull-up/down dis */
+ /* DEBUG_EN: IN, pull-down */
+ CHG_PULL(1),
+ 0x15110600, /* SP0_SO: OUT, pull-up/down dis */
+ /* SP0_SI: IN, pull-up/down dis */
+ /* SP0_CS: OUT, pull-up/down dis */
+ /* SP0_CK: OUT, pull-up/down dis */
+ /* JT0C: IN, pull-up */
+ /* JT0B: OUT, pull-down */
+ /* JT0A: OUT, pull-down */
+ CHG_PULL(2),
+ 0x60000661, /* PM0_SEN: IN, pull-up */
+ /* SD0_DAT: IN, pull-up */
+ /* SD1_CMD: IN, pull-up */
+ /* SD0_CLK: OUT, pull-up/down dis */
+ CHG_PULL(3),
+ 0x00000000, /* (default) */
+
+ GIO_E0(GIO_L),
+ 0x000001d9, /* P8,P7,P6,P4,P3,P0: IN */
+ GIO_E1(GIO_L),
+ 0x00000604, /* P10,P9,P2: OUT */
+ GIO_E0(GIO_H),
+ 0x00001030, /* P44,P37,P36: IN */
+ GIO_E1(GIO_H),
+ 0x00000000, /* (default) */
+ GIO_E0(GIO_HH),
+ 0xc0020100, /* P95,P94,P81,P72:IN */
+ GIO_E1(GIO_HH),
+ 0x00040200, /* P82,P73: OUT */
+ GIO_OL(GIO_L),
+ 0x06040000, /* P10,P9,P2=0 */
+ GIO_OL(GIO_HH),
+ 0x02000000, /* P73=0 */
+ GIO_OH(GIO_HH),
+ 0x00040000, /* P82=0 */
+
+ 0x00000000, /* (terminate) */
+ 0x00000000,
+};
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/cpuctrl.c b/tkernel_source/monitor/hwdepend/arm/mach-acd2/cpuctrl.c
new file mode 100644
index 0000000..2580cef
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-acd2/cpuctrl.c
@@ -0,0 +1,82 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * cpuctrl.c
+ *
+ * ARM CPU control
+ */
+
+#include "sysdepend.h"
+
+/*
+ * Location of the 1st level page table
+ */
+EXPORT UW* const TopPageTable = (UW*)PAGETBL_BASE;
+
+/* ------------------------------------------------------------------------ */
+/*
+ * cache control
+ * acts on the whole address space.
+ */
+
+/*
+ * turn on cache
+ */
+EXPORT void EnableCache( void )
+{
+ setCacheMMU(ENB_CACHEMMU);
+}
+
+/*
+ * turn off cache
+ */
+EXPORT void DisableCache( void )
+{
+ /* MMU can NOT be turned off with this CPU. */
+ setCacheMMU(DIS_CACHEONLY);
+}
+
+/* ------------------------------------------------------------------------ */
+/*
+ * processing on monitor entry
+ */
+
+/*
+ * entry
+ * info, return value is meaningless
+ */
+EXPORT W enterMonitor( UW info )
+{
+ /* cache and MMU is flushed */
+ setCacheMMU(ENB_CACHEMMU);
+
+ return 0;
+}
+
+/*
+ * exit
+ * only in the case of system control processor (CP15)
+ * info is the cache and MMU mode
+ * return value is meaningless
+ */
+EXPORT W leaveMonitor( UW info )
+{
+ /* restore cache && MMU to the original state. */
+ setCacheMMU(info);
+
+ return 0;
+}
+
+/* ------------------------------------------------------------------------ */
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/diskio.c b/tkernel_source/monitor/hwdepend/arm/mach-acd2/diskio.c
new file mode 100644
index 0000000..aa730c4
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-acd2/diskio.c
@@ -0,0 +1,250 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * diskio.c
+ *
+ * Disk I/O
+ */
+
+#include "hwdepend.h"
+#include <device/disk.h>
+
+/*
+ * misaligned data is read as a little-endian data
+ */
+#define GMW(vp) ( (UW)((UB*)vp)[0] \
+ | (UW)((UB*)vp)[1] << 8 \
+ | (UW)((UB*)vp)[2] << 16 \
+ | (UW)((UB*)vp)[3] << 24 )
+#define GMH(vp) ( (UH)((UB*)vp)[0] \
+ | (UH)((UB*)vp)[1] << 8 )
+
+/*
+ * control block for a disk drive
+ * When their number is smaller than the number of disks,
+ * already used block is re-used in place of missing block after it is cleared
+ */
+#define N_DISKCB 3
+LOCAL struct dcblist {
+ const CFGDISK *cfg; /* target device */
+ DISKCB dcb;
+} dcbList[N_DISKCB];
+
+LOCAL W last_dcb = 0; /* the last allocated number from dcbList */
+
+/*
+ * allocating a disk control block
+ */
+LOCAL DISKCB* getDISKCB( const CFGDISK *cfg )
+{
+ W i, n;
+ DISKCB *dcb;
+
+ /* searching for disk drive control block */
+ n = last_dcb;
+ do {
+ i = n;
+ if ( dcbList[i].cfg == cfg ) break;
+ if ( ++n >= N_DISKCB ) n = 0;
+ } while ( n != last_dcb );
+ dcb = &dcbList[i].dcb;
+ last_dcb = i;
+ if ( dcbList[i].cfg != cfg ) {
+ /* re-use after clear */
+ memset(dcb, 0, sizeof(DISKCB));
+ dcbList[i].cfg = cfg;
+ }
+
+ return dcb;
+}
+
+/*
+ * search for a device
+ * return the configuration information of device (indicated by devnm) to cfg_p.
+ * return value is a partition number or error.
+ */
+LOCAL W searchDevice( const UB *devnm, const CFGDISK **cfg_p )
+{
+ UB name[L_DEVNM + 1];
+ W i, pno, c;
+
+ /* checking device name */
+ strncpy(name, devnm, L_DEVNM + 1);
+ if ( name[L_DEVNM] != '\0' ) return E_PAR;
+ i = strlen(name);
+ if ( i <= 0 ) return E_PAR;
+
+ /* check for logical device (partition: 0-3) */
+ pno = 0;
+ c = name[i - 1];
+ if ( c >= '0' && c <='3' ) {
+ if ( --i <= 0 ) return E_PAR;
+ name[i] = '\0'; /* partition number is removed */
+ pno = c - '0' + 1; /* partition number (1 - ) */
+ }
+
+ /* search for a device */
+ for ( i = 0; i < N_ConfigDisk; i++ ) {
+ if ( strncmp(name, ConfigDisk[i].name, L_DEVNM) == 0 ) break;
+ }
+ if ( i >= N_ConfigDisk ) return E_NOEXS;
+
+ *cfg_p = &ConfigDisk[i];
+ return pno;
+}
+
+/*
+ * obtain partition information
+ */
+LOCAL ER readPart( DISKCB *dcb )
+{
+ DiskBlock0 buf;
+ W i, pno;
+ ER err;
+
+ dcb->boot = 0;
+
+ /* if an unexpected disk block size is seen, raise an error */
+ if ( dcb->blksz != sizeof(buf) ) return E_NOSPT;
+
+ /* read master boot record */
+ err = (*dcb->rwdisk)(dcb, 0, 1, &buf, FALSE);
+ if ( err < E_OK ) return err;
+
+ /* check the signature in the boot block */
+ if ( GMH(&buf.signature) != 0xaa55 ) return E_OK; /* no partition */
+
+ /* obtain partition information */
+ for ( i = 0; i < MAX_PARTITION; i++ ) {
+ pno = i + 1;
+ dcb->part[pno].sblk = GMW(buf.part[i].StartBlock);
+ dcb->part[pno].nblk = GMW(buf.part[i].BlockCnt);
+
+ if ( buf.part[i].BootInd == 0x80
+ && dcb->part[pno].nblk > 0
+ && dcb->boot == 0 ) dcb->boot = pno;
+ }
+
+ return E_OK;
+}
+
+/*
+ * open disk (obtain disk drive control block)
+ * open a device indicated by `devnm', and return the disk information in `dcb'.
+ * devnm can specify a device name with partition number.
+ * return the partition number specified by devnm.
+ * return value 0 : entire disks
+ * 1 - : partition number
+ * < 0 : error
+ */
+EXPORT W openDisk( const UB *devnm, DISKCB **dcb_p )
+{
+ const CFGDISK *cfg;
+ DISKCB *dcb;
+ W pno;
+ ER err;
+
+ /* search for a device */
+ pno = searchDevice(devnm, &cfg);
+ if ( pno < E_OK ) return pno;
+
+ /* allocating a disk control block */
+ dcb = getDISKCB(cfg);
+
+ /* initialize disk */
+ err = (*cfg->initdisk)(dcb, cfg);
+ if ( err < E_OK ) return err;
+ if ( dcb->blksz == 0 ) return E_NOMDA;
+
+ if ( dcb->boot == 0xff ) {
+ /* read the partition information */
+ err = readPart(dcb);
+ if ( err < E_OK ) return err;
+ }
+
+ *dcb_p = dcb;
+ return pno;
+}
+
+/*
+ * disk access
+ * devnm device name (possibly with the partition number)
+ * blk start block number
+ * if device name has a partition number, then the block number in that partition
+ * if there is no partition number in the disk anme, the block number in the entire disk
+ * nblk number of blocks
+ * buf buffer (* )
+ * wrt FALSE : read
+ * TRUE : write
+ * return value error code
+ * argument marked with (* ) may be an address specified from external sources.
+ */
+EXPORT ER rwDisk( const UB *devnm, W blk, W nblk, void *buf, BOOL wrt )
+{
+ DISKCB *dcb;
+ W pno, nb;
+ ER err;
+
+ /* initialize disk */
+ pno = openDisk(devnm, &dcb);
+ if ( pno < E_OK ) return pno;
+
+ nb = dcb->part[pno].nblk;
+
+ /* range check of the block number */
+ if ( blk < 0 || blk >= nb
+ || nblk <= 0 || nblk > nb - blk ) return E_PAR;
+
+ /* convert the relative block number in a partiton to a block number in the entire disk */
+ blk += dcb->part[pno].sblk;
+
+ /* read from, or write to disk */
+ err = (*dcb->rwdisk)(dcb, blk, nblk, buf, wrt);
+ if ( err < E_OK ) return err;
+
+ return E_OK;
+}
+
+/*
+ * obtain disk information
+ * devnm device name (possibly with the partition number)
+ * blksz return block size (* )
+ * tblks return the number of all blocks (* )
+ * return value error code
+ * if there is a partition number to the device name, return the specific information to that partition.
+ * argument marked with (* ) may be an address specified from external sources.
+ */
+EXPORT ER infoDisk( const UB *devnm, W *blksz, W *tblks )
+{
+ DISKCB *dcb;
+ W pno, buf, n;
+
+ /* initialize disk */
+ pno = openDisk(devnm, &dcb);
+ if ( pno < E_OK ) return pno;
+
+ /* obtain disk information
+ * since there are addresses specified from external source, use writeMem()
+ */
+ buf = dcb->part[pno].nblk;
+ n = writeMem((UW)tblks, &buf, sizeof(W), sizeof(W));
+ if ( n < sizeof(W) ) return E_MACV;
+
+ buf = dcb->blksz;
+ n = writeMem((UW)blksz, &buf, sizeof(W), sizeof(W));
+ if ( n < sizeof(W) ) return E_MACV;
+
+ return E_OK;
+}
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/eitent-interrupts.c b/tkernel_source/monitor/hwdepend/arm/mach-acd2/eitent-interrupts.c
new file mode 100644
index 0000000..e69de29
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/eitproc.c b/tkernel_source/monitor/hwdepend/arm/mach-acd2/eitproc.c
new file mode 100644
index 0000000..b109c95
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-acd2/eitproc.c
@@ -0,0 +1,132 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * eitproc.c
+ *
+ * EIT processing
+ */
+
+#include "sysdepend.h"
+#include <tk/sysdef.h>
+
+/*
+ * vector information
+ */
+typedef struct vecinfo VECINFO;
+struct vecinfo {
+ UW vec; /* initial vector numer */
+ B *msg; /* message */
+
+ /* processing function
+ * return value 1 : adjust PC by decrementing it by one instruction worth
+ * 0 : PC needs no adjustment
+ */
+ W (*func)( const VECINFO*, UW vec, UW pc, UW cpsr );
+};
+
+/* display message */
+LOCAL W vf_msg( const VECINFO *vi, UW vec, UW pc, UW cpsr )
+{
+ B *msg = vi->msg;
+ B opt;
+
+ if ( msg == NULL ) return 0;
+
+ /* if the first byte of the message is not a letter, treat it as option.
+ * opt = 0 - 037 (the code prior to ' ' )
+ * \020 PC is adjusted to the previous instruction's address
+ */
+ opt = 0;
+ if ( *msg < ' ' ) opt = *msg++;
+
+ DSP_F5(S,"Exception ", D,vec, S," (", S,msg, CH,')');
+
+ return ( opt & 020 )? 1: 0;
+}
+
+/* undefined instruction */
+LOCAL W vf_undef( const VECINFO *vi, UW vec, UW pc, UW cpsr )
+{
+ if (cpsr & PSR_T) {
+ DSP_F3(S,vi->msg, CH,' ', 04X,*((UH*)(pc - 2)));
+ } else {
+ DSP_F3(S,vi->msg, CH,' ', 08X,*((UW*)(pc - 4)));
+ }
+ return 1;
+}
+
+/* data abort */
+LOCAL W vf_dabort( const VECINFO *vi, UW vec, UW pc, UW cpsr )
+{
+ DSP_F1(S,vi->msg);
+ DSP_F4(S," ADDR: ", 08X,getCP15(6, 0), S," STAT: ", 08X,getCP15(5, 0));
+ return 0;
+}
+
+/*
+ * vector information table
+ * this has to be filled in the ascending order of the vector number
+ */
+LOCAL const VECINFO VecInfoTable[] = {
+ { 0, "\020" "Undefined SWI", vf_msg },
+ { EIT_UNDEF, "Undefined Instruction", vf_undef },
+ { EIT_IABORT, "Prefetch Abort", vf_msg },
+ { EIT_DABORT, "Data Abort", vf_dabort },
+ { EIT_DABORT+1, "\020" "Undefined SWI", vf_msg },
+
+ { EIT_FIQ, "Undefined FIQ", vf_msg },
+ { EIT_IRQ(0), "Undefined IRQ", vf_msg },
+ { EIT_GPIO(0), "Undefined GPIO-INT", vf_msg },
+ { EIT_GPIO(127)+1,"\020" "Undefined SWI", vf_msg },
+
+ { N_INTVEC, NULL, vf_msg } /* terminating mark (the last vector number + 1) */
+};
+#define N_VECINFO ( sizeof(VecInfoTable) / sizeof(VECINFO) )
+
+/*
+ * EIT processing
+ * * return value 0 : monitor should keep on running
+ * 1 : return from the interrupt handler
+ */
+EXPORT W procEIT( UW vec )
+{
+ const VECINFO *vp;
+ UW pc, cpsr;
+ W i;
+
+ pc = getCurPCX();
+ cpsr = getCurCPSR();
+
+ /* machine-dependent interrupt processing */
+ i = procHwInt(vec);
+ if ( i == 2 ) return 1; /* exit from the interrupt handler immediately */
+
+ if ( i == 0 ) {
+ /* other EIT processing */
+ for ( i = 1; i < N_VECINFO; ++i ) {
+ if ( vec < VecInfoTable[i].vec ) break;
+ }
+ vp = &VecInfoTable[i-1];
+ i = (*vp->func)(vp, vec, pc, cpsr);
+ if ( i > 0 ) {
+ /* PC is adjusted to the previous instruction's address */
+ pc -= ( (cpsr & PSR_T) != 0 )? 2: 4;
+ }
+ }
+
+ DSP_F5(S,"\nPC: ", 08X,pc, S," CPSR: ", 08X,cpsr, CH,'\n');
+
+ return 0;
+}
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/hwdepend.h b/tkernel_source/monitor/hwdepend/arm/mach-acd2/hwdepend.h
new file mode 100644
index 0000000..0e98fe0
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-acd2/hwdepend.h
@@ -0,0 +1,63 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * hwdepend.h
+ *
+ * T-Monitor hardware-dependent processing
+ */
+
+#ifndef __MONITOR_CMDSVC_HWDEPEND_H__
+#define __MONITOR_CMDSVC_HWDEPEND_H__
+
+#include <tmonitor.h>
+#include "sysdepend.h"
+
+IMPORT UW DipSw; /* dip switch status */
+
+/*
+ * system configuration information
+ */
+IMPORT MEMSEG MemSeg[]; /* memory area definition */
+IMPORT W N_MemSeg; /* number of memory areas */
+
+IMPORT const CFGSIO ConfigSIO[]; /* serial port configuration definition */
+IMPORT const W N_ConfigSIO; /* serial port number */
+
+IMPORT const CFGDISK ConfigDisk[]; /* disk drive configuration definition */
+IMPORT const W N_ConfigDisk; /* nuber of disk drives */
+
+/*
+ * initial processing after reset
+ */
+IMPORT void procReset( void );
+
+/*
+ * initialize hardware (peripherals)
+ */
+IMPORT void initHardware( void );
+
+/*
+ * setting up the initial count for micro-wait()
+ */
+IMPORT void setupWaitUsec( void );
+
+/*
+ * obtain the console port number
+ * console port number (0 - )
+ * if there is no console port, return -1.
+ */
+IMPORT W getConPort( void );
+
+#endif /* __MONITOR_CMDSVC_HWDEPEND_H__ */
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/hwinfo.c b/tkernel_source/monitor/hwdepend/arm/mach-acd2/hwinfo.c
new file mode 100644
index 0000000..3ef3db8
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-acd2/hwinfo.c
@@ -0,0 +1,147 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * hwinfo.c
+ *
+ * hardware configuration information
+ */
+
+#include "hwdepend.h"
+
+/* ------------------------------------------------------------------------ */
+/*
+ * memory region definition
+ */
+
+/*
+ * obtaining memory region information
+ * no = 1 - (and up)
+ * 'no'-th information in the region specified by the attr is returned.
+ * if attr = 0, no matter what the attribute is, 'no'-th information is returned unconditionally.
+ * If there was no such information, return NULL.
+ */
+EXPORT MEMSEG* MemArea( UW attr, W no )
+{
+ MEMSEG *mp;
+ W i;
+
+ if ( attr == 0 ) {
+ i = no - 1;
+ return ( i >= 0 && i < N_MemSeg )? &MemSeg[i]: NULL;
+ }
+
+ for ( i = 0; i < N_MemSeg; ++i ) {
+ mp = &MemSeg[i];
+ if ( (mp->attr & attr) != 0 ) {
+ if ( --no <= 0 ) return mp;
+ }
+ }
+
+ return NULL;
+}
+
+/*
+ * obtaining memory region information (specify address)
+ * within the region specified by `attr', return the information that surrounds the position specified by `addr'.
+ *
+ * if no such information is found, return NULL.
+ */
+EXPORT MEMSEG* AddrMatchMemArea( UW addr, UW attr )
+{
+ MEMSEG *mp;
+ W i;
+
+ for ( i = 0; i < N_MemSeg; ++i ) {
+ mp = &MemSeg[i];
+ if ( (mp->attr & attr) == 0 ) continue;
+
+ if ( addr >= mp->top && addr <= mp->end-1 ) return mp;
+ }
+
+ return NULL;
+}
+
+/*
+ * Decide whether two memory regions are included in another.
+ * if the region, from `top' to `end', is completely included in the region specified by `attr',
+ * TRUE
+ * the location of end is NOT included in the region (end - top) is the region size
+ * end = 0x00000000, by the way, means 0x100000000.
+ */
+EXPORT BOOL inMemArea( UW top, UW end, UW attr )
+{
+ const MEMSEG *mp;
+ W i;
+
+ for ( i = 0; i < N_MemSeg; ++i ) {
+ mp = &MemSeg[i];
+ if ( (mp->attr & attr) == 0 ) continue;
+
+ if ( top >= mp->top && end-1 <= mp->end-1 ) return TRUE;
+ }
+ return FALSE;
+}
+
+/*
+ * Decide whether two memory regions overlap with each other
+ * if the area, from top to end, is included even partially in the region specified by `attr' - 'end',
+ * it is TRUE
+ * the location of end is NOT included in the region (end - top) is the region size
+ * end = 0x00000000, by the way, means 0x100000000.
+ */
+EXPORT BOOL isOverlapMemArea( UW top, UW end, UW attr )
+{
+ const MEMSEG *mp;
+ W i;
+
+ for ( i = 0; i < N_MemSeg; ++i ) {
+ mp = &MemSeg[i];
+ if ( (mp->attr & attr) == 0 ) continue;
+
+ if ( top <= mp->end-1 && end-1 >= mp->top ) return TRUE;
+ }
+ return FALSE;
+}
+
+/* ------------------------------------------------------------------------ */
+/*
+ * boot device following the standard boot order
+ * return the device name that is the 'no'-th device in the standard boot order.
+ *
+ * if no such device name exists (when 'no' is given as a value larger or equal to the last number), it is NULL.
+ */
+EXPORT const UB* bootDevice( W no )
+{
+ if ( no < 0 || no >= N_ConfigDisk ) return NULL;
+
+ return ConfigDisk[no].name;
+}
+
+/*
+ * list of disk drives
+ * returns the disk drive device name, indicated by 'no' ( 0 - : a consecutive number )
+ * if no such device name exists (when 'no' is given as a value larger or equal to the last number), it is NULL.
+ * if attr is not NULL, disk driver attribute returns in `attr' )
+ */
+EXPORT const UB* diskList( W no, UW *attr )
+{
+ if ( no < 0 || no >= N_ConfigDisk ) return NULL;
+
+ if ( attr != NULL ) *attr = ConfigDisk[no].attr;
+
+ return ConfigDisk[no].name;
+}
+
+/* ------------------------------------------------------------------------ */
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/include/mach/cpudepend.h b/tkernel_source/monitor/hwdepend/arm/mach-acd2/include/mach/cpudepend.h
new file mode 100644
index 0000000..4cbb714
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-acd2/include/mach/cpudepend.h
@@ -0,0 +1,96 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * cpudepend.h
+ *
+ * ARM-related definitions
+ */
+
+#ifndef __MONITOR_ARM_CPUDEPEND_H__
+#define __MONITOR_ARM_CPUDEPEND_H__
+
+#include <machine.h>
+
+/*
+ * monitor stack area
+ * stack area is from &__stack_top to &__stack_bottom
+ * initial stack pointer = &__stack_bottom
+ */
+IMPORT UB __stack_top, __stack_bottom;
+
+/*
+ * first level page table
+ */
+IMPORT UW* const TopPageTable; /* location of page table */
+#define N_PageTableEntry 0x1000 /* number of entries */
+
+/*
+ * address conversion to non-cached and cached area
+ * in the case of ARM, all address have the same cache mode, and hence
+ * return as it is.
+ */
+#define NOCACHE_ADDR(p) (p)
+#define CACHE_ADDR(p) (p)
+
+/*
+ * I/O port access functions
+ */
+Inline void out_w( INT port, UW data )
+{
+ *(_UW*)port = data;
+}
+Inline void out_h( INT port, UH data )
+{
+ *(_UH*)port = data;
+}
+Inline void out_b( INT port, UB data )
+{
+ *(_UB*)port = data;
+}
+
+Inline UW in_w( INT port )
+{
+ return *(_UW*)port;
+}
+Inline UH in_h( INT port )
+{
+ return *(_UH*)port;
+}
+Inline UB in_b( INT port )
+{
+ return *(_UB*)port;
+}
+
+/*
+ * value of control register (r1) of system control coprocessor cp15
+ */
+#if CPU_ARM1176
+#define MASK_CACHEMMU (0xFFFFCC78) /* V,I,R,S,C,A,M (B = 0) */
+#define VALID_CACHEMMU (0x3307) /* B = 0 */
+#define DIS_CACHEMMU (0x0000) /* I=0,R=0,S=0,C=0,A=0,M=0 */
+#define DIS_CACHEONLY (0x0001) /* I=0,R=0,S=0,C=0,A=0,M=1 */
+#define ENB_CACHEMMU (0x1007) /* I=1,R=0,S=0,C=1,A=1,M=1 */
+#define ENB_MMUONLY (0x0003) /* I=0,R=0,S=0,C=0,A=1,M=1 */
+#endif
+
+/*
+ * references registers under monitor control
+ * references the value of registers at the time of monitor entry.
+ */
+IMPORT UW getCP15( W reg, W opcd ); /* CP15 register CRn: reg, Op2: opcd */
+IMPORT UW getCurPCX( void ); /* PC register (raw value) */
+IMPORT UW getCurCPSR( void ); /* CPSR register */
+
+#endif /* __MONITOR_ARM_CPUDEPEND_H__ */
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/include/mach/em1d512.h b/tkernel_source/monitor/hwdepend/arm/mach-acd2/include/mach/em1d512.h
new file mode 100644
index 0000000..b1eb46f
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-acd2/include/mach/em1d512.h
@@ -0,0 +1,464 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * em1d.h
+ *
+ * EMMA Mobile(TM)1-D register definitions (excerpt)
+ *
+ * * this is included from assembler program source files
+ */
+
+#ifndef __MONITOR_ARM_EM1D_H__
+#define __MONITOR_ARM_EM1D_H__
+
+#include <tk/sysdef.h>
+
+#define AB0Base 0x2fff0000
+#define AB0_FLASHCOMSET (AB0Base + 0x0000)
+#define AB0_FLASHCOMLATCH (AB0Base + 0x0004)
+#define AB0_FLASHCOMADD0 (AB0Base + 0x0010)
+#define AB0_FLASHCOMDATA0 (AB0Base + 0x0014)
+#define AB0_FLASHCOMADD1 (AB0Base + 0x0018)
+#define AB0_FLASHCOMDATA1 (AB0Base + 0x001c)
+#define AB0_FLASHCLKCTRL (AB0Base + 0x0080)
+#define AB0_FLA_RCLK_DLY (AB0Base + 0x0084)
+#define AB0_WAIT_STATUS (AB0Base + 0x0090)
+#define AB0_CSnBASEADD(n) (AB0Base + 0x0100 + 0x0010 * (n))
+#define AB0_CSnBITCOMP(n) (AB0Base + 0x0104 + 0x0010 * (n))
+#define AB0_CSnWAITCTRL(n) (AB0Base + 0x0200 + 0x0020 * (n))
+#define AB0_CSnWAITCTRL_W(n) (AB0Base + 0x0204 + 0x0020 * (n))
+#define AB0_CSnREADCTRL(n) (AB0Base + 0x0208 + 0x0020 * (n))
+#define AB0_CSnWAIT_MASK(n) (AB0Base + 0x020c + 0x0020 * (n))
+#define AB0_CSnCONTROL(n) (AB0Base + 0x0210 + 0x0020 * (n))
+#define AB0_CSnFLASHRCR(n) (AB0Base + 0x0214 + 0x0020 * (n))
+#define AB0_CSnFLASHWCR(n) (AB0Base + 0x0218 + 0x0020 * (n))
+#define AB0_CSnWAITCTRL2(n) (AB0Base + 0x0300 + 0x0020 * (n))
+#define AB0_CSnWAITCTRL_W2(n) (AB0Base + 0x0304 + 0x0020 * (n))
+#define AB0_CSnREADCTRL2(n) (AB0Base + 0x0308 + 0x0020 * (n))
+#define AB0_CSnWAIT_MASK2(n) (AB0Base + 0x030c + 0x0020 * (n))
+#define AB0_CSnCONTROL2(n) (AB0Base + 0x0310 + 0x0020 * (n))
+#define AB0_CSnFLASHRCR2(n) (AB0Base + 0x0314 + 0x0020 * (n))
+#define AB0_CSnFLASHWCR2(n) (AB0Base + 0x0318 + 0x0020 * (n))
+
+#define LCDBase 0x40270000
+#define LCD_CONTROL (LCDBase + 0x0000)
+#define LCD_QOS (LCDBase + 0x0004)
+#define LCD_DATAREQ (LCDBase + 0x0008)
+#define LCD_LCDOUT (LCDBase + 0x0010)
+#define LCD_BUSSEL (LCDBase + 0x0014)
+#define LCD_STATUS (LCDBase + 0x0018)
+#define LCD_BACKCOLOR (LCDBase + 0x001c)
+#define LCD_AREAADR (LCDBase + 0x0020)
+#define LCD_HOFFSET (LCDBase + 0x0024)
+#define LCD_IFORMAT (LCDBase + 0x0028)
+#define LCD_RESIZE (LCDBase + 0x002c)
+#define LCD_HTOTAL (LCDBase + 0x0030)
+#define LCD_HAREA (LCDBase + 0x0034)
+#define LCD_HEDGE1 (LCDBase + 0x0038)
+#define LCD_HEDGE2 (LCDBase + 0x003c)
+#define LCD_VTOTAL (LCDBase + 0x0040)
+#define LCD_VAREA (LCDBase + 0x0044)
+#define LCD_VEDGE1 (LCDBase + 0x0048)
+#define LCD_VEDGE2 (LCDBase + 0x004c)
+#define LCD_INTSTATUS (LCDBase + 0x0060)
+#define LCD_INTRAWSTATUS (LCDBase + 0x0064)
+#define LCD_INTENSET (LCDBase + 0x0068)
+#define LCD_INTENCLR (LCDBase + 0x006c)
+#define LCD_INTFFCLR (LCDBase + 0x0070)
+#define LCD_FRAMECNT (LCDBase + 0x0074)
+
+#define UARTnBase(n) (0x50000000 + 0x00010000 * (n))
+#define UART0 0x00
+#define UART1 0x01
+#define UART2 0x02
+/* omitted */
+
+#define SDIxBase(x) (0x50050000 + 0x00010000 * (x))
+#define SDIA 0x00
+#define SDIB 0x01
+#define SDIC 0x04
+#define SDIx_CMD(x) (SDIxBase(x) + 0x0000)
+#define SDIx_PORT(x) (SDIxBase(x) + 0x0004)
+#define SDIx_ARG0(x) (SDIxBase(x) + 0x0008)
+#define SDIx_ARG1(x) (SDIxBase(x) + 0x000c)
+#define SDIx_STOP(x) (SDIxBase(x) + 0x0010)
+#define SDIx_SECCNT(x) (SDIxBase(x) + 0x0014)
+#define SDIx_RSP0(x) (SDIxBase(x) + 0x0018)
+#define SDIx_RSP1(x) (SDIxBase(x) + 0x001c)
+#define SDIx_RSP2(x) (SDIxBase(x) + 0x0020)
+#define SDIx_RSP3(x) (SDIxBase(x) + 0x0024)
+#define SDIx_RSP4(x) (SDIxBase(x) + 0x0028)
+#define SDIx_RSP5(x) (SDIxBase(x) + 0x002c)
+#define SDIx_RSP6(x) (SDIxBase(x) + 0x0030)
+#define SDIx_RSP7(x) (SDIxBase(x) + 0x0034)
+#define SDIx_INFO1(x) (SDIxBase(x) + 0x0038)
+#define SDIx_INFO2(x) (SDIxBase(x) + 0x003c)
+#define SDIx_INFO1_MASK(x) (SDIxBase(x) + 0x0040)
+#define SDIx_INFO2_MASK(x) (SDIxBase(x) + 0x0044)
+#define SDIx_CLK_CTRL(x) (SDIxBase(x) + 0x0048)
+#define SDIx_SIZE(x) (SDIxBase(x) + 0x004c)
+#define SDIx_OPTION(x) (SDIxBase(x) + 0x0050)
+#define SDIx_ERR_STS1(x) (SDIxBase(x) + 0x0058)
+#define SDIx_ERR_STS2(x) (SDIxBase(x) + 0x005c)
+#define SDIx_BUF0(x) (SDIxBase(x) + 0x0060)
+#define SDIx_SDIO_MODE(x) (SDIxBase(x) + 0x0068)
+#define SDIx_SDIO_INFO1(x) (SDIxBase(x) + 0x006c)
+#define SDIx_SDIO_INFO1_MASK(x) (SDIxBase(x) + 0x0070)
+#define SDIx_CC_EXT_MODE(x) (SDIxBase(x) + 0x01b0)
+#define SDIx_SOFT_RST(x) (SDIxBase(x) + 0x01c0)
+#define SDIx_VERSION(x) (SDIxBase(x) + 0x01c4)
+#define SDIx_USER(x) (SDIxBase(x) + 0x0200)
+#define SDIx_USER2(x) (SDIxBase(x) + 0x0204)
+#define SDIx_DMA(x) (SDIxBase(x) + 0x0300)
+
+#define AB1Base 0x50070000
+#define AB1_ERROR (AB1Base + 0x0000)
+#define AB1_GENERAL (AB1Base + 0x0004)
+#define AB1_DEBUG0 (AB1Base + 0x0008)
+
+#define USBBase 0x60000000
+/* omitted */
+
+#define TimerBase(x) (0xc0000000 + 0x00000100 * (x))
+#define TI0 0x00
+#define TI1 0x01
+#define TI2 0x02
+#define TI3 0x03
+#define TW0 0x10
+#define TW1 0x11
+#define TW2 0x12
+#define TW3 0x13
+#define TG0 0x20
+#define TG1 0x21
+#define TG2 0x22
+#define TG3 0x23
+#define TG4 0x24
+#define TG5 0x25
+#define Txx_OP(x) (TimerBase(x) + 0x0000)
+#define Txx_CLR(x) (TimerBase(x) + 0x0004)
+#define Txx_SET(x) (TimerBase(x) + 0x0008)
+#define Txx_RCR(x) (TimerBase(x) + 0x000c)
+#define Txx_SCLR(x) (TimerBase(x) + 0x0014)
+
+#define AINTBase 0xc0020000
+#define IT0_IEN0 (AINTBase + 0x0000)
+#define IT0_IEN1 (AINTBase + 0x0004)
+#define IT0_IDS0 (AINTBase + 0x0008)
+#define IT0_IDS1 (AINTBase + 0x000c)
+#define IT0_RAW0 (AINTBase + 0x0010)
+#define IT0_RAW1 (AINTBase + 0x0014)
+#define IT0_MST0 (AINTBase + 0x0018)
+#define IT0_MST1 (AINTBase + 0x001c)
+#define IT0_IIR (AINTBase + 0x0024)
+#define IT0_IPI3_SET (AINTBase + 0x003c)
+#define IT3_IPI0_CLR (AINTBase + 0x005c)
+#define IT0_FIE (AINTBase + 0x0080)
+#define IT0_FID (AINTBase + 0x0084)
+#define IT0_IEN2 (AINTBase + 0x0100)
+#define IT0_IDS2 (AINTBase + 0x0104)
+#define IT0_RAW2 (AINTBase + 0x0108)
+#define IT0_MST2 (AINTBase + 0x010c)
+#define IT_PINV_SET0 (AINTBase + 0x0300)
+#define IT_PINV_SET1 (AINTBase + 0x0304)
+#define IT_PINV_SET2 (AINTBase + 0x0308)
+#define IT_PINV_CLR0 (AINTBase + 0x0310)
+#define IT_PINV_CLR1 (AINTBase + 0x0314)
+#define IT_PINV_CLR2 (AINTBase + 0x0318)
+#define IT0_LIIS (AINTBase + 0x0320)
+#define IT0_LIIR (AINTBase + 0x0324)
+#define IT3_IEN0 (AINTBase + 0xc000)
+#define IT3_IEN1 (AINTBase + 0xc004)
+#define IT3_IDS0 (AINTBase + 0xc008)
+#define IT3_IDS1 (AINTBase + 0xc00c)
+#define IT3_RAW0 (AINTBase + 0xc010)
+#define IT3_RAW1 (AINTBase + 0xc014)
+#define IT3_MST0 (AINTBase + 0xc018)
+#define IT3_MST1 (AINTBase + 0xc01c)
+#define IT3_IIR (AINTBase + 0xc024)
+#define IT3_IPI0_SET (AINTBase + 0xc030)
+#define IT0_IPI3_CLR (AINTBase + 0xc050)
+#define ID_VBS (AINTBase + 0xc090)
+#define ID_CLR (AINTBase + 0xc094)
+#define IT3_IEN2 (AINTBase + 0xc100)
+#define IT3_IDS2 (AINTBase + 0xc104)
+#define IT3_RAW2 (AINTBase + 0xc108)
+#define IT3_MST2 (AINTBase + 0xc10c)
+
+#define ASINTBase 0xcc010000
+#define IT0_IENS0 (ASINTBase + 0xe200)
+#define IT0_IENS1 (ASINTBase + 0xe204)
+#define IT0_IENS2 (ASINTBase + 0xe208)
+#define IT0_IDSS0 (ASINTBase + 0xe20c)
+#define IT0_IDSS1 (ASINTBase + 0xe210)
+#define IT0_IDSS2 (ASINTBase + 0xe214)
+
+#define GIOBase(x) (0xc0050000 + 0x00000040 * (x))
+#define GIO_L 0x00
+#define GIO_H 0x01
+#define GIO_HH 0x02
+#define GIO_HHH 0x08
+#define GIO_E1(x) (GIOBase(x) + 0x0000)
+#define GIO_E0(x) (GIOBase(x) + 0x0004)
+#define GIO_EM(x) (GIOBase(x) + 0x0004)
+#define GIO_OL(x) (GIOBase(x) + 0x0008)
+#define GIO_OH(x) (GIOBase(x) + 0x000c)
+#define GIO_I(x) (GIOBase(x) + 0x0010)
+#define GIO_IIA(x) (GIOBase(x) + 0x0014)
+#define GIO_IEN(x) (GIOBase(x) + 0x0018)
+#define GIO_IDS(x) (GIOBase(x) + 0x001c)
+#define GIO_IIM(x) (GIOBase(x) + 0x001c)
+#define GIO_RAW(x) (GIOBase(x) + 0x0020)
+#define GIO_MST(x) (GIOBase(x) + 0x0024)
+#define GIO_IIR(x) (GIOBase(x) + 0x0028)
+#define GIO_GSW(x) (GIOBase(x) + 0x003c)
+#define GIO_IDT0(x) (GIOBase(x) + 0x0100)
+#define GIO_IDT1(x) (GIOBase(x) + 0x0104)
+#define GIO_IDT2(x) (GIOBase(x) + 0x0108)
+#define GIO_IDT3(x) (GIOBase(x) + 0x010c)
+#define GIO_RAWBL(x) (GIOBase(x) + 0x0110)
+#define GIO_RAWBH(x) (GIOBase(x) + 0x0114)
+#define GIO_IRBL(x) (GIOBase(x) + 0x0118)
+#define GIO_IRBH(x) (GIOBase(x) + 0x011c)
+
+#define MEMCBase 0xc00a0000
+#define MEMC_CACHE_MODE (MEMCBase + 0x0000)
+#define MEMC_DEGFUN (MEMCBase + 0x0008)
+#define MEMC_INTSTATUS_A (MEMCBase + 0x0014)
+#define MEMC_INTRAWSTATUS_A (MEMCBase + 0x0018)
+#define MEMC_INTENSET_A (MEMCBase + 0x001c)
+#define MEMC_INTENCLR_A (MEMCBase + 0x0020)
+#define MEMC_INTFFCLR_A (MEMCBase + 0x0024)
+#define MEMC_ERRMID (MEMCBase + 0x0068)
+#define MEMC_ERRADR (MEMCBase + 0x006c)
+#define MEMC_REQSCH (MEMCBase + 0x1000)
+#define MEMC_DDR_CONFIGF (MEMCBase + 0x2000)
+#define MEMC_DDR_CONFIGA1 (MEMCBase + 0x2004)
+#define MEMC_DDR_CONFIGA2 (MEMCBase + 0x2008)
+#define MEMC_DDR_CONFIGC1 (MEMCBase + 0x200c)
+#define MEMC_DDR_CONFIGC2 (MEMCBase + 0x2010)
+#define MEMC_DDR_CONFIGR1 (MEMCBase + 0x2014)
+#define MEMC_DDR_CONFIGR2 (MEMCBase + 0x2018)
+#define MEMC_DDR_CONFIGR3 (MEMCBase + 0x201c)
+#define MEMC_DDR_CONFIGT1 (MEMCBase + 0x2020)
+#define MEMC_DDR_CONFIGT2 (MEMCBase + 0x2024)
+#define MEMC_DDR_CONFIGT3 (MEMCBase + 0x2028)
+#define MEMC_DDR_STATE8 (MEMCBase + 0x202c)
+
+#define PMUBase 0xc0100000
+#define PMU_PC (PMUBase + 0x0004)
+#define PMU_START (PMUBase + 0x0008)
+#define PMU_POWER_ON_PC (PMUBase + 0x0030)
+#define PMU_WDT_COUNT_EN (PMUBase + 0x0060)
+#define PMU_WDT_COUNT_LMT (PMUBase + 0x0064)
+#define PMU_INT_HANDLER_PC (PMUBase + 0x0068)
+#define PMU_PSR (PMUBase + 0x0070)
+#define PMU_TRIG_STATUS (PMUBase + 0x0074)
+#define PMU_REGA (PMUBase + 0x0078)
+#define PMU_REGB (PMUBase + 0x007c)
+#define PMU_INTSTATUS_A (PMUBase + 0x0080)
+#define PMU_INTRAWSTATUS_A (PMUBase + 0x0084)
+#define PMU_INTENSET_A (PMUBase + 0x0088)
+#define PMU_INTENCLR_A (PMUBase + 0x008c)
+#define PMU_INTFFCLR_A (PMUBase + 0x0090)
+#define PMU_PCERR (PMUBase + 0x00a8)
+#define PMU_CMD_BUF_RAM (PMUBase + 0x1000)
+#define PMU_CMD_BUF_FF (PMUBase + 0x2000)
+
+#define ASMUBase 0xc0110000
+#define RESETCTRL0 (ASMUBase + 0x0000)
+#define RESETREQ0 (ASMUBase + 0x0004)
+#define RESETREQ0ENA (ASMUBase + 0x0008)
+#define RESETREQ1 (ASMUBase + 0x000c)
+#define RESETREQ1ENA (ASMUBase + 0x0010)
+#define RESETREQ2 (ASMUBase + 0x0018)
+#define RESETREQ2ENA (ASMUBase + 0x001c)
+#define WDT_INT_RESET (ASMUBase + 0x0020)
+#define RESET_PCLK_COUNT (ASMUBase + 0x0024)
+#define AUTO_MODE_EN (ASMUBase + 0x007c)
+#define CLK_MODE_SEL (ASMUBase + 0x0080)
+#define PLL1CTRL0 (ASMUBase + 0x0084)
+#define PLL1CTRL1 (ASMUBase + 0x0088)
+#define PLL2CTRL0 (ASMUBase + 0x008c)
+#define PLL2CTRL1 (ASMUBase + 0x0090)
+#define PLL3CTRL0 (ASMUBase + 0x0094)
+#define PLL3CTRL1 (ASMUBase + 0x0098)
+#define PLLLOCKTIME (ASMUBase + 0x009c)
+#define AUTO_PLL_STANDBY (ASMUBase + 0x00a8)
+#define PLLVDDWAIT (ASMUBase + 0x00b4)
+#define CLKSTOPSIG_ST (ASMUBase + 0x00c4)
+#define CLK32_STATUS (ASMUBase + 0x00c8)
+#define POWER_RECORD (ASMUBase + 0x00cc)
+#define ASMU_INT_STATUS (ASMUBase + 0x00d0)
+#define ASMU_INT_RAW_STATUS (ASMUBase + 0x00d4)
+#define ASMU_INT_ENSET (ASMUBase + 0x00d8)
+#define ASMU_INT_ENCLR (ASMUBase + 0x00dc)
+#define ASMU_INT_ENMON (ASMUBase + 0x00e0)
+#define ASMU_INT_CLEAR (ASMUBase + 0x00e4)
+#define NORMALA_DIV (ASMUBase + 0x00f0)
+#define NORMALB_DIV (ASMUBase + 0x00f4)
+#define NORMALC_DIV (ASMUBase + 0x00f8)
+#define NORMALD_DIV (ASMUBase + 0x00fc)
+#define ECONOMY_DIV (ASMUBase + 0x0100)
+#define STANDBY_DIV (ASMUBase + 0x0104)
+#define POWERON_DIV (ASMUBase + 0x0108)
+#define DIVSP0SCLK (ASMUBase + 0x0118)
+#define DIVSP1SCLK (ASMUBase + 0x011c)
+#define DIVSP2SCLK (ASMUBase + 0x0120)
+#define DIVMEMCRCLK (ASMUBase + 0x0128)
+#define DIVCAMSCLK (ASMUBase + 0x012c)
+#define DIVLCDLCLK (ASMUBase + 0x0130)
+#define DIVIICSCLK (ASMUBase + 0x0134)
+#define TI0TIN_SEL (ASMUBase + 0x0138)
+#define TI1TIN_SEL (ASMUBase + 0x013c)
+#define TI2TIN_SEL (ASMUBase + 0x0140)
+#define TI3TIN_SEL (ASMUBase + 0x0144)
+#define TIGnTIN_SEL (ASMUBase + 0x0148)
+#define DIVTIMTIN (ASMUBase + 0x014c)
+#define DIVMWISCLK (ASMUBase + 0x0150)
+#define DIVDMATCLK (ASMUBase + 0x0154)
+#define DIVU70SCLK (ASMUBase + 0x0158)
+#define DIVU71SCLK (ASMUBase + 0x015c)
+#define DIVU72SCLK (ASMUBase + 0x0160)
+#define DIVPM0SCLK (ASMUBase + 0x016c)
+#define DIVPM1SCLK (ASMUBase + 0x0170)
+#define DIVREFCLK (ASMUBase + 0x0178)
+#define DIVPWMPWCLK (ASMUBase + 0x0184)
+#define AHBCLKCTRL0 (ASMUBase + 0x01a0)
+#define AHBCLKCTRL1 (ASMUBase + 0x01a4)
+#define APBCLKCTRL0 (ASMUBase + 0x01a8)
+#define APBCLKCTRL1 (ASMUBase + 0x01ac)
+#define CLKCTRL (ASMUBase + 0x01b0)
+#define GCLKCTRL0 (ASMUBase + 0x01b4)
+#define GCLKCTRL0ENA (ASMUBase + 0x01b8)
+#define GCLKCTRL1 (ASMUBase + 0x01bc)
+#define GCLKCTRL1ENA (ASMUBase + 0x01c0)
+#define GCLKCTRL2 (ASMUBase + 0x01c4)
+#define GCLKCTRL2ENA (ASMUBase + 0x01c8)
+#define GCLKCTRL3 (ASMUBase + 0x01cc)
+#define GCLKCTRL3ENA (ASMUBase + 0x01d0)
+#define AUTO_FRQ_CHANGE (ASMUBase + 0x01dc)
+#define AUTO_FRQ_MASK0 (ASMUBase + 0x01e0)
+#define AUTO_FRQ_MASK1 (ASMUBase + 0x01e4)
+#define DFS_HALFMODE (ASMUBase + 0x01e8)
+#define FLA_CLK_DLY (ASMUBase + 0x01f0)
+#define MEMCCLK270_SEL (ASMUBase + 0x01fc)
+#define ASMU_BGCTRL (ASMUBase + 0x0208)
+#define QR_ENA (ASMUBase + 0x0220)
+#define QR_CLKDIV (ASMUBase + 0x0224)
+#define FAKE_MODE (ASMUBase + 0x0238)
+#define POWERSW_STATUS (ASMUBase + 0x023c)
+#define POWERSW_ENA (ASMUBase + 0x0240)
+#define L1_POWERSW (ASMUBase + 0x0244)
+#define ACPU_POWERSW (ASMUBase + 0x0248)
+#define ADSP_POWERSW (ASMUBase + 0x024c)
+#define ACPU_BUB (ASMUBase + 0x0254)
+#define ADSP_BUB (ASMUBase + 0x0258)
+#define POWERSW_ACTRL_EN (ASMUBase + 0x025c)
+#define LOG1SW_ACTRL (ASMUBase + 0x0260)
+#define ADSPSW_ACTRL (ASMUBase + 0x0264)
+#define L1_BUZ (ASMUBase + 0x0268)
+#define L1_BUZ2 (ASMUBase + 0x026c)
+#define ACPUBUFTYPE (ASMUBase + 0x0288)
+#define ADSPUBUFTYPE (ASMUBase + 0x028c)
+#define HXBBUFTYPE (ASMUBase + 0x0290)
+#define STATUS_RECORD(n) (ASMUBase + 0x0320 + 0x004 *(n))
+#define ACPU_INIT (ASMUBase + 0x0360)
+#define AB1_U70WAITCTRL (ASMUBase + 0x03c0)
+#define AB1_U71WAITCTRL (ASMUBase + 0x03c4)
+#define AB1_U72WAITCTRL (ASMUBase + 0x03c8)
+#define AB1_IIC2WAITCTRL (ASMUBase + 0x03cc)
+#define AB1_IICWAITCTRL (ASMUBase + 0x03d0)
+#define AB1_U70READCTRL (ASMUBase + 0x03d4)
+#define AB1_U71READCTRL (ASMUBase + 0x03d8)
+#define AB1_U72READCTRL (ASMUBase + 0x03dc)
+#define AB1_IIC2READCTRL (ASMUBase + 0x03e0)
+#define AB1_IICREADCTRL (ASMUBase + 0x03e4)
+#define AB1_SDIBWAITCTRL (ASMUBase + 0x03e8)
+#define AB1_SDIBREADCTRL (ASMUBase + 0x03ec)
+#define AB1_SDICWAITCTRL (ASMUBase + 0x03f0)
+#define AB1_SDICREADCTRL (ASMUBase + 0x03f4)
+#define FLASHCLK_CTRL (ASMUBase + 0x0494)
+#define L2_POWERSW_BUZ (ASMUBase + 0x0500)
+#define LOG2SW_ACTRLEN (ASMUBase + 0x0504)
+#define LOG2SW_ACTRL (ASMUBase + 0x0508)
+#define L3_POWERSW_BUZ (ASMUBase + 0x050c)
+#define LOG3SW_ACTRLEN (ASMUBase + 0x0510)
+#define LOG3SW_ACTRL (ASMUBase + 0x0514)
+#define PLL_STATUS (ASMUBase + 0x0520)
+#define IO_L0_LM_BUZ (ASMUBase + 0x0814)
+#define RESETREQ3 (ASMUBase + 0x083c)
+#define RESETREQ3ENA (ASMUBase + 0x0840)
+#define APBCLKCTRL2 (ASMUBase + 0x0848)
+#define GCLKCTRL4 (ASMUBase + 0x084c)
+#define GCLKCTRL4ENA (ASMUBase + 0x0850)
+#define AUTO_FRQ_MASK3 (ASMUBase + 0x0860)
+#define DFS_FIFOMODE (ASMUBase + 0x0864)
+#define DFS_FIFO_REQMASK (ASMUBase + 0x0868)
+#define LCD_FIFOTHRESHOLD (ASMUBase + 0x086c)
+#define CAM_FIFOTHRESHOLD (ASMUBase + 0x0870)
+#define CAM_SAFE_RESET (ASMUBase + 0x0878)
+#define DTV_SAFE_RESET (ASMUBase + 0x0880)
+#define USB_SAFE_RESET (ASMUBase + 0x0884)
+#define CLKCTRL1 (ASMUBase + 0x088c)
+#define AB1_SDIAWAITCTRL (ASMUBase + 0x0890)
+#define AB1_SDIAREADCTRL (ASMUBase + 0x0894)
+#define MEMC_HAND_SHAKE_FAKE (ASMUBase + 0x08a0)
+#define SEL_BIGWEST (ASMUBase + 0x08b8)
+
+#define SPnBase(n) (0xc0120000 + 0x00010000 * (n))
+#define SP0 0x00
+#define SP1 0x01
+#define SPn_MODE(n) (SPnBase(n) + 0x0000)
+#define SPn_POL(n) (SPnBase(n) + 0x0004)
+#define SPn_CONTROL(n) (SPnBase(n) + 0x0008)
+#define SPn_TX_DATA(n) (SPnBase(n) + 0x0010)
+#define SPn_RX_DATA(n) (SPnBase(n) + 0x0014)
+#define SPn_STATUS(n) (SPnBase(n) + 0x0018)
+#define SPn_RAW_STATUS(n) (SPnBase(n) + 0x001c)
+#define SPn_ENSET(n) (SPnBase(n) + 0x0020)
+#define SPn_ENCLR(n) (SPnBase(n) + 0x0024)
+#define SPn_FFCLR(n) (SPnBase(n) + 0x0028)
+#define SPn_CONTROL2(n) (SPnBase(n) + 0x0034)
+#define SPn_TIECS(n) (SPnBase(n) + 0x0038)
+
+#define CHGREGBase 0xc0140000
+#define CHG_BOOT_MODE (CHGREGBase + 0x0000)
+#define CHG_L1_HOLD (CHGREGBase + 0x0004)
+#define CHG_LSI_REVISION (CHGREGBase + 0x0010)
+#define CHG_CTRL_SDINT (CHGREGBase + 0x0104)
+#define CHG_CTRL_AB0_BOOT (CHGREGBase + 0x0108)
+#define CHG_CTRL_OSC (CHGREGBase + 0x0110)
+#define CHG_PINSEL_G(n) (CHGREGBase + 0x0200 + 0x0004 * ((n) / 16))
+#define CHG_PINSEL_SP0 (CHGREGBase + 0x0280)
+#define CHG_PINSEL_DTV (CHGREGBase + 0x0284)
+#define CHG_PINSEL_SD0 (CHGREGBase + 0x0288)
+#define CHG_PINSEL_SD1 (CHGREGBase + 0x028c)
+#define CHG_PINSEL_IIC2 (CHGREGBase + 0x0290)
+#define CHG_PINSEL_REFCLKO (CHGREGBase + 0x0294)
+#define CHG_PULL_G(n) (CHGREGBase + 0x0300 + 0x0004 * ((n) / 8))
+#define CHG_PULL(n) (CHGREGBase + 0x0380 + 0x0004 * (n))
+#define CHG_DRIVE(n) (CHGREGBase + 0x0400 + 0x0004 * (n))
+
+#define IICBase(x) (0x50030000 + 0x00010000 * (x))
+#define IIC 0x01
+#define IIC2 0x00
+#define IIC_IIC(n) (IICBase(n) + 0x0000)
+#define IIC_IICC(n) (IICBase(n) + 0x0008)
+#define IIC_SVA(n) (IICBase(n) + 0x000c)
+#define IIC_IICCL(n) (IICBase(n) + 0x0010)
+#define IIC_IICSE(n) (IICBase(n) + 0x001c)
+#define IIC_IICF(n) (IICBase(n) + 0x0028)
+
+#endif /*__MONITOR_ARM_EM1D_H__*/
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/memattr.S b/tkernel_source/monitor/hwdepend/arm/mach-acd2/memattr.S
new file mode 100644
index 0000000..eb1fa2e
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-acd2/memattr.S
@@ -0,0 +1,129 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * memattr.S
+ *
+ * manipulation of page table
+ */
+#define _in_asm_source_
+
+#include <machine.h>
+#include <tk/sysdef.h>
+
+#include "setup_em1d512.h"
+
+/*
+ * memory barrier macros
+ */
+.macro _mov reg, val
+ .ifnes "\reg", "\val"
+ mov \reg, \val
+ .endif
+.endm
+.macro .ISB reg, val=#0
+ _mov \reg, \val
+ mcr p15, 0, \reg, cr7, c5, 4
+.endm
+.macro .DSB reg, val=#0
+ _mov \reg, \val
+ mcr p15, 0, \reg, cr7, c10, 4
+.endm
+.macro .DMB reg, val=#0
+ _mov \reg, \val
+ mcr p15, 0, \reg, cr7, c10, 5
+.endm
+
+/*
+ * change memory attribute
+ * void ChangeMemAttr(UW top, UW end, UW attr)
+ * change the memory attribute of memory area from `top' to `end' - 1 into `attr'
+ * The physical address where T-Monitor resides is assumed to start at 0x00000000.
+ * It must be called with disabled cache.
+ */
+ .text
+ .balign 4
+ .globl Csym(ChangeMemAttr)
+ .type Csym(ChangeMemAttr), %function
+Csym(ChangeMemAttr):
+changememattr_start:
+ stmfd sp!, {r4, r5, r7, r9, r10}
+
+ /* Map T-Monitor to 0x00000000 and up, the information before the mapping is saved. */
+ ldr ip, =PAGETBL_BASE
+ ldr r4, [ip]
+ ldr r10, =attr_prev
+ str r4, [r10]
+ ldr r4, =0x00009402 // Strongly-order, Kernel/RO
+ str r4, [ip]
+
+ .DSB r4
+ mcr p15, 0, r4, cr8, cr7, 0 // I/D TLB invalidate
+ mcr p15, 0, r4, cr7, cr5, 6 // invalidate BTC
+ .DSB r4
+ .ISB r4
+
+ /* Jump to the address into the remapped area */
+ ldr r4, =changememattr_main
+ ldr r9, =0xfff00000
+ bic r4, r4, r9 // r4 &= 0x000fffff
+ mov pc, r4
+
+ .pool
+
+changememattr_main:
+ bic r2, r2, r9 // r2 &= 0x000fffff
+ mov r4, r0, lsr #20
+ add r4, ip, r4, lsl #2 // r4 = (r2 >> 20) * 4 + PAGETBL_BASE
+
+changememattr_loop:
+ ldr r5, [r4] // *r4 = (*r4 & 0xfff00000) | r2
+ and r5, r5, r9
+ orr r5, r5, r2
+ str r5, [r4], #4
+ add r0, r0, #0x00100000
+ cmp r0, r1
+ bne changememattr_loop
+
+ /* Jump to the address in the originally mapped area */
+ .DSB r4
+ mcr p15, 0, r4, cr8, cr7, 0 // I/D TLB invalidate
+ mcr p15, 0, r4, cr7, cr5, 6 // invalidate BTC
+ .DSB r4
+ .ISB r4
+
+ ldr pc, =changememattr_finish
+
+ .pool
+
+changememattr_finish:
+ /* Unmap the T-Monitor in the area from 0x00000000 and up. */
+ ldr r4, [r10] // attr_prev
+ str r4, [ip] // PAGETBL_BASE
+
+ .DSB r4
+ mcr p15, 0, r4, cr8, cr7, 0 // I/D TLB invalidate
+ mcr p15, 0, r4, cr7, cr5, 6 // invalidate BTC
+ .DSB r4
+ .ISB r4
+
+ ldmfd sp!, {r4, r5, r7, r9, r10}
+ bx lr
+
+ .pool
+
+
+ .bss
+attr_prev:
+ .long 0
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/misc.c b/tkernel_source/monitor/hwdepend/arm/mach-acd2/misc.c
new file mode 100644
index 0000000..4486c5a
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-acd2/misc.c
@@ -0,0 +1,46 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * misc.c
+ *
+ */
+
+#include "sysdepend.h"
+
+/*
+ * obtain switch status
+ */
+EXPORT UW getDipSw( void )
+{
+ return DipSw;
+}
+
+/*
+ * Obtain boot selection information
+ */
+EXPORT W bootSelect( void )
+{
+ if ( (DipSw & (SW_MON|SW_ABT)) != 0 ) return BS_MONITOR;
+
+ return BS_AUTO;
+}
+
+/*
+ * obtain the console port number
+ */
+EXPORT W getConPort( void )
+{
+ return 0;
+}
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/setup_em1d512.h b/tkernel_source/monitor/hwdepend/arm/mach-acd2/setup_em1d512.h
new file mode 100644
index 0000000..e733589
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-acd2/setup_em1d512.h
@@ -0,0 +1,47 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * setup_em1d512.h
+ *
+ * EM1D-512 configuration information
+ *
+ * this file included from assembly source files, too.
+ */
+
+#define EITENT_BASE 0x70000000 /* address for exception branch processing */
+#define PAGETBL_BASE 0x30000000 /* address of the first level table page. */
+
+/*
+ * clock value
+ */
+#define PLL1_CLK 499712 /* 499.712MHz */
+#define PLL2_CLK 401418 /* 401.408MHz */
+#define PLL3_CLK 229376 /* 229.376MHz */
+
+#define ACPU_CLK (PLL1_CLK / 1)
+#define Txx_CLK (PLL3_CLK / 8)
+
+/*
+ * assignment to DipSw (switches)
+ */
+#define SW_ABT 0x0100 /* Abort SW */
+#define SW_MON 0x0020 /* Monitor Boot */
+#define SW_BHI 0x0000 /* fix HI_BAUD_RATE */
+
+/*
+ * LED display (two bits, 2 bits)
+ */
+#define LED_POWERUP 0x01 /* Power-on */
+#define LED_MEMCLR 0xff /* Memory clear */
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/sio.c b/tkernel_source/monitor/hwdepend/arm/mach-acd2/sio.c
new file mode 100644
index 0000000..af858b2
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-acd2/sio.c
@@ -0,0 +1,80 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * sio.c
+ *
+ * serial port I/O
+ */
+
+#include "hwdepend.h"
+
+EXPORT W ConPort; /* console port number */
+EXPORT UW ConPortBps; /* console port commnication speed (bps) */
+
+LOCAL SIOCB SIO; /* serial port control block */
+
+/*
+ * initialize serial port
+ * port console port number (0 - )
+ * when it is -1, it means there is no console.
+ * speed communication speed (bps)
+ */
+EXPORT ER initSIO( W port, W speed )
+{
+ const CFGSIO *cp;
+ ER err;
+
+ if ( port >= N_ConfigSIO ) port = 0; /* invalid value is turned into a default value. */
+
+ memset(&SIO, 0, sizeof(SIO));
+ ConPort = port;
+ ConPortBps = speed;
+
+ if ( port < 0 ) return E_OK; /* no console */
+
+ /* initialize hardware */
+ cp = &ConfigSIO[port];
+ err = (*cp->initsio)(&SIO, cp, speed);
+ if ( err < E_OK ) goto err_ret;
+
+ return E_OK;
+
+err_ret:
+ /* if there was an error, treat it as no console */
+ memset(&SIO, 0, sizeof(SIO));
+ ConPort = -1;
+ return err;
+}
+
+/*
+ * serial port I/O
+ */
+EXPORT void putSIO( UB c )
+{
+ if ( SIO.put != NULL ) (*SIO.put)(&SIO, c);
+}
+
+/*
+ * serial port input (with buffering)
+ * tmo timeout (milliseconds)
+ * You can not wait forever.
+ * return value >= 0 : character code
+ * -1 : timeout
+ * receive error is ignored
+ */
+EXPORT W getSIO( W tmo )
+{
+ return ( SIO.get != NULL )? (*SIO.get)(&SIO, tmo): -1;
+}
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/startup.c b/tkernel_source/monitor/hwdepend/arm/mach-acd2/startup.c
new file mode 100644
index 0000000..fa0feb3
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-acd2/startup.c
@@ -0,0 +1,92 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * startup.c
+ *
+ * system boot processing
+ */
+
+#include "hwdepend.h"
+
+/* No support for the progress report yet */
+#define DispProgress(n) /* nop */
+
+/*
+ * debug port speed
+ * default setting is LO:38400bps, and HI:115200bps. But
+ * if you need a different set value, then define the following macros in {cpu}/{machine}/setup_xxx.h :
+ * LO_BAUD_RATE, and HI_BAUD_RATE.
+ */
+#ifndef LO_BAUD_RATE
+# define LO_BAUD_RATE 38400
+#endif
+#ifndef HI_BAUD_RATE
+# define HI_BAUD_RATE 115200
+#endif
+
+/*
+ * initial processing after reset
+ */
+EXPORT void procReset( void )
+{
+ const MEMSEG *mp;
+ W i;
+ W speed;
+
+ DispProgress(0x01);
+
+ /* system basic set up */
+ resetSystem(0);
+ DispProgress(0x06);
+
+ /* setting up the initial count for micro-wait */
+ setupWaitUsec();
+ DispProgress(0x07);
+
+ /* initialize console serial port */
+#if SW_BHI == 0
+ speed = HI_BAUD_RATE; /* HI speed is fixed. */
+#else
+ speed = ( (DipSw & SW_BHI) != 0 )? HI_BAUD_RATE: LO_BAUD_RATE;
+#endif
+ initSIO(getConPort(), speed);
+ DispProgress(0x08);
+
+ /* initialize hardware (peripherals) */
+ initHardware();
+ DispProgress(0x0d);
+
+ /* memory clear is not done to save time when automatic reboot is under way. */
+ if ( bootSelect() == BS_MONITOR ) {
+ cpuLED(LED_MEMCLR);
+
+ /* all memory clear (save the monitor area) */
+ for ( i = 1;; ++i ) {
+ mp = MemArea(MSA_OS|MSA_ERAM, i);
+ if ( mp == NULL ) break;
+
+ memset((void*)mp->top, 0, mp->end - mp->top);
+ }
+ }
+ cpuLED(LED_POWERUP);
+ DispProgress(0x0e);
+
+ /* initialize break processing */
+ initBreak();
+
+ /* Invoking user reset initialization routine */
+ callUserResetInit();
+ DispProgress(0x0f);
+}
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/sysdepend.h b/tkernel_source/monitor/hwdepend/arm/mach-acd2/sysdepend.h
new file mode 100644
index 0000000..8003371
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-acd2/sysdepend.h
@@ -0,0 +1,43 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * sysdepend.h
+ *
+ * system-related definitions: ARM CPUs.
+ */
+
+#ifndef __MONITOR_CMDSVC_SYSDEPEND_H__
+#define __MONITOR_CMDSVC_SYSDEPEND_H__
+
+#include "hwdepend.h"
+#include <sys/sysinfo.h>
+#include <sys/rominfo.h>
+#include "setup_em1d512.h"
+
+/*
+ * cache and MMU control
+ */
+IMPORT void setCacheMMU( UW cp15r1 );
+
+/*
+ * machine-dependent interrupt processing
+ * info is defined in machine-dependent manner.
+ * return value 0 : it is not the target of processing.
+ * 1 : the object is the target of processing (the monitor should continue monitoring)
+ * 2 : the object is the target of processing (exiting interrupt handler).
+ */
+IMPORT W procHwInt( UW info );
+
+#endif /* __MONITOR_CMDSVC_SYSDEPEND_H__ */
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/system.c b/tkernel_source/monitor/hwdepend/arm/mach-acd2/system.c
new file mode 100644
index 0000000..8bfe2aa
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-acd2/system.c
@@ -0,0 +1,307 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by T-Engine Forum at 2011/09/08.
+ * Modified by T-Engine Forum at 2013/03/04.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * system.c
+ *
+ * system-related processing
+ *
+ * target: EM1D-512
+ */
+
+#include "sysdepend.h"
+#include <mach/em1d512.h>
+
+EXPORT UW DipSw; /* DipSw status */
+
+/* hardware dependent functions */
+IMPORT UW DipSwStatus(void);
+IMPORT void usbPower(BOOL power);
+IMPORT void powerOff(void);
+IMPORT void resetStart(void);
+
+/* interrupt entry point (eitent.S) */
+LOCAL void _gio0Hdr(void) {}
+LOCAL void _gio1Hdr(void) {}
+LOCAL void _gio2Hdr(void) {}
+LOCAL void _gio3Hdr(void) {}
+LOCAL void _gio4Hdr(void) {}
+LOCAL void _gio5Hdr(void) {}
+LOCAL void _gio6Hdr(void) {}
+LOCAL void _gio7Hdr(void) {}
+
+/* default handler (cmdsvc) */
+IMPORT void _defaultHdr(void);
+
+/* macros for manipulating cache/MMU/PMIC */
+#define EnbCacheMMU(x) setCacheMMU(ENB_CACHEMMU)
+#define DisCacheMMU(x) setCacheMMU(ENB_MMUONLY) /* MMU can't be turned off */
+
+/* ------------------------------------------------------------------------ */
+
+IMPORT char __loadaddr; /* monitor load address */
+IMPORT MEMSEG NoMemSeg[]; /* memory unused area */
+IMPORT W N_NoMemSeg;
+
+/*
+ power management controller (DA9052) handler routines
+*/
+#define SPIPol 0x0092
+
+/* initialize SPI for PMIC communication */
+LOCAL void pmicInit(void)
+{
+ out_w(SPn_MODE(SP0), 0x2700); /* 8bit, CS0, Master, CPU mode */
+ out_w(SPn_TIECS(SP0), 0x000f); /* CS0: follow the specification by SPn_POL */
+ out_w(SPn_POL(SP0), SPIPol);
+ out_w(SPn_ENCLR(SP0), ~0); /* interrupt disable */
+
+ out_w(SPn_CONTROL(SP0), 0x0100); /* start reset */
+ waitUsec(10);
+ out_w(SPn_CONTROL(SP0), 0x0000); /* release reset */
+ out_w(SPn_CONTROL2(SP0), 0x0000);
+
+ return;
+}
+
+/* wait for data of SPI for PMIC communication */
+LOCAL void pmicWait(void)
+{
+ W i;
+
+ for (i = 1000000; i > 0; i--) {
+ if (in_w(SPn_RAW_STATUS(SP0)) & 0x0004) break;
+ waitUsec(1);
+ }
+ if (!i) pmicInit();
+
+ return;
+}
+
+/* contro CS line of SPI for PMIC communication */
+LOCAL void pmicCSassert(BOOL cs)
+{
+ waitNsec(200);
+ out_w(SPn_POL(SP0), SPIPol ^ (cs ? 0x0001 : 0x0000));
+ waitNsec(200);
+
+ return;
+}
+
+/* read PMIC register */
+EXPORT W pmicRead(W reg)
+{
+ W dat;
+
+ pmicCSassert(TRUE); /* CS assert */
+
+ out_w(SPn_FFCLR(SP0), ~0); /* status flag is cleared */
+ out_w(SPn_TX_DATA(SP0), (reg << 1) | 1); /* send register number */
+ out_w(SPn_CONTROL(SP0), 0x0009); /* send start */
+ pmicWait();
+
+ out_w(SPn_FFCLR(SP0), ~0); /* status flag is cleared */
+ out_w(SPn_CONTROL(SP0), 0x0005); /* start receive */
+ pmicWait();
+ dat = in_w(SPn_RX_DATA(SP0)); /* data received */
+
+ pmicCSassert(FALSE); /* CS de-assert */
+
+ return dat;
+}
+
+/* write PMIC register */
+EXPORT void pmicWrite(W reg, W dat)
+{
+ pmicCSassert(TRUE); /* CS assert */
+
+ out_w(SPn_FFCLR(SP0), ~0); /* status flag is cleared */
+ out_w(SPn_TX_DATA(SP0), reg << 1); /* send register number */
+ out_w(SPn_CONTROL(SP0), 0x0009); /* send start */
+ pmicWait();
+
+ out_w(SPn_FFCLR(SP0), ~0); /* status flag is cleared */
+ out_w(SPn_TX_DATA(SP0), dat); /* send data */
+ out_w(SPn_CONTROL(SP0), 0x0009); /* send start */
+ pmicWait();
+
+ pmicCSassert(FALSE); /* CS de-assert */
+
+ return;
+}
+
+/* ------------------------------------------------------------------------ */
+
+/* basic system set up (performed during reset, and Disk Boot) */
+EXPORT void resetSystem(W boot)
+{
+ MEMSEG *mp;
+ UW i, va;
+
+ /* obtain DipSw status */
+ if (!boot) DipSw = DipSwStatus();
+
+ DisCacheMMU();
+
+ /* set up interrupt controller */
+ out_w(IT0_IDS0, ~0); /* CPU: all interrupts disabled */
+ out_w(IT0_IDS1, ~0);
+ out_w(IT0_IDS2, ~0);
+ out_w(IT0_IIR, ~0);
+ out_w(IT3_IPI0_CLR, 0x0000003f);
+ out_w(IT3_IDS0, ~0); /* DSP: all interrupts disabled */
+ out_w(IT3_IDS1, ~0);
+ out_w(IT3_IDS2, ~0);
+ out_w(IT3_IIR, ~0);
+ out_w(IT0_IPI3_CLR, 0x0000003f);
+ out_w(IT0_FID, 0x00000001); /* CPU: FIQ disabled */
+ out_w(GIO_IIA(GIO_L), 0); /* GPIO: interrupt disabled */
+ out_w(GIO_IIA(GIO_H), 0);
+ out_w(GIO_IIA(GIO_HH), 0);
+ out_w(GIO_IIA(GIO_HHH), 0);
+ out_w(GIO_GSW(GIO_L), 0); /* GPIO: FIQ interrupt disabled */
+ out_w(GIO_GSW(GIO_H), 0);
+ out_w(GIO_GSW(GIO_HH), 0);
+ out_w(GIO_GSW(GIO_HHH), 0);
+ out_w(IT0_LIIR, 0x0000000f); /* internal interrupt disabled */
+ out_w(IT_PINV_CLR0, ~0); /* inhibit interrupt polarity inversion */
+ out_w(IT_PINV_CLR1, ~0);
+ out_w(IT_PINV_CLR2, ~0);
+ out_w(IT0_IEN0, 0x0c000000); /* CPU: GPIO interrupt enabled */
+ out_w(IT0_IEN1, 0x003c0000);
+ out_w(IT0_IEN2, 0x00018000);
+
+ /* power on controller initialization */
+ pmicInit();
+
+ /* USB power on */
+ usbPower(TRUE);
+
+ /* clear system common area (vector table, and SysInfo) */
+ memset(&SCInfo, 0, sizeof(SysCommonInfo));
+ memset(SCArea, 0, sizeof(SysCommonArea));
+
+ /* if monitor is loaded into RAM, exclude the RAM area */
+ mp = MemArea(MSA_OS, 1);
+ va = (UW)&__loadaddr;
+ if (va >= mp->top && va < mp->end) mp->end = va;
+
+ /* exclude the area where ROM disk data is stored */
+ va = (UW)ROMInfo->userarea;
+ if (va >= mp->top && va < mp->end) mp->end = va;
+
+ /* initialize system common information (SysInfo) */
+ SCInfo.ramtop = (void*)mp->top;
+ if (va < mp->top || va > mp->end) va = mp->end;
+ SCInfo.ramend = (void*)va;
+
+ /* set up EIT vectors */
+ /* we do not need _defaultHdr absolutely, but just in case set it up */
+ SCArea->intvec[EIT_DEFAULT] = _defaultHdr; /* default handler */
+ SCArea->intvec[EIT_UNDEF] = _defaultHdr; /* undefined instruction */
+ SCArea->intvec[SWI_MONITOR] = _defaultHdr; /* SWI - monitor SVC */
+ SCArea->intvec[EIT_IRQ(26)] = _gio6Hdr; /* GPIO branch */
+ SCArea->intvec[EIT_IRQ(27)] = _gio7Hdr;
+ SCArea->intvec[EIT_IRQ(50)] = _gio0Hdr;
+ SCArea->intvec[EIT_IRQ(51)] = _gio1Hdr;
+ SCArea->intvec[EIT_IRQ(52)] = _gio2Hdr;
+ SCArea->intvec[EIT_IRQ(53)] = _gio3Hdr;
+ SCArea->intvec[EIT_IRQ(79)] = _gio4Hdr;
+ SCArea->intvec[EIT_IRQ(80)] = _gio5Hdr;
+ SCArea->intvec[EIT_GPIO(8)] = _defaultHdr; /* abort switch */
+
+ /* set up initial page table */
+ for (i = 0; i < N_MemSeg; ++i) {
+ mp = &MemSeg[i];
+ if (!mp->pa) continue;
+
+ /* FlashROM has already been mapped, and so do not touch it */
+ if (mp->attr == MSA_FROM) continue;
+
+ /* set up in unit of section (1MB) */
+ for ( va = (mp->top & 0xfff00000);
+ va != ((mp->end + 0x000fffff) & 0xfff00000);
+ va += 0x00100000 ) {
+ TopPageTable[va / 0x00100000] =
+ ((mp->pa & 0xfff00000) + va) |
+ (mp->pa & 0x000fffff);
+ }
+ }
+
+ for (i = 0; i < N_NoMemSeg; ++i) {
+ mp = &NoMemSeg[i];
+
+ /* set up in unit of section (1MB) */
+ for ( va = (mp->top & 0xfff00000);
+ va != ((mp->end + 0x000fffff) & 0xfff00000);
+ va += 0x00100000 ) {
+ TopPageTable[va / 0x00100000] = 0;
+ }
+ }
+
+ DSB();
+ Asm("mcr p15, 0, %0, cr8, c7, 0":: "r"(0)); /* I/D TLB invalidate */
+ Asm("mcr p15, 0, %0, cr7, c5, 6":: "r"(0)); /* invalidate BTC */
+ DSB();
+ ISB();
+
+ EnbCacheMMU();
+
+ return;
+}
+
+/* ------------------------------------------------------------------------ */
+
+/*
+ system termination: reset / system power off
+ reset 0 power off
+ -1 reboot
+ 0xaa55 halt boot and power off
+*/
+EXPORT void sysExit(W reset)
+{
+ DisCacheMMU();
+
+ /* after this point, delay such as waitUsec() spends more time than the number indicates // */
+
+ /* LED off */
+ cpuLED(0x00);
+
+ /* all interrupts disabled */
+ out_w(IT0_IDS0, ~0); /* CPU: all interrupts disabled */
+ out_w(IT0_IDS1, ~0);
+ out_w(IT0_IDS2, ~0);
+ out_w(IT3_IPI0_CLR, 0x0000003f);
+ out_w(IT3_IDS0, ~0); /* DSP: all interrupts disabled */
+ out_w(IT3_IDS1, ~0);
+ out_w(IT3_IDS2, ~0);
+ out_w(IT0_IPI3_CLR, 0x0000003f);
+ out_w(IT0_FID, 0x00000001); /* FIQ disabled */
+ out_w(IT0_LIIR, 0x0000000f); /* internal interrupt disabled */
+
+ /* power on controller initialization */
+ pmicInit();
+
+ /* USB power off */
+ usbPower(FALSE);
+
+ if (reset >= 0) powerOff();
+
+ /* reset start */
+ resetStart();
+}
+
+/* ------------------------------------------------------------------------ */
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/waitusec.c b/tkernel_source/monitor/hwdepend/arm/mach-acd2/waitusec.c
new file mode 100644
index 0000000..d76e1ff
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-acd2/waitusec.c
@@ -0,0 +1,112 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * waitusec.c
+ *
+ * EM1-D512: micro wait
+ */
+
+#include "sysdepend.h"
+#include <mach/em1d512.h>
+
+LOCAL UW delay64us; /* wait for 64 microsec */
+
+/*
+ * wait for nanoseconds
+ */
+EXPORT void waitNsec(_UW nsec)
+{
+ for (nsec = nsec * delay64us / 64000; nsec > 0; nsec--);
+
+ return;
+}
+
+/*
+ * wait for microseconds
+ */
+EXPORT void waitUsec(_UW usec)
+{
+ for (usec = usec * delay64us / 64; usec > 0; usec--);
+
+ return;
+}
+
+/*
+ * wait for milliseconds
+ */
+EXPORT void waitMsec(UW msec)
+{
+ while (msec-- > 0) waitUsec(1000);
+
+ return;
+}
+
+/* ------------------------------------------------------------------------ */
+
+/*
+ * setting up the initial count for micro-wait()
+ */
+EXPORT void setupWaitUsec(void)
+{
+ UW t0, t1, t2;
+
+#define MAX_CNT (ACPU_CLK * 64 / 10) /* 1 Clock */
+#define MIN_CNT (ACPU_CLK * 64 / 1280) /* 128 Clock */
+
+ /* use TI0 timer, and assume clock is PLL3 / 8 */
+ out_w(Txx_OP(TI0), 0); /* Timer stop, count clear */
+ while (in_w(Txx_RCR(TI0)));
+
+ out_w(Txx_SET(TI0), 0xffffffff); /* maximum count */
+ out_w(Txx_OP(TI0), 0x00000003); /* Timer start */
+
+ delay64us = 64;
+ waitUsec(1000); /* wait for a while until things settle down */
+
+ t0 = in_w(Txx_RCR(TI0));
+ waitUsec(1000);
+ t1 = in_w(Txx_RCR(TI0));
+ waitUsec(3000);
+ t2 = in_w(Txx_RCR(TI0));
+
+ out_w(Txx_OP(TI0),0); /* Timer stop, count clear */
+ while (in_w(Txx_RCR(TI0)));
+
+ t2 -= t1; /* count for 3000 times */
+ t1 -= t0; /* count for 1000 times */
+ t2 -= t1; /* count for 2000 times */
+
+ /*
+ * calculate the count for 64 microsec
+ *
+ * 2000 loops x timer clock [MHz] x 64 [microsec]
+ * delay64us = ------------------------------------------------
+ * t2
+ *
+ * * considering the representation of PLL3_CLK (1/1000MHz unit), and setting of pre scaler,
+ * it can be written down as follows.
+ *
+ * 2 loops x PLL3_CLK [1/1000MHz] x 8 [microsec]
+ * delay64us = -------------------------------------------
+ * t2
+ *
+ */
+ delay64us = (t2 == 0) ? MAX_CNT : ((2 * PLL3_CLK * 8) / t2);
+ if (delay64us > MAX_CNT) delay64us = MAX_CNT;
+ else if (delay64us < MIN_CNT) delay64us = MIN_CNT;
+
+ return;
+}
+
--
1.9.1
References
