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Message #00021
[PATCH] tmonitor: struct dir
From: Du Huanpeng <u74147@xxxxxxxxx>
Signed-off-by: Du Huanpeng <u74147@xxxxxxxxx>
---
tkernel_source/monitor/bin/tef_em1d/_dmy | 0
tkernel_source/monitor/cmdsvc/boot.c | 126 ++
.../monitor/cmdsvc/build/tef_em1d/Makefile | 78 --
tkernel_source/monitor/cmdsvc/cmdsvc.h | 307 +++++
tkernel_source/monitor/cmdsvc/command.c | 1274 ++++++++++++++++++++
tkernel_source/monitor/cmdsvc/console.c | 293 +++++
tkernel_source/monitor/cmdsvc/help.h | 50 +
tkernel_source/monitor/cmdsvc/helpmsg.c | 392 ++++++
tkernel_source/monitor/cmdsvc/load.c | 329 +++++
tkernel_source/monitor/cmdsvc/memory.c | 170 +++
tkernel_source/monitor/cmdsvc/src/armv6/break.c | 560 ---------
tkernel_source/monitor/cmdsvc/src/armv6/chkaddr.c | 136 ---
tkernel_source/monitor/cmdsvc/src/armv6/cpudep.h | 79 --
.../monitor/cmdsvc/src/armv6/disassemble.c | 63 -
tkernel_source/monitor/cmdsvc/src/armv6/misc.c | 54 -
tkernel_source/monitor/cmdsvc/src/armv6/monent.c | 97 --
tkernel_source/monitor/cmdsvc/src/armv6/monhdr.S | 224 ----
tkernel_source/monitor/cmdsvc/src/armv6/register.c | 430 -------
tkernel_source/monitor/cmdsvc/src/armv6/step.c | 499 --------
tkernel_source/monitor/cmdsvc/src/boot.c | 126 --
tkernel_source/monitor/cmdsvc/src/cmdsvc.h | 307 -----
tkernel_source/monitor/cmdsvc/src/command.c | 1274 --------------------
tkernel_source/monitor/cmdsvc/src/console.c | 293 -----
tkernel_source/monitor/cmdsvc/src/help.h | 50 -
tkernel_source/monitor/cmdsvc/src/helpmsg.c | 392 ------
tkernel_source/monitor/cmdsvc/src/load.c | 329 -----
tkernel_source/monitor/cmdsvc/src/memory.c | 170 ---
tkernel_source/monitor/cmdsvc/src/string.c | 262 ----
tkernel_source/monitor/cmdsvc/src/svc.c | 170 ---
tkernel_source/monitor/cmdsvc/src/wrkbuf.c | 27 -
tkernel_source/monitor/cmdsvc/svc.c | 174 +++
tkernel_source/monitor/cmdsvc/wrkbuf.c | 27 +
.../monitor/driver/flash/build/tef_em1d/Makefile | 89 --
tkernel_source/monitor/driver/flash/cfi.c | 64 +
tkernel_source/monitor/driver/flash/cfi_16x1.c | 199 +++
tkernel_source/monitor/driver/flash/flash.h | 81 ++
tkernel_source/monitor/driver/flash/main.c | 159 +++
tkernel_source/monitor/driver/flash/reset-em1d.c | 43 +
tkernel_source/monitor/driver/flash/setup-em1d.c | 71 ++
tkernel_source/monitor/driver/flash/src/cfi.c | 64 -
tkernel_source/monitor/driver/flash/src/cfi_16x1.c | 199 ---
tkernel_source/monitor/driver/flash/src/flash.h | 81 --
tkernel_source/monitor/driver/flash/src/main.c | 159 ---
.../monitor/driver/flash/src/reset-em1d.c | 43 -
.../monitor/driver/flash/src/setup-em1d.c | 71 --
.../monitor/driver/memdisk/build/tef_em1d/Makefile | 75 --
tkernel_source/monitor/driver/memdisk/memdsk.c | 163 +++
tkernel_source/monitor/driver/memdisk/src/memdsk.c | 163 ---
.../monitor/driver/sio/build/tef_em1d/Makefile | 75 --
tkernel_source/monitor/driver/sio/ns16550.c | 294 +++++
tkernel_source/monitor/driver/sio/src/ns16550.c | 294 -----
tkernel_source/monitor/hwdepend/arm/cpu/break.c | 560 +++++++++
tkernel_source/monitor/hwdepend/arm/cpu/cpuctrl2.S | 90 ++
.../monitor/hwdepend/arm/cpu/disassemble.c | 63 +
tkernel_source/monitor/hwdepend/arm/cpu/eitent.S | 313 +++++
tkernel_source/monitor/hwdepend/arm/cpu/monhdr.S | 224 ++++
tkernel_source/monitor/hwdepend/arm/cpu/register.c | 430 +++++++
tkernel_source/monitor/hwdepend/arm/cpu/reset.S | 639 ++++++++++
tkernel_source/monitor/hwdepend/arm/cpu/step.c | 499 ++++++++
.../monitor/hwdepend/arm/include/asm/cpudep.h | 79 ++
.../monitor/hwdepend/arm/lib/monitor.lnk | 112 ++
.../monitor/hwdepend/arm/mach-em1d/chkaddr.c | 136 +++
.../monitor/hwdepend/arm/mach-em1d/config.c | 669 ++++++++++
.../monitor/hwdepend/arm/mach-em1d/cpuctrl.c | 82 ++
.../monitor/hwdepend/arm/mach-em1d/diskio.c | 250 ++++
.../monitor/hwdepend/arm/mach-em1d/eitproc.c | 132 ++
.../monitor/hwdepend/arm/mach-em1d/hwdepend.h | 63 +
.../monitor/hwdepend/arm/mach-em1d/hwinfo.c | 147 +++
.../arm/mach-em1d/include/mach/cpudepend.h | 96 ++
.../hwdepend/arm/mach-em1d/include/mach/em1d512.h | 464 +++++++
.../monitor/hwdepend/arm/mach-em1d/memattr.S | 129 ++
.../monitor/hwdepend/arm/mach-em1d/misc.c | 46 +
.../monitor/hwdepend/arm/mach-em1d/setup_em1d512.h | 47 +
.../monitor/hwdepend/arm/mach-em1d/sio.c | 80 ++
.../monitor/hwdepend/arm/mach-em1d/startup.c | 92 ++
.../monitor/hwdepend/arm/mach-em1d/sysdepend.h | 43 +
.../monitor/hwdepend/arm/mach-em1d/system.c | 307 +++++
.../monitor/hwdepend/arm/mach-em1d/waitusec.c | 112 ++
tkernel_source/monitor/hwdepend/arm/misc.c | 54 +
tkernel_source/monitor/hwdepend/arm/monent.c | 97 ++
.../monitor/hwdepend/tef_em1d/build/Makefile | 77 --
.../monitor/hwdepend/tef_em1d/src/config.c | 669 ----------
.../monitor/hwdepend/tef_em1d/src/cpuctrl.c | 82 --
.../monitor/hwdepend/tef_em1d/src/cpuctrl2.S | 90 --
.../monitor/hwdepend/tef_em1d/src/diskio.c | 250 ----
.../monitor/hwdepend/tef_em1d/src/eitent.S | 313 -----
.../monitor/hwdepend/tef_em1d/src/eitproc.c | 132 --
.../monitor/hwdepend/tef_em1d/src/hwdepend.h | 63 -
.../monitor/hwdepend/tef_em1d/src/hwinfo.c | 147 ---
.../monitor/hwdepend/tef_em1d/src/memattr.S | 129 --
.../monitor/hwdepend/tef_em1d/src/misc.c | 46 -
.../monitor/hwdepend/tef_em1d/src/reset.S | 639 ----------
.../monitor/hwdepend/tef_em1d/src/setup_em1d512.h | 47 -
tkernel_source/monitor/hwdepend/tef_em1d/src/sio.c | 80 --
.../monitor/hwdepend/tef_em1d/src/startup.c | 92 --
.../monitor/hwdepend/tef_em1d/src/sysdepend.h | 43 -
.../monitor/hwdepend/tef_em1d/src/system.c | 307 -----
.../monitor/hwdepend/tef_em1d/src/waitusec.c | 112 --
tkernel_source/monitor/include/arm/cpudepend.h | 96 --
tkernel_source/monitor/include/arm/em1d512.h | 464 -------
tkernel_source/monitor/lib/string.c | 262 ++++
.../monitor/tmmain/build/tef_em1d/Makefile | 144 ---
.../monitor/tmmain/build/tef_em1d/monitor.lnk | 112 --
tkernel_source/monitor/tmmain/version.c | 6 +
104 files changed, 10539 insertions(+), 11067 deletions(-)
delete mode 100644 tkernel_source/monitor/bin/tef_em1d/_dmy
create mode 100644 tkernel_source/monitor/cmdsvc/boot.c
delete mode 100644 tkernel_source/monitor/cmdsvc/build/tef_em1d/Makefile
create mode 100644 tkernel_source/monitor/cmdsvc/cmdsvc.h
create mode 100644 tkernel_source/monitor/cmdsvc/command.c
create mode 100644 tkernel_source/monitor/cmdsvc/console.c
create mode 100644 tkernel_source/monitor/cmdsvc/help.h
create mode 100644 tkernel_source/monitor/cmdsvc/helpmsg.c
create mode 100644 tkernel_source/monitor/cmdsvc/load.c
create mode 100644 tkernel_source/monitor/cmdsvc/memory.c
delete mode 100644 tkernel_source/monitor/cmdsvc/src/armv6/break.c
delete mode 100644 tkernel_source/monitor/cmdsvc/src/armv6/chkaddr.c
delete mode 100644 tkernel_source/monitor/cmdsvc/src/armv6/cpudep.h
delete mode 100644 tkernel_source/monitor/cmdsvc/src/armv6/disassemble.c
delete mode 100644 tkernel_source/monitor/cmdsvc/src/armv6/misc.c
delete mode 100644 tkernel_source/monitor/cmdsvc/src/armv6/monent.c
delete mode 100644 tkernel_source/monitor/cmdsvc/src/armv6/monhdr.S
delete mode 100644 tkernel_source/monitor/cmdsvc/src/armv6/register.c
delete mode 100644 tkernel_source/monitor/cmdsvc/src/armv6/step.c
delete mode 100644 tkernel_source/monitor/cmdsvc/src/boot.c
delete mode 100644 tkernel_source/monitor/cmdsvc/src/cmdsvc.h
delete mode 100644 tkernel_source/monitor/cmdsvc/src/command.c
delete mode 100644 tkernel_source/monitor/cmdsvc/src/console.c
delete mode 100644 tkernel_source/monitor/cmdsvc/src/help.h
delete mode 100644 tkernel_source/monitor/cmdsvc/src/helpmsg.c
delete mode 100644 tkernel_source/monitor/cmdsvc/src/load.c
delete mode 100644 tkernel_source/monitor/cmdsvc/src/memory.c
delete mode 100644 tkernel_source/monitor/cmdsvc/src/string.c
delete mode 100644 tkernel_source/monitor/cmdsvc/src/svc.c
delete mode 100644 tkernel_source/monitor/cmdsvc/src/wrkbuf.c
create mode 100644 tkernel_source/monitor/cmdsvc/svc.c
create mode 100644 tkernel_source/monitor/cmdsvc/wrkbuf.c
delete mode 100644 tkernel_source/monitor/driver/flash/build/tef_em1d/Makefile
create mode 100644 tkernel_source/monitor/driver/flash/cfi.c
create mode 100644 tkernel_source/monitor/driver/flash/cfi_16x1.c
create mode 100644 tkernel_source/monitor/driver/flash/flash.h
create mode 100644 tkernel_source/monitor/driver/flash/main.c
create mode 100644 tkernel_source/monitor/driver/flash/reset-em1d.c
create mode 100644 tkernel_source/monitor/driver/flash/setup-em1d.c
delete mode 100644 tkernel_source/monitor/driver/flash/src/cfi.c
delete mode 100644 tkernel_source/monitor/driver/flash/src/cfi_16x1.c
delete mode 100644 tkernel_source/monitor/driver/flash/src/flash.h
delete mode 100644 tkernel_source/monitor/driver/flash/src/main.c
delete mode 100644 tkernel_source/monitor/driver/flash/src/reset-em1d.c
delete mode 100644 tkernel_source/monitor/driver/flash/src/setup-em1d.c
delete mode 100644 tkernel_source/monitor/driver/memdisk/build/tef_em1d/Makefile
create mode 100644 tkernel_source/monitor/driver/memdisk/memdsk.c
delete mode 100644 tkernel_source/monitor/driver/memdisk/src/memdsk.c
delete mode 100644 tkernel_source/monitor/driver/sio/build/tef_em1d/Makefile
create mode 100644 tkernel_source/monitor/driver/sio/ns16550.c
delete mode 100644 tkernel_source/monitor/driver/sio/src/ns16550.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/cpu/break.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/cpu/cpuctrl2.S
create mode 100644 tkernel_source/monitor/hwdepend/arm/cpu/disassemble.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/cpu/eitent.S
create mode 100644 tkernel_source/monitor/hwdepend/arm/cpu/monhdr.S
create mode 100644 tkernel_source/monitor/hwdepend/arm/cpu/register.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/cpu/reset.S
create mode 100644 tkernel_source/monitor/hwdepend/arm/cpu/step.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/include/asm/cpudep.h
create mode 100644 tkernel_source/monitor/hwdepend/arm/lib/monitor.lnk
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-em1d/chkaddr.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-em1d/config.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-em1d/cpuctrl.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-em1d/diskio.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-em1d/eitproc.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-em1d/hwdepend.h
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-em1d/hwinfo.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-em1d/include/mach/cpudepend.h
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-em1d/include/mach/em1d512.h
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-em1d/memattr.S
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-em1d/misc.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-em1d/setup_em1d512.h
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-em1d/sio.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-em1d/startup.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-em1d/sysdepend.h
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-em1d/system.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/mach-em1d/waitusec.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/misc.c
create mode 100644 tkernel_source/monitor/hwdepend/arm/monent.c
delete mode 100644 tkernel_source/monitor/hwdepend/tef_em1d/build/Makefile
delete mode 100644 tkernel_source/monitor/hwdepend/tef_em1d/src/config.c
delete mode 100644 tkernel_source/monitor/hwdepend/tef_em1d/src/cpuctrl.c
delete mode 100644 tkernel_source/monitor/hwdepend/tef_em1d/src/cpuctrl2.S
delete mode 100644 tkernel_source/monitor/hwdepend/tef_em1d/src/diskio.c
delete mode 100644 tkernel_source/monitor/hwdepend/tef_em1d/src/eitent.S
delete mode 100644 tkernel_source/monitor/hwdepend/tef_em1d/src/eitproc.c
delete mode 100644 tkernel_source/monitor/hwdepend/tef_em1d/src/hwdepend.h
delete mode 100644 tkernel_source/monitor/hwdepend/tef_em1d/src/hwinfo.c
delete mode 100644 tkernel_source/monitor/hwdepend/tef_em1d/src/memattr.S
delete mode 100644 tkernel_source/monitor/hwdepend/tef_em1d/src/misc.c
delete mode 100644 tkernel_source/monitor/hwdepend/tef_em1d/src/reset.S
delete mode 100644 tkernel_source/monitor/hwdepend/tef_em1d/src/setup_em1d512.h
delete mode 100644 tkernel_source/monitor/hwdepend/tef_em1d/src/sio.c
delete mode 100644 tkernel_source/monitor/hwdepend/tef_em1d/src/startup.c
delete mode 100644 tkernel_source/monitor/hwdepend/tef_em1d/src/sysdepend.h
delete mode 100644 tkernel_source/monitor/hwdepend/tef_em1d/src/system.c
delete mode 100644 tkernel_source/monitor/hwdepend/tef_em1d/src/waitusec.c
delete mode 100644 tkernel_source/monitor/include/arm/cpudepend.h
delete mode 100644 tkernel_source/monitor/include/arm/em1d512.h
create mode 100644 tkernel_source/monitor/lib/string.c
delete mode 100644 tkernel_source/monitor/tmmain/build/tef_em1d/Makefile
delete mode 100644 tkernel_source/monitor/tmmain/build/tef_em1d/monitor.lnk
create mode 100644 tkernel_source/monitor/tmmain/version.c
diff --git a/tkernel_source/monitor/bin/tef_em1d/_dmy b/tkernel_source/monitor/bin/tef_em1d/_dmy
deleted file mode 100644
index e69de29..0000000
diff --git a/tkernel_source/monitor/cmdsvc/boot.c b/tkernel_source/monitor/cmdsvc/boot.c
new file mode 100644
index 0000000..0e182a3
--- /dev/null
+++ b/tkernel_source/monitor/cmdsvc/boot.c
@@ -0,0 +1,126 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * boot.c
+ *
+ * boot processing
+ */
+
+#include "cmdsvc.h"
+
+/*
+ * boot information
+ * Information passed to primary boot loader (PBOOT).
+ * This address (&bootinfo) is passed to the primary boot loader and is directly referenced.
+ */
+LOCAL BootInfo bootInfo;
+
+/*
+ * Loading of the primary bootloader (PBOOT).
+ * return value boot partition number
+ */
+LOCAL W loadPBoot( const UB *devnm, DISKCB **dcb_p )
+{
+ W retry = 2;
+ W pno;
+ DISKCB *dcb;
+ ER err;
+
+ while ( --retry >= 0 ) {
+
+ /* opening of a disk device */
+ pno = openDisk(devnm, &dcb);
+ if ( pno < E_OK ) {
+ err = pno;
+ if ( err == E_IO ) continue; /* retry */
+ return err;
+ }
+
+ /* If there is no partition specification in the device name, we assume the boot partition. */
+ if ( pno == 0 ) pno = dcb->boot;
+
+ /* read the boot block inside the target partiion */
+ err = (*dcb->rwdisk)(dcb, dcb->part[pno].sblk, 1,
+ PBootAddr, FALSE);
+ if ( err < E_OK ) {
+ if ( err == E_IO ) continue; /* retry */
+ return err;
+ }
+
+ /* check the signature in the boot block */
+ if ( *(UH*)(PBootAddr + 510) != BootSignature ) return E_BOOT;
+
+ *dcb_p = dcb;
+ return pno;
+ }
+
+ return E_IO;
+}
+
+/*
+ * disk boot
+ * devnm device name (possibly with the partition number)
+ * if it is NULL, the standard search order is used to look for a bootable device.
+ * return value error code
+ */
+EXPORT ER bootDisk( const UB *devnm )
+{
+ DISKCB *dcb;
+ W pno, i, c;
+ ER err;
+
+ if ( devnm != NULL ) {
+ /* boot from the specified device */
+ pno = loadPBoot(devnm, &dcb);
+ if ( pno < E_OK ) return pno;
+ } else {
+ /* Boot using the standard boot order */
+ pno = E_BOOT;
+ for ( i = 0;; i++ ) {
+ devnm = bootDevice(i);
+ if ( devnm == NULL ) break; /* end is seen */
+
+ pno = loadPBoot(devnm, &dcb);
+ if ( pno >= 0 ) break;
+ }
+ }
+ if ( pno >= 0 ) {
+ /* Length of the device name without the partition number */
+ i = strlen(devnm);
+ c = devnm[i - 1];
+ if ( i >= 2 && c >= '0' && c <= '3' ) --i;
+
+ /* Set boot information */
+ strncpy(bootInfo.devnm, devnm, L_DEVNM);
+ bootInfo.devnm[i] = '\0'; /* erase partition number */
+ bootInfo.part = pno - 1;
+ bootInfo.start = dcb->part[pno].sblk;
+ bootInfo.secsz = dcb->blksz;
+
+ /* prepare for primary boot execution */
+ setUpBoot(PBootAddr, &bootInfo);
+
+ } else {
+ /* if boot from disk fails
+ try invoking ROM kernel */
+ err = bootROM();
+ if ( err < E_OK ) {
+ if ( err != E_ABORT ) err = pno;
+ return err;
+ }
+ }
+
+ return E_OK;
+}
diff --git a/tkernel_source/monitor/cmdsvc/build/tef_em1d/Makefile b/tkernel_source/monitor/cmdsvc/build/tef_em1d/Makefile
deleted file mode 100644
index 0f33bf3..0000000
--- a/tkernel_source/monitor/cmdsvc/build/tef_em1d/Makefile
+++ /dev/null
@@ -1,78 +0,0 @@
-#
-# ----------------------------------------------------------------------
-# T-Kernel 2.0 Software Package
-#
-# Copyright 2011 by Ken Sakamura.
-# This software is distributed under the latest version of T-License 2.x.
-# ----------------------------------------------------------------------
-#
-# Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
-# Modified by T-Engine Forum at 2012/11/07.
-# Modified by T-Engine Forum at 2013/03/01.
-# Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
-#
-# ----------------------------------------------------------------------
-#
-
-# T-Monitor : cmdsvc (em1d)
-
-MACHINE = em1d
-TETYPE = tef
-
-SRC_SYSDEP = monhdr.S monent.c chkaddr.c register.c break.c \
- disassemble.c misc.c step.c
-
-# ----------------------------------------------------------------------------
-
-DEPS = Dependencies
-DEPENDENCIES_OUTPUT := $(DEPS)
-
-include $(BD)/etc/makerules
-
-TMONITOR_INSTALLDIR = $(BD)/monitor/bin/$(TETYPE)_$(MACHINE)
-
-HEADER = $(BD)/include $(BD)/monitor/include
-
-# ----------------------------------------------------------------------------
-
-TARGET = cmdsvc
-TARGET2 = wrkbuf
-
-S = ../../src
-
-VPATH = $(S):$(S)/armv6
-HEADER += $(S)
-
-SRC = command.c helpmsg.c svc.c memory.c \
- console.c load.c boot.c string.c
-SRC += $(SRC_SYSDEP)
-
-OBJ = $(addsuffix .o, $(basename $(SRC)))
-
-CFLAGS += $(CFLAGS_WARNING)
-
-# ----------------------------------------------------------------------------
-
-.PHONY: all clean install
-
-ALL = $(TARGET).o $(TARGET2).o
-
-all: $(ALL)
-
-$(TARGET).o: $(OBJ)
- $(LINK_R.o) $^ $(OUTPUT_OPTION)
-
-clean:
- $(RM) $(OBJ) $(ALL) $(DEPS)
-
-install: $(addprefix $(TMONITOR_INSTALLDIR)/, $(ALL))
-
-$(TMONITOR_INSTALLDIR)/%: %
- $(BD)/etc/backup_copy -t -d !OLD $< $(TMONITOR_INSTALLDIR)
-
-ifdef DEPENDENCIES_OUTPUT
- $(DEPS): ; touch $(DEPS)
-else
- $(DEPS): $(SRC) ; $(MAKEDEPS) $@ $?
-endif
--include $(DEPS)
diff --git a/tkernel_source/monitor/cmdsvc/cmdsvc.h b/tkernel_source/monitor/cmdsvc/cmdsvc.h
new file mode 100644
index 0000000..e10e236
--- /dev/null
+++ b/tkernel_source/monitor/cmdsvc/cmdsvc.h
@@ -0,0 +1,307 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by T-Engine Forum at 2013/03/01.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * cmdsvc.h
+ *
+ * T-Monitor command / SVC common processing definitions
+ */
+
+#include <tmonitor.h>
+#include <tm/tmonitor.h>
+
+#if CPU_ARMv6
+# include "armv6/cpudep.h"
+#endif
+
+/* ======================================================================== */
+/*
+ * Hardware-independent
+ */
+
+#define L_LINE 256 /* number of characters per line */
+IMPORT UB lineBuf[L_LINE]; /* line buffer */
+
+#define WRKBUF_SZ 1024 /* must be larger than or equal to 1024 */
+IMPORT UB wrkBuf[WRKBUF_SZ]; /* work buffer for various operations */
+
+#define L_BPCMD 80 /* breakpooint command length */
+
+IMPORT W errinfo; /* error information */
+
+/*
+ * display boot message
+ */
+IMPORT void dispTitle( void );
+
+/*
+ * command execution
+ * cmd command string
+ * if it is NULL, we are wainting for command input
+ * fin = 0 : execute cmd and then wait for command input
+ * > 0 : execute cmd and return
+ * < 0 : execute cmd and return (ignore execution such as GO,STEP, etc.)
+ * if cmd = NULL, fin is ignored. (equivalent to fin = 0)
+ */
+IMPORT void procCommand( UB *cmd, W fin );
+
+/*
+ * loading from serial line
+ * proto [P_XMODEM] | [P_SFORM] (other protocols are ignored)
+ * P_XMODEM XMODEM
+ * not specified no control sequence
+ * P_SFORM S-Record format
+ * not specficied memory image (binary data)
+ * addr load address
+ * In the case of P_SFORM, the initial ooad address is set to addr.
+ * Loading is done with the above adjustment. If addr = 0, adjustment is not madem, but
+ * load it to data address.
+ * range valid load range
+ * range[0] start address of the valid load range
+ * range[1] end address of the valid load range
+ * range[2] load offset
+ * load offset is valid only when P_SFORM is used and addr = 0.
+ * Its value is the sum of the load address added with the range[2] offset value.
+ * This is where loading takes place.
+ * range[0] and range[1] will return the final starting and loading address after the loading.
+ *
+ * if range = NULL, below is assumed.
+ * range[0] = 0x00000000
+ * range[1] = 0xffffffff
+ * range[2] = 0
+ * return value error code
+ */
+IMPORT ER doLoading( W proto, UW addr, UW range[3] );
+
+/* load option (LOAD commands, etc.) */
+#define P_XMODEM 0x20 /* XMODEM */
+#define P_TEXT 0x10 /* no protocol */
+#define P_SFORM 0x02 /* S-Format */
+#define P_MEMIMG 0x01 /* memory image */
+
+/*
+ * Flash ROM disk write
+ * blksz = 0 set up
+ * Prepare writing to ROM disk and return the maximum ROM size
+ * in sz (bytes).
+ * Return the address to which the data to be written to ROM disk should be loaded.
+ * blksz > 0 written
+ * blksz ROM disk block size
+ * sz number of written blocks
+ * return value error code
+ */
+IMPORT W writeRda( UW blksz, UW *sz );
+
+/*
+ * disk boot
+ * devnm device name (possibly with the partition number)
+ * if it is NULL, the standard search order is used to look for a bootable device.
+ * return value error code
+ */
+IMPORT ER bootDisk( const UB *devnm );
+
+/*
+ * monitor service call
+ * fno function code
+ * p1-p4 parameters
+ * return value return value of the service call
+ */
+IMPORT W procSVC( W fno, W p1, W p2, W p3, W p4 );
+
+/* ======================================================================== */
+/*
+ * Hardware-dependent
+ */
+
+/*
+ * disassember
+ * saddr pass the address where the instruction to be disassembled is.
+ * returns the adjusted address that points at the start of the instruction.
+ * naddr returns the address of the next instruction. (if it is NULL, value is not returned)
+ * str the buffer to store the disassembled instruction string (must be long enough)
+ * return value error code
+ */
+IMPORT ER disAssemble( UW *saddr, UW *naddr, UB *str );
+
+/*
+ * examine and obtain the breakpoint attribute
+ * examine the breakpoint attribute string specified by `name', and if it is legal,
+ * return its attribute code as return value.
+ * In the case of illegal attribute string, return an error (E_BPATR).
+ */
+IMPORT W getBreakAtr( UB *name );
+
+/*
+ * set breakpoint
+ * addr address where breakpoint is set
+ * atr breakpoint attribute
+ * cmd command that is to be executed at the breakpoint (valid only when cmdlen > 0)
+ * cmdlen cmd length
+ * return value error code
+ */
+IMPORT ER setBreak( UW addr, W atr, UB *cmd, W cmdlen );
+
+/*
+ * release breakpoint
+ * addr address where breakpoint is to be released
+ * if it is 0, then release all breakpoints
+ * return value error code
+ */
+IMPORT ER clearBreak( UW addr );
+
+/*
+ * list all breakpoints
+ */
+IMPORT void dspBreak( void );
+
+/*
+ * release breakpoint temporarily (monitor entry)
+ * return value if the current PC is not a breakpoint, returns 0.
+ * if it is a breakpoint, returns non-zero value.
+ */
+IMPORT W resetBreak( UW vec );
+
+/*
+ * set breakpoints (monitor exit)
+ */
+IMPORT void setupBreak( void );
+
+/*
+ * forcibly stop trace
+ */
+IMPORT void stopTrace( void );
+
+/*
+ * trace or normal execution
+ * trace 0 : GO command
+ * 1 : STEP command
+ * 2 : NEXT command
+ * pc execution start address
+ * par in the case of GO
+ * tempoary breakpoint address (if 0, then no temporary breakpoionts)
+ * in the case of STEP/NEXT
+ * number of steps (0 is regarded as 1)
+ * return value error code
+ */
+IMPORT ER goTrace( W trace, UW pc, UW par );
+
+/*
+ * break processing
+ * bpflg return the value returned by resetBreak() as is.
+ * cmd return the command to be executed at the breakpoint.
+ * return value 0 : return monitor immediately and contineu executing the user program.
+ * 1 : enter command processing of the monitor and execute cmd.
+ */
+IMPORT W procBreak( W bpflg, UB **cmd );
+
+/*
+ * search register
+ * Return the register number (0 and upward) for the register name `name'.
+ * grp 0 : exclude group names from the search.
+ * 1 : include the group names in the search/
+ * name is L_REGNM bytes long, and if the result is not long enough, the remaining part is filled with space.
+ * L_REGNM is machine-dependent, but should be less than or equal to L_SYMBOL.
+ * if the name is invalid (not found), return -1.
+ */
+IMPORT W searchRegister( UB *name, W grp );
+
+/*
+ * obtain / set register value
+ * regno register number
+ * val value to set
+ * return value obtained set value(if there is an error, 0).
+ * * set : error code
+ */
+IMPORT UW getRegister( W regno );
+IMPORT ER setRegister( W regno, UW val );
+
+/*
+ * display register value
+ * display the register or register group specified by `regno'.
+ * if regno < 0, thendisplay the default register group.
+ */
+IMPORT void dispRegister( W regno );
+
+/*
+ * obtain / set the current PC register
+ */
+IMPORT UW getCurPC( void );
+IMPORT void setCurPC( UW val );
+
+/*
+ * prepare to execute the boot program
+ * pass boot info to a boot program and start it from the address, `start'.
+ *
+ * It means that we don't execute ROM kernel immediately, but we prepare so that upon return from the ordinary monitor,
+ * it gets executed.
+ */
+IMPORT void setUpBoot( void *start, BootInfo *bootinfo );
+
+/*
+ * Prepare ROM kernel execution
+ * It means that we don't execute ROM kernel immediately, but we prepare so that upon return from the ordinary monitor,
+ * it gets executed.
+ */
+IMPORT ER bootROM( void );
+
+/*
+ * Initialize address check data (executed upon monitor entry)
+ */
+IMPORT void initChkAddr( void );
+
+/*
+ * validate memory address
+ * check whether access to area starting from logical address, addr, and has the length of len bytes,
+ * return the corresponding physical address of addr in pa.
+ * rw = 0 for read / rw = 1 for write is checked for the access right check.
+ * Returns the length of accessible bytes for a consecutive region that starts from addr.
+ * if addr is inaccessible, then the size for the accesible region is 0.
+ * So, 0 is returned. In this case, error code is set to a global variable errinfo.
+ * the address returned to pa is machine-depdenent, and may not be a physical address always.
+ */
+IMPORT W chkMemAddr( UW addr, UW *pa, W len, W rw );
+
+/*
+ * validate I/O address
+ * heck whether we can access a region from an I/O address (logical address in the case of memory mapped I/O), with the len bytes length,
+ * the I/O address (physical address if memory mapped I/O is used) is returned
+ * in pa.
+ * Returns the length of accessible bytes for a consecutive region that starts from addr.
+ * if addr is inaccessible, then the size for the accesible region is 0.
+ * So, 0 is returned.
+ * * the address returned to pa is machine-depdenent, and, in the case of memory mapped I/O.
+ * may not be a physical address always. if memory mapped I/O is not used,
+ * generally speaking, pa will return addr unmodiifed.
+ */
+IMPORT W chkIOAddr( UW addr, UW *pa, W len );
+
+/*
+ * Validate PC address
+ * If addr is valid then return 0, otherwise return -1.
+ */
+IMPORT W invalidPC( UW addr );
+
+/*
+ * Check whehter kill command can be executed
+ * If it can be executed, return 0, and if not, return -1.
+ */
+IMPORT W isKillValid( void );
+
+/*
+ * calling an external program
+ */
+IMPORT W callExtProg( FP entry );
+
+/* ------------------------------------------------------------------------ */
diff --git a/tkernel_source/monitor/cmdsvc/command.c b/tkernel_source/monitor/cmdsvc/command.c
new file mode 100644
index 0000000..1025698
--- /dev/null
+++ b/tkernel_source/monitor/cmdsvc/command.c
@@ -0,0 +1,1274 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by T-Engine Forum at 2013/03/04.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * command.c
+ *
+ * command processing
+ */
+
+#include "cmdsvc.h"
+#include "help.h"
+#include <tk/dbgspt.h>
+
+#define DEF_MEM_SIZE 64 /* default memory dump size */
+#define DEF_DA_STEP 16 /* default disassbmle size */
+#define MAX_DSP_CNT 64 /* maximum cut off count for display */
+#define MAX_RANGE 0x1000000 /* maximum range (16 MB) */
+#define IMPLICIT_SIZE 0x1000 /* implicit size specification */
+
+EXPORT UB lineBuf[L_LINE]; /* line buffer */
+EXPORT W killProcReq; /* request to forcibly kill a process */
+
+#define L_SYMBOL 23 /* effective symbol length */
+#define SETDT_SZ 128 /* data size */
+
+#define CMD_FINISH (9999) /* command end specification */
+
+EXPORT W errinfo; /* error information */
+LOCAL W errcode; /* error code */
+
+LOCAL UW dAddr; /* D address command */
+LOCAL UW mAddr; /* M command address */
+LOCAL UW daAddr; /* DA command address */
+LOCAL UW cAddr; /* the current start address */
+LOCAL W cLen; /* the current memory byte length */
+
+LOCAL W token; /* token type */
+LOCAL UW tokenVal; /* numeric token / register number */
+LOCAL UB *tokenStr; /* character string / symbol item pointer */
+LOCAL W tokenLen; /* character string / symbol item length */
+LOCAL UB tokenSym[L_SYMBOL + 1]; /* symbol item string(capital letters) */
+LOCAL UB symExt[2]; /* extended symbol letters */
+LOCAL UB *lptr; /* line pointer */
+
+#define PROMPT "TM> " /* prompt */
+
+/* item type */
+#define tEOL 0x00 /* line end */
+#define tEOC 0x01 /* end of command */
+#define tDLM 0x02 /* delimiter */
+#define tSIZ 0x11 /* size specification */
+#define tOPADD 0x12 /* + operator */
+#define tOPSUB 0x13 /* - operator */
+#define tOPMUL 0x14 /* * operator */
+#define tOPDIV 0x15 /* / operator */
+#define tOPIND 0x16 /* & operator */
+#define tEOD 0x17 /* end of data */
+#define tUP 0x18 /* previous data */
+#define tSYM 0x20 /* symbol */
+#define tNUM 0x21 /* numeric value */
+#define tSTR 0x22 /* character string */
+#define tERRR 0x100 /* error */
+#define tERCH 0x100 /* error: illegal character */
+#define tERNUM 0x101 /* error: illegal numeric form */
+
+/* character classficiation */
+#define isSpace(c) isspace(c) ((c) && (c) <= ' ')
+#define isNum(c) ((c) >= '0' && (c) <= '9')
+#define isAlpha(c) ( ((c) >= 'A' && (c) <= 'Z') ||\
+ ((c) >= 'a' && (c) <= 'z') )
+#define isAlNum(c) (isNum(c) || isAlpha(c))
+#define isSym(c) (isAlpha(c) || c == '$' || c == '_' ||\
+ c == '?' || c == '@')
+#define isExtSym(c) ((c) && ((c) == symExt[0] || (c) == symExt[1]))
+
+/* alignment adjustment */
+#define ALIGN_L(v, unit) ((v) & ~((unit) - 1))
+#define ALIGN_U(v, unit) (((v) + (unit) - 1) & ~((unit) - 1))
+
+/* error return */
+#define return_er(er) return (errcode = er)
+#define er_return(er) {errcode = er; return;}
+#define oer_return(er) {if ((er) == E_NOEXS)\
+ errcode = E_ONOEXS;\
+ else errcode = er;\
+ return;}
+
+#define DB16 0x00000 /* default base number */
+#define DB10 0x10000
+
+/*
+ display error message
+*/
+LOCAL void dspError(void)
+{
+ UB *mp = NULL;
+
+ if (token >= tERRR) { /* priortize the item error */
+ switch(token) {
+ case tERCH: mp = "Illegal Character"; break;
+ case tERNUM: mp = "Illegal Number Format"; break;
+ }
+ } else {
+ if (errinfo < 0) errcode = errinfo;
+ switch(errcode) {
+ case E_MACV: mp = "Illegal Address"; break;
+ case E_ROM: mp = "ROM Address"; break;
+ case E_LESS: if (token <= tEOC)
+ {mp = "Less Parameter"; break;}
+ case E_PAR: mp = "Illegal Parameter"; break;
+ case E_ID: mp = "Illegal ID Number"; break;
+ case E_CTX: mp = "Context Error"; break;
+ case E_LIMIT: mp = "Too Many Parameters"; break;
+ case E_OBJ: mp = "Abnormal Object Status"; break;
+ case E_NOSPT: mp = "Not Supported"; break;
+ case E_NOEXS: mp = "Unknown Device"; break;
+ case E_IO: mp = "I/O Error"; break;
+ case E_RONLY: mp = "Read Only"; break;
+ case E_NOMDA: mp = "No Media"; break;
+ case E_PROTECT: mp = "Write Protected"; break;
+
+ case E_CMD: mp = "Unknown Command"; break;
+ case E_RANGE: mp = "Illegal Address Range"; break;
+ case E_EMPTY: mp = "Empty String"; break;
+ case E_ILREG: mp = "Unknown Register Name"; break;
+ case E_PC: mp = "Illegal PC Value"; break;
+ case E_BOOT: mp = "No Bootable Disk"; break;
+
+ case E_PROTO: mp = "Unknown Load Protocol"; break;
+ case E_NOADDR: mp = "No Load Address"; break;
+ case E_LOADFMT: mp = "Illegal S-Format Record"; break;
+ case E_LOAD: mp = "Loading Error"; break;
+ case E_CANCEL: mp = "Loading Cancelled"; break;
+ case E_XMODEM: mp = "XMODEM Protocol Error"; break;
+
+ case E_BPATR: mp = "Unknown Break Point Attribute"; break;
+ case E_BPBAD: mp = "Illegal Break Point"; break;
+ case E_BPDSLT: mp = "Break Point at Delayed Slot"; break;
+ case E_BPROM: mp = "Break Point in ROM"; break;
+ case E_BPCMD: mp = "Too Long Break Point Command"; break;
+ case E_BPUDF: mp = "Undefined Break Point"; break;
+ case E_SBPOVR: mp = "Too Many Software Break Points"; break;
+ case E_HBPOVR: mp = "Too Many Hardware Break Points"; break;
+
+ case E_ONOEXS: mp = "Noexistent Object"; break;
+ }
+ }
+ if (mp) {
+ DSP_F3(S,"ERR: ", S,mp, CH,'\n');
+ } else {
+ DSP_F3(S,"ERR: [", 08X,errcode, S,"]\n");
+ }
+}
+/*
+ input of a line
+*/
+LOCAL W getLine(UB *msg)
+{
+ if (msg) DSP_S(msg); /* display prompt */
+ memset(lineBuf, 0, sizeof(lineBuf)); /* clear buffer */
+ return getString(lptr = lineBuf); /* input a line and initialize the line pointer */
+}
+/*
+ skip spaces
+*/
+LOCAL void skipSpace(void)
+{
+ while (isSpace(*lptr)) lptr++;
+}
+/*
+ extract hexadecimal value
+*/
+LOCAL W getHexVal(UB **ptr)
+{
+ W c;
+ UW v;
+ UB *p;
+
+ p = *ptr;
+ for (v = 0; ((c = *p) >= '0' && c <= '9') ||
+ (c >= 'A' && c <= 'F') || (c >= 'a' && c <= 'f'); p++) {
+ if (v >= 0x10000000) break; /* overflow */
+ v <<= 4;
+ v += (c >= 'a' ? (c - 'a' + 10) :
+ (c >= 'A' ? (c - 'A' + 10) : ( c - '0')));
+ }
+ *ptr = p;
+ return v;
+}
+/*
+ extract item
+
+ numerical constant: H'<digit> 0x<digit> hexadecimal
+ D'<digital> decimal (base 10)
+ Q'<digit> octal (base 8)
+ B'<digit> binary(base 2)
+ <digit> '<digit> hexadecimal(base 16)
+ character constant: "<character>.." only ASCII characters are allowed
+ symbol: <letter$_><letter$_digit>..
+ operator: + addition
+ - subtraction
+ * multiplication
+ / division
+ & indirect reference
+ separator: ,
+ special symbol: ; EndOfCommand(same as EndOfLine)
+ # size specificication
+ . end of data
+ ^ UP (return to previous line)
+*/
+LOCAL W getToken(W defbase)
+{
+ W c, i, base;
+
+ tokenVal = 0;
+ skipSpace();
+ if ((c = *lptr) == 0) {i = tEOL; goto EXIT;}
+ lptr++;
+
+ if (c == ';') {i = tEOC; goto EXIT;}
+ if (c == ',') {i = tDLM; goto EXIT;}
+ if (c == '#') {i = tSIZ; goto EXIT;}
+ if (c == '.') {i = tEOD; goto EXIT;}
+ if (c == '^') {i = tUP; goto EXIT;}
+ if (c == '+') {i = tOPADD; goto EXIT;}
+ if (c == '-') {i = tOPSUB; goto EXIT;}
+ if (c == '*') {i = tOPMUL; goto EXIT;}
+ if (c == '/') {i = tOPDIV; goto EXIT;}
+ if (c == '&') {i = tOPIND; goto EXIT;}
+
+ if (c == '"') { /* character string */
+ for (tokenStr = lptr; (c = *lptr) && c != '"'; lptr++);
+ tokenLen = lptr - tokenStr;
+ if (c) lptr++;
+ i = tSTR;
+ goto EXIT;
+ }
+
+ if (*lptr == '\'') { /* number with prefix */
+ if (c == 'Q' || c == 'q') {base = 8; goto NUMVAL;}
+ if (c == 'B' || c == 'b') {base = 2; goto NUMVAL;}
+ if (c == 'D' || c == 'd') {base = 10;
+NUMVAL:
+ while ((c = *++lptr) >= '0' && c < base + '0')
+ tokenVal = tokenVal * base + c - '0';
+ goto NUMEXIT;
+ }
+ if (c == 'H' || c == 'h') goto HEXVAL;
+ }
+
+ if (isNum(c)) { /* simple number */
+ if (c != '0' || (*lptr != 'x' && *lptr != 'X')) {
+ lptr -= 2;
+ if (defbase == DB10) {base = 10; goto NUMVAL;}
+ }
+ goto HEXVAL;
+ }
+
+ if (c == '\'') { /* hexadecimal number */
+ lptr--;
+HEXVAL:
+ lptr++;
+ tokenVal = getHexVal(&lptr);
+ c = *lptr;
+NUMEXIT:
+ /* if the end of the numeric value is alphanumeric letter, then it is regarded as illegal numeric format. */
+ i = (isSym(c) || isNum(c)) ? tERNUM : tNUM;
+ goto EXIT;
+ }
+
+ if (isSym(c)) { /* symbol */
+ tokenStr = --lptr;
+ for (i = 0; isSym(c) || isNum(c) || isExtSym(c); c = *++lptr) {
+ /* set to tokenSym[] in capital letters */
+ if (i < L_SYMBOL) {
+ if (c >= 'a' && c <= 'z') c -= 'a' - 'A';
+ tokenSym[i++] = c;
+ }
+ }
+ /* Fill the rest of tokenSym[] with space */
+ while (i < L_SYMBOL) tokenSym[i++] = ' ';
+
+ tokenLen = lptr - tokenStr;
+ i = tSYM;
+ goto EXIT;
+ }
+ /* other: illegal character error */
+ i = tERCH;
+EXIT:
+ return token = i;
+}
+/*
+ check for end of command
+*/
+LOCAL W isnotEOC(void)
+{
+ if (token <= tEOC) return 0;
+ return_er(E_PAR);
+}
+/*
+ check for separator (1)
+*/
+LOCAL W isDLM(void)
+{
+ if (token == tDLM) {getToken(0); return 1;}
+ return 0;
+}
+/*
+ check for separator (2)
+*/
+LOCAL W isnotDLM(void)
+{
+ if (isDLM()) return 0;
+ return_er(E_LESS);
+}
+/*
+ obtain numeric parameter (with performing + - * / operations)
+
+ [+|-] {symbol|numeric value} [{+|-|* |/} {symbol|numeric value}].. {,|EOL}
+*/
+LOCAL W getNumber(W defbase, W *val)
+{
+ W op, v;
+ UB *p;
+
+ /* process leading + and - */
+ if ((op = token) == tOPADD || op == tOPSUB) getToken(defbase);
+
+ for (*val = 0; ;) {
+ if (token == tSYM) { /* register name */
+ if ((v = searchRegister(tokenSym, 0)) >= 0) {
+ tokenVal = getRegister(v);
+ } else { /* hexadecimal value */
+ if (tokenSym[L_SYMBOL - 1] != ' ') break;
+ p = tokenSym;
+ tokenVal = getHexVal(&p);
+ if (*p != ' ') break;
+ }
+ } else if (token != tNUM) {
+ return_er(E_LESS); /* non-numeric value */
+ }
+
+ /* Performing + - * / operations */
+ if (op == tOPADD) *val += tokenVal;
+ else if (op == tOPSUB) *val -= tokenVal;
+ else if (op == tOPMUL) *val *= tokenVal;
+ else if (op == tOPDIV) *val /= tokenVal;
+ else *val = tokenVal;
+
+ /* & operation */
+ while (getToken(defbase) == tOPIND) {
+ if (readMem(*val, &v, 4, 4) != 4) return_er(E_MACV);
+ *val = v;
+ }
+
+ /* extract the next item: if the next item is among "+ - * /" then continue processing */
+ if (token < tOPADD || token > tOPDIV) break;
+ op = token;
+ getToken(defbase);
+ }
+ if (token > tDLM) return_er(E_LESS);
+ return 0;
+}
+/*
+ obtain address range parameter
+
+ [start_addr][,{end_addr|#count}]
+ cAddr = start_addr
+ cLen = count
+
+ flg 0x01 start_addr cannot be omitted
+ 0x02 end_addr|#count (cannot be omitted)
+*/
+LOCAL W getAddrRange(W unit, W flg, W defsz)
+{
+ W sizeflg;
+
+ /* start address */
+ if (token > tDLM) {
+ if (getNumber(0, &cAddr)) return E_LESS;
+ } else {
+ if (flg & 0x01) return_er(E_LESS); /* cannot be omitted */
+ }
+
+ /* align start address */
+ cAddr = ALIGN_L(cAddr, unit);
+
+ /* end address */
+ cLen = defsz;
+ if (token == tDLM) {
+ sizeflg = 0;
+ if (getToken(0) == tSIZ) {
+ getToken(0);
+ sizeflg++;
+ }
+ if (getNumber(0, (UW*)&cLen)) return E_LESS;
+ if (sizeflg == 0) { /* end address: up to "+ size" */
+ if ((UW)cLen >= cAddr || (UW)cLen >= IMPLICIT_SIZE)
+ /* truncate (using the size as unit) */
+ cLen = ((W)((UW)cLen - cAddr) + unit) / unit;
+ }
+ cLen *= unit;
+ } else {
+ if (flg & 0x02) return_er(E_LESS); /* cannot be omitted */
+ }
+
+ /* validate address range */
+ if (cLen <= 0 || cLen > MAX_RANGE) return_er(E_RANGE);
+ if (((cLen + cAddr - 1) ^ cAddr) & 0x80000000) {
+ cLen = (0x80000000 - (cAddr & 0x7fffffff)) / unit;
+ if ((cLen *= unit) == 0) return_er(E_RANGE);
+ }
+ return 0;
+}
+/*
+ extract set data address
+
+ {character string | numeric parameter}[, {character string | numeric parameter}]...EOC
+*/
+LOCAL W getSetData(UB *buf, W unit)
+{
+ W n, k;
+ UW num;
+
+ for (n = 0; ;) {
+ if (token == tSTR) { /* character string */
+ if (tokenLen == 0) return_er(E_EMPTY);
+
+ /* Fill with 0 using 'unit' as data unit. */
+ k = ALIGN_U(tokenLen, unit);
+ if (n + k > SETDT_SZ) return_er(E_LIMIT);
+ memcpy(&buf[n], tokenStr, tokenLen);
+ n += tokenLen;
+ if ((k -= tokenLen) > 0) memset(&buf[n], 0, k);
+ n += k;
+ getToken(0);
+ } else { /* numeric parameter */
+ if (n + unit > SETDT_SZ) return_er(E_LIMIT);
+ if (getNumber(0, &num)) return E_LESS;
+ switch (unit) {
+ case 4: *((UW*)&buf[n]) = (UW)num; break;
+ case 2: *((UH*)&buf[n]) = (UH)num; break;
+ default: buf[n] = (UB)num;
+ }
+ n += unit;
+ }
+ if (token <= tEOC) break;
+ if (isnotDLM()) return E_LESS;
+ }
+ if (n == 0) return_er(E_EMPTY);
+ return n; /* data length */
+}
+/*
+ memory read (with error message)
+*/
+LOCAL W reaMemory(UW addr, void *dt, W len, W unit)
+{
+ W n;
+
+ if ((n = readMem(addr, dt, len, unit)) == len) return 0;
+ DSP_F3(S,"ERR: Memory Read at H'", 08X,(addr+n), CH,'\n');
+ return -1;
+}
+/*
+ memory write (with error message)
+*/
+LOCAL W wriMemory(UW addr, void *dt, W len, W unit)
+{
+ W n;
+
+ if ((n = writeMem(addr, dt, len, unit)) == len) return 0;
+ DSP_F3(S,"ERR: Memory Write at H'", 08X,(addr+n), CH,'\n');
+ return -1;
+}
+/*
+ display memory content
+*/
+LOCAL void dspMemory(void *p, W unit)
+{
+ switch (unit) {
+ case 4: DSP_F2(08X,*((UW*)p), CH,' '); break;
+ case 2: DSP_F2(04X,*((UH*)p), CH,' '); break;
+ default: DSP_F2(02X,*((UB*)p), CH,' ');
+ }
+}
+/*
+ memroy dump command processing
+
+ D [start_addr][,{end_addr|#data_cnt}]
+ DB [start_addr][,{end_addr|#data_cnt}]
+ DH [start_addr][,{end_addr|#data_cnt}]
+ DW [start_addr][,{end_addr|#data_cnt}]
+*/
+LOCAL void cmdDump(W unit)
+{
+ W i, n, k;
+ UB *cp, *ep;
+
+ /* extract address range */
+ cAddr = dAddr;
+ if (getAddrRange(unit, 0x00, DEF_MEM_SIZE) || isnotEOC()) return;
+
+ /* dump memory content */
+ ep = cp = wrkBuf;
+ for (dAddr = cAddr, i = 0; i < cLen;) {
+ /* display address */
+ if ((i % 16) == 0) DSP_F2(08X,dAddr, S,": ");
+
+ /* obtain memory content */
+ if (cp >= ep) {
+ if ((n = cLen - i) > WRKBUF_SZ) n = WRKBUF_SZ;
+ k = readMem(dAddr, cp = wrkBuf, n, unit);
+ if (n != k) {
+ errcode = E_MACV;
+ cLen = i + k;
+ }
+ ep = cp + k;
+ }
+ /* display memory content */
+ if (i < cLen) {
+ dspMemory(cp, unit);
+ cp += unit;
+ dAddr += unit;
+ i += unit;
+ }
+ /* display character */
+ if ((n = i % 16) == 0 || i >= cLen) {
+ k = 16 - n;
+ if (n) { /* move forward to where we start character dump */
+ n = k / unit * (unit * 2 + 1);
+ while (n-- > 0) DSP_CH(' ');
+ }
+ k = (i % 16) ? (i % 16) : 16;
+ for (cp -= k; cAddr < dAddr; cAddr++) {
+ n = *cp++;
+ DSP_CH((n >= ' ' && n < 0x7f) ? n : '.');
+ }
+ DSP_LF;
+ }
+ if (checkAbort()) {DSP_LF; break;}
+ }
+}
+/*
+ memory update command processing
+
+ M [start_addr][,data]..
+ MB [start_addr][,data]..
+ MH [start_addr][,data]..
+ MW [start_addr][,data]..
+*/
+LOCAL void cmdModify(W unit)
+{
+ W n;
+ UB buf[4];
+ UB svbuf[L_LINE];
+ UB *svlptr, svtoken;
+ UB dt[SETDT_SZ];
+
+ /* start address */
+ cAddr = mAddr;
+ if (token > tDLM && getNumber(0, &cAddr)) return;
+
+ /* align address */
+ cAddr = ALIGN_L(cAddr, unit);
+
+ if (token <= tEOC) { /* interactive processing */
+ /* save command line */
+ memcpy(svbuf, lineBuf, L_LINE);
+ svlptr = lptr;
+ svtoken = token;
+
+ for (;;) {
+ DSP_F2(08X,cAddr, S,": "); /* display address */
+ if (reaMemory(cAddr, buf, unit, unit)) break;
+ dspMemory(buf, unit); /* display data */
+
+ if (getLine("-> ") < 0) break; /* input set data */
+ if (getToken(0) == tEOD) break; /* end of data */
+ if (token <= tEOC) cAddr += unit; /* skip */
+ else if (token == tUP) cAddr -= unit; /* previous */
+ else if ((n = getSetData(dt, unit)) < 0) break;
+ else {
+ if (wriMemory(cAddr, dt, n, unit)) break;
+ cAddr += n;
+ }
+ }
+ /* restore command line */
+ memcpy(lineBuf, svbuf, L_LINE);
+ lptr = svlptr;
+ token = svtoken;
+ if (errcode == E_LESS) errcode = E_PAR;
+
+ } else if (! isnotDLM()) { /* set data processing */
+ if ((n = getSetData(dt, unit)) > 0) {
+ if (wriMemory(cAddr, dt, n, unit) == 0) cAddr += n;
+ }
+ }
+ mAddr = cAddr;
+}
+/*
+ memory embedding command processing
+
+ F start_addr,{end_addr|#data_cnt}[,data]..
+ FB start_addr,{end_addr|#data_cnt}[,data]..
+ FH start_addr,{end_addr|#data_cnt}[,data]..
+ FW start_addr,{end_addr|#data_cnt}[,data]..
+*/
+LOCAL void cmdFill(W unit)
+{
+ W n;
+ UB dt[SETDT_SZ];
+
+ /* extract address range */
+ if (getAddrRange(unit, 0x03, DEF_MEM_SIZE)) return;
+
+ /* extract set data */
+ if (token <= tEOC) {
+ memset(dt, 0, sizeof(UW)); /* 0 by default */
+ n = unit;
+ } else {
+ if (isnotDLM()) return;
+ if ((n = getSetData(dt, unit)) < 0) return;
+ }
+
+ /* embed set data into memory */
+ if (n == unit) { /* fast processing */
+ wriMemory(cAddr, dt, cLen, unit | 0x10);
+ } else { /* ordinary mode */
+ for (; cLen > 0; cLen -= n, cAddr += n) {
+ if (n > cLen) n = cLen;
+ if (wriMemory(cAddr, dt, n, unit)) break;
+ }
+ }
+}
+/*
+ memory search command processing
+
+ SC start_addr,{end_addr|#data_cnt},search_data..
+ SCB start_addr,{end_addr|#data_cnt},search_data..
+ SCH start_addr,{end_addr|#data_cnt},search_data..
+ SCW start_addr,{end_addr|#data_cnt},search_data..
+*/
+LOCAL void cmdSearch(W unit)
+{
+ W n, len, cnt, ofs;
+ UB *cp, *ep;
+ UB dt[SETDT_SZ];
+
+ /* extract address range */
+ if (getAddrRange(unit, 0x01, DEF_MEM_SIZE) || isnotDLM()) return;
+
+ /* extract search data */
+ if ((len = getSetData(dt, unit)) < 0) return;
+
+ ep = cp = wrkBuf;
+ for (ofs = cnt = 0; ; ) {
+ /* obtain memory content */
+ if (cp >= ep) {
+ if ((n = WRKBUF_SZ - ofs) > cLen) n = cLen;
+ if (ofs + n < len) break; /* end */
+ if (reaMemory(cAddr, &wrkBuf[ofs], n, unit)) break;
+ cAddr += n;
+ cLen -= n;
+ ep = (cp = wrkBuf) + ofs + n;
+ }
+ /* check if the leading byte matches */
+ for ( ; cp < ep && *cp != dt[0]; cp += unit);
+ if ((ofs = ep - cp) < len) {
+ /* if enough data is not there, move to the beginning of buffer. */
+ if (ofs > 0) memcpy(wrkBuf, ep = cp, ofs);
+ continue;
+ }
+ /* check for the matching of whole data */
+ if (memcmp(cp, dt, len) == 0) {
+ if (++cnt > MAX_DSP_CNT) {
+ DSP_S("..More..\n");
+ break;
+ }
+ DSP_F2(08X,(cAddr - (ep - cp)), S,":\n");
+ }
+ /* next */
+ cp += unit;
+ ofs = 0;
+ if (checkAbort()) break;
+ }
+}
+/*
+ memory comparison / move command processing
+
+ CMP start_addr,{end_addr|#data_cnt},target_addr
+ MOV start_addr,{end_addr|#data_cnt},target_addr
+*/
+LOCAL void cmdCmpMov(W mov)
+{
+ UW dst;
+ W i, n, cnt;
+#define BFSZ (WRKBUF_SZ / 2)
+
+ /* extract address range */
+ if (getAddrRange(1, 0x01, DEF_MEM_SIZE) || isnotDLM()) return;
+
+ /* transfer / compare target */
+ if (getNumber(0, &dst) || isnotEOC()) return;
+
+ if (mov) { /* memory transfer */
+ for (; (n = cLen) > 0 && checkAbort() == 0;
+ cAddr += n, dst += n, cLen -= n) {
+ if (n > WRKBUF_SZ) n = WRKBUF_SZ;
+ if (reaMemory(cAddr, wrkBuf, n, 1)) break;
+ if (wriMemory(dst, wrkBuf, n, 1)) break;
+ }
+
+ } else { /* memory comparison */
+ for (cnt = 0; (n = cLen) > 0 && checkAbort() == 0;
+ cAddr += n, dst += n, cLen -= n) {
+ if (n > BFSZ) n = BFSZ;
+ if (reaMemory(cAddr, wrkBuf, n, 1)) break;
+ if (reaMemory(dst, &wrkBuf[BFSZ], n, 1)) break;
+ if (memcmp(wrkBuf, &wrkBuf[BFSZ], n) == 0) continue;
+ for (i = 0; i < n; i++) {
+ if (wrkBuf[i] == wrkBuf[BFSZ + i]) continue;
+ if (++cnt > MAX_DSP_CNT) {
+ DSP_S("..More..\n");
+ cLen = 0; /* terminate */
+ break;
+ }
+ DSP_F4(08X,(cAddr + i), S,": ",
+ 02X,wrkBuf[i], S," -> ");
+ DSP_F4(08X,(dst + i), S,": ",
+ 02X,(wrkBuf[BFSZ + i]), CH,'\n');
+ }
+ }
+ }
+}
+/*
+ I/O port input and output command processing
+
+ IB/IH/IW port
+ OB/OH/OW port, data
+*/
+LOCAL void cmdIO(W unit)
+{
+ UW port, data;
+ UB *dir;
+
+ /* extract port number */
+ if (getNumber(0, &port)) return;
+
+ if (unit & 0x10) { /* output command */
+ if (!isDLM()) er_return(E_LESS);
+ if (getNumber(0, &data) || isnotEOC()) return;
+ if (writeIO(port, data, unit &= 0x0f) == 0) er_return(E_MACV);
+ dir = "<--";
+ } else { /* input command */
+ if (isnotEOC()) return;
+ if (readIO(port, &data, unit) == 0) er_return(E_MACV);
+ dir = "-->";
+ }
+ /* display result */
+ DSP_F2(S,"Port ", 08X,port);
+ switch (unit) {
+ case 4: DSP_F5(S,":W ", S,dir, CH,' ', 08X,(UW)data, CH,'\n');
+ break;
+ case 2: DSP_F5(S,":H ", S,dir, CH,' ', 04X,(UH)data, CH,'\n');
+ break;
+ default:DSP_F5(S,":B ", S,dir, CH,' ', 02X,(UB)data, CH,'\n');
+ break;
+ }
+}
+/*
+ disasseble command processing
+
+ DA [start_addr][,steps]
+*/
+LOCAL void cmdDisasm(void)
+{
+ er_return(E_NOSPT);
+}
+/*
+ display / set register command processing
+
+ R [register_name[,data]]
+*/
+LOCAL void cmdRegister(void)
+{
+ W rno;
+ UW num;
+
+ if (token <= tEOC) { /* ordinary register dump */
+ dispRegister(-1);
+
+ } else { /* extract register name */
+ if (token != tSYM || (rno = searchRegister(tokenSym, 1)) < 0)
+ er_return(E_ILREG);
+
+ if (getToken(0) <= tEOC) { /* display register */
+ dispRegister(rno);
+
+ } else if (!isnotDLM() && !getNumber(0, &num)) { /* set register */
+ if (!isnotEOC())
+ er_return(setRegister(rno, num));
+ }
+
+
+ }
+}
+/*
+ execute / trace command processing
+
+ G [start_addr][,end_addr]
+ S/N [start_addr][,steps]
+*/
+LOCAL void cmdGoTrace(W trace)
+{
+ UW pc, par;
+
+ /* extract execution address */
+ pc = getCurPC();
+ if (token > tDLM && getNumber(0, &pc)) return;
+ if (invalidPC(pc)) er_return(E_PC);
+
+ /* extract end address or number of steps */
+ par = 0;
+ if (isDLM()) {
+ if (getNumber(0, &par)) return;
+ if (trace == 0 && invalidPC(par)) er_return(E_MACV);
+ }
+ if (isnotEOC()) return;
+
+ if (trace && par <= 0) par = 1; /* number of steps */
+
+ /*execute program */
+ errcode = goTrace(trace, pc, par);
+ if (errcode >= E_OK) errcode = CMD_FINISH; /*command process termination */
+}
+/*
+ display / set breakpoint command processing
+
+ B [break_addr[,break_attr][,commands]]
+*/
+LOCAL void cmdBreak( void )
+{
+ UW addr;
+ W atr, cmdlen;
+ UB *cmd;
+
+ if (token <= tEOC) { /* display breakpoint */
+ dspBreak();
+ return;
+ }
+
+ /* extract breakpoint address */
+ if (getNumber(0, &addr)) return;
+
+ /* extract break attribute and command */
+ atr = cmdlen = 0;
+ cmd = NULL;
+ while (token == tDLM) {
+ /* "+:" are handled as symbols */
+ symExt[0] = '+'; symExt[1] = ':';
+ getToken(0);
+ symExt[0] = symExt[1] = '\0';
+ if (token == tSYM) {
+ if (atr) break;
+ if ((atr = getBreakAtr(tokenSym)) < 0)
+ er_return(E_BPATR);
+ } else if (token == tSTR) {
+ if (cmdlen) break;
+ if ((cmdlen = tokenLen) > L_BPCMD) er_return(E_BPCMD);
+ cmd = tokenStr;
+ }
+ getToken(0);
+ }
+
+ /*set breakpoint */
+ if (! isnotEOC()) {
+ if ((atr = setBreak(addr, atr, cmd, cmdlen))) er_return(atr);
+ }
+}
+/*
+ clear breakpoint command processing
+
+ BC [break_addr][,break_addr]..
+*/
+LOCAL void cmdBrkClr(void)
+{
+ UW addr;
+
+ if (token <= tEOC) {
+ clearBreak(0); /* clear all */
+ } else {
+ do { /* clear individual breakpoint */
+ if (getNumber(0, &addr)) return;
+ if (clearBreak(addr) < 0) er_return(E_BPUDF);
+ } while (isDLM());
+ isnotEOC();
+ }
+}
+/*
+ download command processing
+
+ LO protocol[,loading_addr]
+*/
+LOCAL void cmdLoad(void)
+{
+ W i, par;
+ UW addr;
+LOCAL const struct {
+ UB nm[2];
+ UH par;
+} proto[] = {
+ {"S ", P_TEXT | P_SFORM},
+ {"XS", P_XMODEM | P_SFORM},
+ {"XM", P_XMODEM | P_MEMIMG},
+ {" ", 0x00}
+};
+
+ /* extract protocol */
+ if (token != tSYM) er_return(E_LESS);
+
+ par = 0;
+ if (tokenSym[2] == ' ') {
+ for (i = 0; proto[i].par != 0; i++) {
+ if (memcmp(tokenSym, proto[i].nm, sizeof(UH)) == 0) {
+ par = proto[i].par;
+ break;
+ }
+ }
+ }
+ if (par == 0) er_return(E_PROTO);
+
+ /* extract start address */
+ getToken(0);
+ if (isDLM()) {
+ if (getNumber(0, &addr)) return;
+ } else {
+ addr = 0;
+ if (par & P_MEMIMG) er_return(E_NOADDR);
+ }
+ if (isnotEOC()) return;
+
+ /* execute loading */
+ errcode = doLoading(par, addr, NULL);
+}
+/*
+ backtrace command processing
+
+ BTR
+*/
+LOCAL void cmdBackTrace(void)
+{
+ er_return(E_NOSPT);
+}
+/*
+ disk command processing
+
+ RD device, sblk, nblk, addr
+ WD device, sblk, nblk, addr
+ ID device
+ BD [device]
+*/
+LOCAL void cmdDisk(W kind)
+{
+ W i;
+ UW par[3], blksz, nblks;
+ UB c, devnm[L_DEVNM + 1];
+
+ /* extract device name */
+ if (token <= tEOC) {
+ if (kind != 3) er_return(E_LESS);
+ devnm[0] = '\0';
+ } else {
+ if (token != tSYM || tokenLen > L_DEVNM) er_return(E_LESS);
+ /* device names are to be given in lower case letters */
+ for (i = 0; i < tokenLen; i++) {
+ c = tokenSym[i];
+ if (c >= 'A' && c <= 'Z') c += 'a' - 'A';
+ devnm[i] = c;
+ }
+ devnm[i] = '\0';
+ getToken(0);
+ }
+
+ /* extract parameters */
+ if (kind <= 1) {
+ for (i = 0; i < 3; i++) {
+ if (isnotDLM()) return;
+ if (getNumber(0, &par[i])) return;
+ }
+ }
+ if (isnotEOC()) return;
+
+ switch(kind) {
+ case 0: /* ReadDisk */
+ case 1: /* WriteDisk */
+ errcode = rwDisk(devnm, par[0], par[1], (void*)par[2], kind);
+ break;
+ case 2: /* InfoDisk */
+ errcode = infoDisk(devnm, &blksz, &nblks);
+ if (errcode >= E_OK) {
+ DSP_S(devnm);
+ DSP_F5(S,": Bytes/block: ", D,blksz,
+ S," Total blocks: ", D,nblks, CH,'\n');
+ }
+ break;
+ case 3: /* BootDisk */
+ errcode = bootDisk(( devnm[0] == '\0' )? NULL: devnm);
+ if (errcode >= E_OK) errcode = CMD_FINISH; /* Fin */
+ break;
+ }
+}
+/*
+ exit command processing
+
+ EX [par]
+*/
+LOCAL void cmdExit(void)
+{
+ W par;
+
+ /* extract parameters */
+ if (token <= tDLM) par = 0;
+ else if (getNumber(0, &par)) return;
+
+ DSP_S((par < 0) ? "** System Reset\n" : "** System Power Off\n");
+ waitMsec(100); /* give extra time for draining the remaining output */
+
+ sysExit(par); /* system reset or power off (never returnes) */
+}
+/*
+ forcible kill process command processing
+
+ KILL
+*/
+LOCAL void cmdKill(void)
+{
+ if (isnotEOC()) return;
+ if (isKillValid() == 0) {
+ killProcReq = 1;
+ errcode = CMD_FINISH;
+ }
+}
+/*
+ FROM write command processing
+
+ WROM
+*/
+LOCAL void cmdWrom(void)
+{
+ UW addr, data;
+ W nsec;
+
+ /* extract parameters */
+ if (getNumber(0, &addr)) return;
+ if (isnotDLM() || getNumber(0, &data)) return;
+ if (isnotDLM() || getNumber(0, &nsec)) return;
+ if (isnotEOC()) return;
+ errcode = writeFrom(addr, data, nsec, 1);
+}
+/*
+ FLASH ROM load command processing
+
+ FLLO [attr]
+*/
+LOCAL void cmdFlashLoad(void)
+{
+ W i, proto, mode;
+ UW addr[3];
+
+ proto = P_TEXT | P_SFORM;
+ mode = 0;
+
+ /* extract attributes */
+ if (token > tEOC) {
+ if (token != tSYM) er_return(E_PAR);
+ for (i = 0; i < L_SYMBOL; i++) {
+ switch(tokenSym[i]) {
+ case 'X': proto = P_XMODEM | P_SFORM; break;
+ case 'E': mode = 1; break;
+ case ' ': i = L_SYMBOL; break;
+ default: er_return(E_PAR);
+ }
+ }
+ getToken(0);
+ if (isnotEOC()) return;
+ }
+
+ /* execute loading */
+ setupFlashLoad(0, addr);
+ i = addr[1] - addr[0] + 1;
+ if (mode) {
+ DSP_S("Fill Loading RAM Area with 0xFF\n");
+ memset((void*)addr[0], 0xFF, i);
+ } else {
+ DSP_S("Copy Flash ROM Image to RAM Area\n");
+ memcpy((void*)addr[0], (void*)(addr[0] - addr[2]), i);
+ }
+ DSP_S("> Load S-Format Data of Flash ROM\n");
+ errcode = doLoading(proto, 0, addr);
+ if (errcode < 0) return;
+
+ /* FLASH ROM write */
+ setupFlashLoad(-1, addr);
+ DSP_F5(S,"Writing Flash ROM at ", 08X,addr[0],
+ S," [", D,addr[2], S," blks] ... wait\n");
+ errcode = writeFrom(addr[0], addr[1], addr[2], -1);
+}
+/*
+ command table
+*/
+typedef struct {
+ UB fnm[12]; /* full command name */
+ UB snm[4]; /* abbreviated command name */
+ FP func; /* processing function */
+ W para; /* parameter information and other */
+ HELP *help; /* help message */
+} CMDTAB;
+
+#define IGN_TRACE 0x1000
+
+LOCAL void cmdHelp(void);
+
+LOCAL const CMDTAB cmdTab[] = {
+ {"DUMP ","D ", cmdDump, 1, &helpD },
+ {"DUMPBYTE ","DB ", cmdDump, 1, &helpDB },
+ {"DUMPHALF ","DH ", cmdDump, 2, &helpDH },
+ {"DUMPWORD ","DW ", cmdDump, 4, &helpDW },
+ {"MODIFY ","M ", cmdModify, 1, &helpM },
+ {"MODIFYBYTE ","MB ", cmdModify, 1, &helpMB },
+ {"MODIFYHALF ","MH ", cmdModify, 2, &helpMH },
+ {"MODIFYWORD ","MW ", cmdModify, 4, &helpMW },
+ {"FILL ","F ", cmdFill, 1, &helpF },
+ {"FILLBYTE ","FB ", cmdFill, 1, &helpFB },
+ {"FILLHALF ","FH ", cmdFill, 2, &helpFH },
+ {"FILLWORD ","FW ", cmdFill, 4, &helpFW },
+ {"SEARCH ","SC ", cmdSearch, 1, &helpSC },
+ {"SEARCHBYTE ","SCB ", cmdSearch, 1, &helpSCB },
+ {"SEARCHHALF ","SCH ", cmdSearch, 2, &helpSCH },
+ {"SEARCHWORD ","SCW ", cmdSearch, 4, &helpSCW },
+ {"COMPARE ","CMP ", cmdCmpMov, 0, &helpCMP },
+ {"MOVE ","MOV ", cmdCmpMov, 1, &helpMOV },
+ {"INPUTBYTE ","IB ", cmdIO, 1, &helpIB },
+ {"INPUTHALF ","IH ", cmdIO, 2, &helpIH },
+ {"INPUTWORD ","IW ", cmdIO, 4, &helpIW },
+ {"OUTPUTBYTE ","OB ", cmdIO, 0x11, &helpOB },
+ {"OUTPUTHALF ","OH ", cmdIO, 0x12, &helpOH },
+ {"OUTPUTWORD ","OW ", cmdIO, 0x14, &helpOW },
+ {"DISASSEMBLE ","DA ", cmdDisasm, 0, &helpDA },
+ {"REGISTER ","R ", cmdRegister, 0, &helpR },
+ {"BREAKPOINT ","B ", cmdBreak, 0, &helpB },
+ {"BREAKCLEAR ","BC ", cmdBrkClr, 0, &helpBC },
+ {"GO ","G ", cmdGoTrace, 0 | IGN_TRACE, &helpG },
+ {"STEP ","S ", cmdGoTrace, 1 | IGN_TRACE, &helpS },
+ {"NEXT ","N ", cmdGoTrace, 2 | IGN_TRACE, &helpN },
+ {"BACKTRACE ","BTR ", cmdBackTrace, 0, &helpBTR },
+ {"LOAD ","LO ", cmdLoad, 0, &helpLO },
+ {"READDISK ","RD ", cmdDisk, 0, &helpRD },
+ {"WRITEDISK ","WD ", cmdDisk, 1, &helpWD },
+ {"INFODISK ","ID ", cmdDisk, 2, &helpID },
+ {"BOOTDISK ","BD ", cmdDisk, 3, &helpBD },
+ {"KILL ","KILL", cmdKill, 0, &helpKILL },
+ {"WRITEROM ","WROM", cmdWrom, 0, &helpWROM },
+ {"FLASHLOAD ","FLLO", cmdFlashLoad, 0, &helpFLLO },
+ {"HELP ","H ", cmdHelp, 0, &helpH },
+ {"HELP ","? ", cmdHelp, 0, &helpH },
+ {"EXIT ","EX ", cmdExit, 0, &helpEX },
+ { } /* end */
+};
+/*
+ searching command
+*/
+LOCAL W searchCommand(void)
+{
+ W i;
+
+ if (token == tSYM && tokenSym[12] == ' ') {
+ for (i = 0; cmdTab[i].func != NULL; i++) {
+ if (memcmp(cmdTab[i].fnm, tokenSym, 12) == 0 ||
+ (tokenSym[4] == ' ' &&
+ memcmp(cmdTab[i].snm, tokenSym, sizeof(UW)) == 0) )
+ return i;
+ }
+ }
+ return E_CMD;
+}
+/*
+ help command pcrocessing
+
+ H(?) [command]
+*/
+LOCAL void cmdHelp(void)
+{
+ W i;
+
+ i = searchCommand();
+ printHelp(( i < 0 )? &helpALL: cmdTab[i].help);
+}
+/*
+ command interpreter
+
+ cmd : initial command line (if NULL : none)
+ fin : 0 = continue, 1 = finish (command execution)
+ < 0 : trace command execution
+*/
+EXPORT void procCommand(UB *cmd, W fin)
+{
+ W i, par;
+
+ /* initialize command input */
+ if (cmd) {
+ strcpy(lptr = lineBuf, cmd);
+ token = tEOC;
+ } else {
+ token = tEOL;
+ fin = 0;
+ }
+
+ /* set DA address to PC */
+ daAddr = getCurPC();
+
+ for (;;) {
+ /* skip the remainder of the previous command */
+ while (token > tEOC) getToken(0);
+
+ /* input a command line */
+ if (token == tEOL) {
+ if (fin) break; /* end */
+ if (getLine(PROMPT) <= 0) continue;
+ }
+
+ /* skip comment */
+ skipSpace();
+ if (*lptr == '*') {
+ getToken(0);
+ continue;
+ }
+ /* extract command */
+ if (getToken(0) <= tEOC) continue; /* skip empty line */
+
+ /* searching command */
+ errcode = errinfo = 0;
+ if ((i = searchCommand()) < 0) {
+ errcode = E_CMD;
+ } else {
+ if (checkAbort()) continue;
+ par = cmdTab[i].para;
+
+ /* if there is an initial command, the execution command is ignored */
+ if (fin < 0 && (par & IGN_TRACE)) continue;
+
+ /* read-ahead of parameters */
+ getToken(0);
+
+ /* command execution */
+ (*(cmdTab[i].func))(par & 0xff);
+ }
+ if (errcode == CMD_FINISH) break; /* finish */
+
+ /* display error */
+ if (errcode < 0) dspError();
+ }
+}
diff --git a/tkernel_source/monitor/cmdsvc/console.c b/tkernel_source/monitor/cmdsvc/console.c
new file mode 100644
index 0000000..ea95744
--- /dev/null
+++ b/tkernel_source/monitor/cmdsvc/console.c
@@ -0,0 +1,293 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * console.c
+ *
+ * console I/O
+ */
+
+#include "cmdsvc.h"
+
+/* control characters */
+#define BS ('H'-'@')
+#define CAN ('X'-'@')
+#define CTLC ('C'-'@')
+#define DEL (0x7f)
+#define CR (0x0d)
+#define LF (0x0a)
+#define XOFF ('S'-'@')
+#define XON ('Q'-'@')
+#define ERASE ('K'-'@')
+#define CAN2 ('U'-'@')
+#define TAB ('I'-'@')
+#define ESC ('['-'@')
+#define CUR_UP ('P'-'@') /* or ESC [ A */
+#define CUR_DWN ('N'-'@') /* or ESC [ B */
+#define CUR_FWD ('F'-'@') /* or ESC [ C */
+#define CUR_BWD ('B'-'@') /* or ESC [ D */
+
+#define HISTBUF_SZ 1024 /* history buffer size */
+
+LOCAL UB hist[HISTBUF_SZ]; /* history buffer */
+LOCAL W CTRL_C_IN; /* CTRL-C input flag */
+LOCAL W XOFF_IN; /* XOFF input flag */
+LOCAL const UB Digit[] = "0123456789ABCDEF";
+
+/*
+ * detect CTRL-C
+ * check if there is a history of control-C input to the console
+ * history is cleared
+ * return value TRUE : CTRL-C input exists
+ * FALSE : CTRL-C input is absent
+ */
+EXPORT BOOL checkAbort( void )
+{
+ if (CTRL_C_IN) {CTRL_C_IN = 0; return TRUE;}
+ return FALSE;
+}
+
+/*
+ * console output (one character)
+ * XON/XOFF flow control
+ * check for CTRL-C input
+ * return value 0 : normal
+ * -1 : CTRL-C input exists
+ */
+EXPORT W putChar( W c )
+{
+ W ch;
+
+ if (XOFF_IN || (ch = getSIO(0)) == XOFF) {
+ while ((ch = getSIO(1)) != XON && ch != CTLC);
+ XOFF_IN = 0;
+ }
+ if (ch == CTLC) {CTRL_C_IN++; return -1;}
+ if (c == LF) putSIO(CR);
+ putSIO(c);
+ return 0;
+}
+
+/*
+ * console output (character string)
+ * XON/XOFF flow control
+ * check for CTRL-C input
+ * return value 0 : normal
+ * -1 : CTRL-C input exists
+ */
+EXPORT W putString( const UB *str )
+{
+ UB c;
+
+ while ((c = *str++)) {
+ if (putChar(c) < 0) return -1;
+ }
+ return 0;
+}
+
+/*
+ * console output (hexadecimal: 2, 4, or 8 columns)
+ * XON/XOFF flow control
+ * check for CTRL-C input
+ * return value 0 : normal
+ * -1 : CTRL-C input exists
+ */
+EXPORT W putHex2( UB val )
+{
+ if (putChar(Digit[(val >> 4) & 0x0f]) < 0) return -1;
+ if (putChar(Digit[(val >> 0) & 0x0f]) < 0) return -1;
+ return 0;
+}
+
+EXPORT W putHex4( UH val )
+{
+ if (putHex2(val >> 8) < 0) return -1;
+ if (putHex2(val >> 0) < 0) return -1;
+ return 0;
+}
+
+EXPORT W putHex8( UW val )
+{
+ if (putHex2(val >> 24) < 0) return -1;
+ if (putHex2(val >> 16) < 0) return -1;
+ if (putHex2(val >> 8) < 0) return -1;
+ if (putHex2(val >> 0) < 0) return -1;
+ return 0;
+}
+
+/*
+ * console output (decimal: 10 columns/zero-suppress supported)
+ * XON/XOFF flow control
+ * check for CTRL-C input
+ * return value 0 : normal
+ * -1 : CTRL-C input exists
+ */
+EXPORT W putDec( UW val )
+{
+ W i;
+ UB d[11]; /* required columns for displaying 32-bit maximum cardinal(4,294,967,295) +1 */
+
+ for (i = 0; i < sizeof(d); i++) {
+ d[i] = Digit[val % 10];
+ val /= 10;
+ if (!val) break;
+ }
+
+ for (; i >= 0; i--) {
+ if (putChar(d[i]) < 0) return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * console input (one character)
+ * if wait = TRUE, wait for input if FALSE, do not wait.
+ * return value >= 0 : character
+ * -1 : no input
+ */
+EXPORT W getChar( BOOL wait )
+{
+ W c;
+
+ for (;;) {
+ if ((c = getSIO(0)) == XOFF) XOFF_IN = 1;
+ else if (c != -1 || !wait) break;
+ }
+ return c;
+}
+
+/*
+ * consle input (character string)
+ * line input with editing
+ * return value >= 0 : number of input characters
+ * -1 : CTRL-C was detected
+ */
+EXPORT W getString( UB *str )
+{
+ W i, c, c1;
+ W cp, ep, hp, esc;
+ W len;
+
+ CTRL_C_IN = 0;
+ c = c1 = 0;
+ cp = ep = esc = 0;
+ hp = -1;
+
+ while (ep < L_LINE - 2) {
+ if ((c = getSIO(0)) <= 0) continue;
+ len = 1;
+ if (c & 0x80) { /* EUC 2 bytes characters */
+ if (c1 == 0) {c1 = c; continue;}
+ c |= c1 << 8;
+ c1 = 0;
+ len = 2;
+ }
+ if (c == ESC) {esc = 1; continue;}
+
+ if (esc) { /* ESC sequence */
+ if (esc == 1) {
+ esc = (c == '[') ? 2 : 0;
+ continue;
+ }
+ esc = 0;
+ if (c == 'A') c = CUR_UP;
+ else if (c == 'B') c = CUR_DWN;
+ else if (c == 'C') c = CUR_FWD;
+ else if (c == 'D') c = CUR_BWD;
+ else continue;
+ }
+ if (c == CUR_FWD) {
+ if (cp < ep) {
+ if (str[cp] & 0x80) putSIO(str[cp++]);
+ putSIO(str[cp++]);
+ }
+ continue;
+ }
+ if (c == CUR_BWD) {
+ if (cp > 0) {
+ if (str[--cp] & 0x80) {putSIO(BS); cp--;}
+ putSIO(BS);
+ }
+ continue;
+ }
+ if (c == CUR_UP || c == CUR_DWN) { /* history is recalled */
+ if (c == CUR_DWN) {
+ if (hp <= 0) continue;
+ for (hp--; (--hp) > 0 && hist[hp];);
+ if (hp) hp++;
+ } else {
+ i = hp < 0 ? 0 : (strlen(&hist[hp]) + hp + 1);
+ if (hist[i] == '\0') continue;
+ hp = i;
+ }
+ for (; cp > 0; cp--) putSIO(BS);
+ for (i = strlen(&hist[hp]); cp < i; cp++)
+ putSIO(str[cp] = hist[hp + cp]);
+ c = ERASE;
+ }
+ if (c == BS || c == DEL) {
+ if (cp <= 0) continue;
+ len = (str[cp - 1] & 0x80) ? 2 : 1;
+ if (cp < ep) memcpy(&str[cp - len], &str[cp], ep - cp);
+ for (i = 0; i < len; i++)
+ {str[--ep] = ' '; putSIO(BS);}
+ cp -= len;
+ for (i = cp; i < ep + len; i++) putSIO(str[i]);
+ for (; i > cp; i--) putSIO(BS);
+ continue;
+ }
+ if (c == CAN || c == CAN2) {
+ for (; cp > 0; cp--) putSIO(BS);
+ c = ERASE;
+ }
+ if (c == ERASE) {
+ for (i = cp; i < ep; i++) putSIO(' ');
+ for (; i > cp; i--) putSIO(BS);
+ ep = cp;
+ continue;
+ }
+
+ if (c == CR || c == LF) break;
+
+ if (c == CTLC) {
+ CTRL_C_IN++;
+ break;
+ }
+
+ if (c < ' ' && c != TAB) continue;
+
+ if (cp < ep) memmove(&str[cp + len], &str[cp], ep - cp);
+ if (len == 2) {
+ str[cp + 1] = c & 0xff;
+ c = (c >> 8) & 0xff;
+ }
+ str[cp] = c;
+ for (ep += len, i = cp; i < ep; i++) putSIO(str[i]);
+ for (cp += len; i > cp; i--) putSIO(BS);
+ }
+ putSIO(CR); /* echo back */
+ putSIO(LF);
+ str[ep] = '\0';
+ if (c == CTLC) return -1;
+
+ if (ep) { /* add to history buffer */
+ i = ep + 1;
+ memmove(&hist[i], hist, HISTBUF_SZ - i);
+ memcpy(hist, str, i);
+ hist[HISTBUF_SZ - 2] = '\0';
+ hist[HISTBUF_SZ - 1] = '\0';
+ }
+ return ep;
+}
diff --git a/tkernel_source/monitor/cmdsvc/help.h b/tkernel_source/monitor/cmdsvc/help.h
new file mode 100644
index 0000000..1af3a5d
--- /dev/null
+++ b/tkernel_source/monitor/cmdsvc/help.h
@@ -0,0 +1,50 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * help.h
+ *
+ * help message definitions
+ */
+
+/*
+ * help message definitions
+ */
+typedef struct help HELP;
+struct help {
+ void (*prfn)( const HELP* ); /* display function */
+ const UB *msg; /* message */
+};
+
+/*
+ * display help message
+ */
+IMPORT void printHelp( const HELP *help );
+
+/*
+ * help message data
+ */
+IMPORT const HELP helpALL;
+IMPORT const HELP helpD, helpDB, helpDH, helpDW;
+IMPORT const HELP helpM, helpMB, helpMH, helpMW;
+IMPORT const HELP helpF, helpFB, helpFH, helpFW;
+IMPORT const HELP helpSC, helpSCB, helpSCH, helpSCW;
+IMPORT const HELP helpCMP, helpMOV;
+IMPORT const HELP helpIB, helpIH, helpIW;
+IMPORT const HELP helpOB, helpOH, helpOW;
+IMPORT const HELP helpDA, helpR, helpB, helpBC;
+IMPORT const HELP helpG, helpS, helpN, helpBTR, helpLO;
+IMPORT const HELP helpRD, helpWD, helpID, helpBD;
+IMPORT const HELP helpKILL, helpWROM, helpFLLO;
+IMPORT const HELP helpH, helpEX;
diff --git a/tkernel_source/monitor/cmdsvc/helpmsg.c b/tkernel_source/monitor/cmdsvc/helpmsg.c
new file mode 100644
index 0000000..a71424b
--- /dev/null
+++ b/tkernel_source/monitor/cmdsvc/helpmsg.c
@@ -0,0 +1,392 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * helpmsg.c
+ *
+ * command help message
+ */
+
+#include "cmdsvc.h"
+#include "help.h"
+
+/*
+ * display help message
+ */
+EXPORT void printHelp( const HELP *help )
+{
+ (*help->prfn)(help);
+}
+
+/*
+ * display simple help message
+ */
+LOCAL void prSimpleHelp( const HELP *help )
+{
+ DSP_S(help->msg);
+}
+
+/*
+ * display help message for dump command
+ */
+LOCAL void prDumpHelp( const HELP *help )
+{
+ const UB *p1 = help->msg;
+ const UB *p2;
+
+ for (; *p1; p1++);
+ p2 = ++p1;
+ for (; *p2; p2++);
+ p2++;
+ DSP_F5(S,"Dump", S,help->msg,
+ S,"(D", S,p1, S,") [start_addr][,{end_addr|#data_cnt}] ");
+ DSP_F3(S,": Dump Memory in ", S,p2, CH,'\n');
+}
+
+/*
+ * display help message for modify command
+ */
+LOCAL void prModifyHelp( const HELP *help )
+{
+ const UB *p1 = help->msg;
+ const UB *p2;
+
+ for (; *p1; p1++);
+ p2 = ++p1;
+ for (; *p2; p2++);
+ p2++;
+ DSP_F5(S,"Modify", S,help->msg,
+ S,"(M", S,p1, S,") [start_addr][,data].. ");
+ DSP_F3(S,": Modify Memory in ", S,p2, CH,'\n');
+}
+
+/*
+ * display help message for fill command
+ */
+LOCAL void prFillHelp( const HELP *help )
+{
+ const UB *p1 = help->msg;
+ const UB *p2;
+
+ for (; *p1; p1++);
+ p2 = ++p1;
+ for (; *p2; p2++);
+ p2++;
+ DSP_F5(S,"Fill", S,help->msg,
+ S,"(F", S,p1, S,") start_addr,{end_addr|#data_cnt}[,data].. ");
+ DSP_F3(S,": Fill Memory in ", S,p2, CH,'\n');
+}
+
+/*
+ * display help message for search command
+ */
+LOCAL void prSearchHelp( const HELP *help )
+{
+ const UB *p1 = help->msg;
+ const UB *p2;
+
+ for (; *p1; p1++);
+ p2 = ++p1;
+ for (; *p2; p2++);
+ p2++;
+ DSP_F5(S,"Search", S,help->msg,
+ S,"(SC", S,p1,
+ S,") start_addr,{end_addr|#data_cnt},data[,data].. ");
+ DSP_F3(S,": Search Memory in ", S,p2, CH,'\n');
+}
+
+/*
+ * display help message for input command
+ */
+LOCAL void prInputHelp( const HELP *help )
+{
+ const UB *p = help->msg;
+
+ for (; *p; p++);
+ p++;
+ DSP_F5(S,"Input", S,help->msg, S,"(I", S,p, S,") port ");
+ DSP_F3(S,": Input ", S,help->msg, S," from I/O port\n");
+}
+
+/*
+ * display help message for output command
+ */
+LOCAL void prOutputHelp( const HELP *help )
+{
+ const UB *p = help->msg;
+
+ for (; *p; p++);
+ p++;
+ DSP_F5(S,"Output", S,help->msg, S,"(O", S,p, S,") port,data ");
+ DSP_F3(S,": Output ", S,help->msg, S," to I/O port\n");
+}
+
+/*
+ * display help message with disk name listing
+ */
+LOCAL void prDiskHelp( const HELP *help )
+{
+ const UB *devnm;
+ UW attr;
+ W i;
+
+ DSP_S(help->msg);
+ DSP_S(" device :");
+ for ( i = 0;; ++i ) {
+ devnm = ( help == &helpBD )? bootDevice(i): diskList(i, &attr);
+ if ( devnm == NULL ) break;
+
+ /* exclude devices that can not be specified */
+ if ( help == &helpWD && (attr & DA_RONLY) != 0 ) continue;
+ DSP_F2(CH,' ', S,devnm);
+ }
+ DSP_LF;
+}
+
+/*
+ * display help message for WROM command
+ */
+LOCAL void prWRomHelp( const HELP *help )
+{
+ const MEMSEG *rom, *ram;
+ UW ram_top, sz;
+
+ rom = MemArea(MSA_FROM, 1);
+ ram = MemArea(MSA_OS, 1);
+ if ( rom == NULL || ram == NULL ) {
+ DSP_S("Not Supported\n");
+ return;
+ }
+
+ ram_top = (ram->top + FROM_SECSZ - 1) & ~(FROM_SECSZ - 1);
+ sz = rom->end - rom->top;
+ if ( sz > ram->end - ram_top ) sz = ram->end - ram_top;
+
+ DSP_S(help->msg);
+ DSP_F5(S," rom_addr : 0x", 08X,rom->top,
+ S," - 0x", 08X,(rom->end-FROM_SECSZ), CH,'\n');
+ DSP_F5(S," data_ram_addr : 0x", 08X,ram_top,
+ S," - 0x", 08X,(ram->end-FROM_SECSZ), CH,'\n');
+ DSP_F5(S," block_count : 1 - ", D,(sz / FROM_SECSZ),
+ S," (1 block = ", D,(FROM_SECSZ / 1024), S,"KB)\n");
+}
+
+/* ------------------------------------------------------------------------ */
+
+EXPORT const HELP helpALL = { prSimpleHelp,
+ "--- Command List : \"? command\" for details ---\n"
+ "DumpByte/Half/Word(D/DB/DH/DW) ModifyByte/Half/Word(M/MB/MH/MW)\n"
+ "FillByte/Half/Word(F/FB/FH/FW) SearchByte/Half/Word(SC/SCB/SCH/SCW)\n"
+ "InputByte/Half/Word(IB/IH/IW) OutputByte/Half/Word(OB/OH/OW)\n"
+ "Compare(CMP) Move(MOV) Disassemble(DA) Register(R)\n"
+ "Go(G) Step(S) Next(N) BreakPoint(B) BreakClear(BC)\n"
+ "BackTrace(BTR) Kill(KILL) Load(LO)"
+ "\n"
+ "BootDisk(BD) ReadDisk(RD) WriteDisk(WD) InfoDisk(ID)\n"
+ "WriteROM(WROM) FlashLoad(FLLO) Exit(EX) Help(H/?)\n"
+};
+
+EXPORT const HELP helpD = { prDumpHelp,
+ "\0\0Byte"
+};
+
+EXPORT const HELP helpDB = { prDumpHelp,
+ "Byte\0B\0Byte"
+};
+
+EXPORT const HELP helpDH = { prDumpHelp,
+ "Half\0H\0Half"
+};
+
+EXPORT const HELP helpDW = { prDumpHelp,
+ "Word\0W\0Word"
+};
+
+EXPORT const HELP helpM = { prModifyHelp,
+ "\0\0Byte"
+};
+
+EXPORT const HELP helpMB = { prModifyHelp,
+ "Byte\0B\0Byte"
+};
+
+EXPORT const HELP helpMH = { prModifyHelp,
+ "Half\0H\0Half"
+};
+
+EXPORT const HELP helpMW = { prModifyHelp,
+ "Word\0W\0Word"
+};
+
+EXPORT const HELP helpF = { prFillHelp,
+ "\0\0Byte"
+};
+
+EXPORT const HELP helpFB = { prFillHelp,
+ "Byte\0B\0Byte"
+};
+
+EXPORT const HELP helpFH = { prFillHelp,
+ "Half\0H\0Half"
+};
+
+EXPORT const HELP helpFW = { prFillHelp,
+ "Word\0W\0Word"
+};
+
+EXPORT const HELP helpSC = { prSearchHelp,
+ "\0\0Byte"
+};
+
+EXPORT const HELP helpSCB = { prSearchHelp,
+ "Byte\0B\0Byte"
+};
+
+EXPORT const HELP helpSCH = { prSearchHelp,
+ "Half\0H\0Half"
+};
+
+EXPORT const HELP helpSCW = { prSearchHelp,
+ "Word\0W\0Word"
+};
+
+EXPORT const HELP helpCMP = { prSimpleHelp,
+ "Compare(CMP) start_addr,{end_addr|#byte_cnt},compare_addr : "
+ "Compare Memory\n"
+};
+
+EXPORT const HELP helpMOV = { prSimpleHelp,
+ "Move(MOV) start_addr,{end_addr|#byte_cnt},dest_addr : Move Memory\n"
+};
+
+EXPORT const HELP helpIB = { prInputHelp,
+ "Byte\0B"
+};
+
+EXPORT const HELP helpIH = { prInputHelp,
+ "Half\0H"
+};
+
+EXPORT const HELP helpIW = { prInputHelp,
+ "Word\0W"
+};
+
+EXPORT const HELP helpOB = { prOutputHelp,
+ "Byte\0B"
+};
+
+EXPORT const HELP helpOH = { prOutputHelp,
+ "Half\0H"
+};
+
+EXPORT const HELP helpOW = { prOutputHelp,
+ "Word\0W"
+};
+
+EXPORT const HELP helpDA = { prSimpleHelp,
+ "Disassemble(DA) [start_addr][,step_cnt] : Disassemble\n"
+ " Not Supported\n"
+};
+
+EXPORT const HELP helpR = { prSimpleHelp,
+ "Register(R) [register_name[,data]] : Register Dump / Modify\n"
+};
+
+EXPORT const HELP helpG = { prSimpleHelp,
+ "Go(G) [start_addr][,break_addr] : Go Program\n"
+};
+
+EXPORT const HELP helpB = { prSimpleHelp,
+ "BreakPoint(B) [break_addr[,break_attr][,\"command\"]] : Set Break Point\n"
+ " break_attr : S\n"
+};
+
+EXPORT const HELP helpBC = { prSimpleHelp,
+ "BreakClear(BC) [break_addr][,break_addr].. : Clear Break Point\n"
+};
+
+EXPORT const HELP helpS = { prSimpleHelp,
+ "Step(S) [start_addr][,step_cnt] : Step Trace Program\n"
+};
+
+EXPORT const HELP helpN = { prSimpleHelp,
+ "Next(N) [start_addr][,step_cnt] : Next Trace Program\n"
+};
+
+EXPORT const HELP helpBTR = { prSimpleHelp,
+ "BackTrace(BTR) [frame_pointer] : Display Backtrace\n"
+ " Not Supported\n"
+};
+
+EXPORT const HELP helpLO = { prSimpleHelp,
+ "Load(LO) {S|XS|XM} [,load addr] : Load Program / Data\n"
+ " S : Load s-format data (no protocol)\n"
+ " XM : Load memory image (XMODEM protocol)\n"
+ " XS : Load s-format data (XMODEM protocol)\n"
+};
+
+EXPORT const HELP helpRD = { prDiskHelp,
+ "ReadDisk(RD) device, start_block, nblocks, mem_addr : Read Disk Blocks\n"
+};
+
+EXPORT const HELP helpWD = { prDiskHelp,
+ "WriteDisk(WD) device, start_block, nblocks, mem_addr : Write Disk Blocks\n"
+};
+
+EXPORT const HELP helpID = { prDiskHelp,
+ "InfoDisk(ID) device : Display Disk Information\n"
+};
+
+EXPORT const HELP helpBD = { prDiskHelp,
+ "BootDisk(BD) [device] : Boot from Disk\n"
+};
+
+EXPORT const HELP helpKILL = { prSimpleHelp,
+ "Kill : Kill Process and Continue\n"
+};
+
+EXPORT const HELP helpH = { prSimpleHelp,
+ "Help(H/?) [command_name] : Help Message\n"
+};
+
+EXPORT const HELP helpEX = { prSimpleHelp,
+ "Exit(EX) [0] : System Power Off\n"
+ "Exit(EX) -1 : System Reset (Restart)\n"
+};
+
+EXPORT const HELP helpWROM = { prWRomHelp,
+ "WriteROM(WROM) rom_addr, data_ram_addr, block_count : "
+ "Write Flash ROM blocks\n"
+};
+
+EXPORT const HELP helpFLLO = { prSimpleHelp,
+ "FlashLoad(FLLO) [attr] : Load S-Format Data & Write Flash ROM\n"
+ " attr: X Use XMODEM protocol\n"
+ " E Fill write blocks with 0xFF\n"
+ " Default : Overwrite original Flash ROM Image\n"
+};
+
+/* ======================================================================== */
+
+/*
+ * display boot message
+ */
+EXPORT void dispTitle( void )
+{
+ int i;
+
+ DSP_S("\n\n");
+ for ( i = 0; Title[i] != NULL; i++ ) DSP_S(Title[i]);
+ DSP_S("\n\n");
+}
diff --git a/tkernel_source/monitor/cmdsvc/load.c b/tkernel_source/monitor/cmdsvc/load.c
new file mode 100644
index 0000000..292a47c
--- /dev/null
+++ b/tkernel_source/monitor/cmdsvc/load.c
@@ -0,0 +1,329 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * load.c
+ *
+ * load processing
+ */
+
+#include "cmdsvc.h"
+
+LOCAL UW s_addr; /* start address */
+LOCAL UW e_addr; /* end address + 1 */
+LOCAL UW offset; /* address offset */
+LOCAL UW loaddr; /* address lower limit */
+LOCAL UW hiaddr; /* address upper limit */
+LOCAL W blkno; /* block number */
+LOCAL W blkptr; /* read pointer */
+#define XBLK_SZ 1024 /* XMODEM block size (extended) */
+#define BLK_SZ 128 /* XMODEM block size */
+#define blkbuf wrkBuf /* block buffer */
+LOCAL W blksz; /* block size */
+
+LOCAL FUNCP readFn; /* read function */
+
+#define inputByte(tmo) getSIO(tmo) /* input one byte */
+#define outputByte(c) putSIO(c) /* output one byte */
+
+/* XMODEM control codes */
+#define SOH (0x01)
+#define STX (0x02)
+#define EOT (0x04)
+#define ACK (0x06)
+#define NAK (0x15)
+#define CAN (0x18)
+#define CTLC ('C' - '@')
+#define CTLZ ('Z' - '@')
+
+/* XMODEM time out specification
+ * wait for SOH : 10 seconds / 10 retries
+ * timeout between two characters : 1 seconds
+ *
+ * how to cope with communication software (mainly for TeraTerm) that does not start automatic transfer
+ * (this falls outside XMODEM specification)
+ * Since the timeout value for SOH is 10 seconds, the initial transfer always seem to wait for 10 seconds.
+ * The initial timeout for SOH is set to 3 seconds (only for the very first transfer.)
+ */
+#define IDLE_TMO ( 1 * 1000) /* idle wait(milliseconds) */
+#define RECV_TMO ( 1 * 1000) /* timeout for data input (milliseconds) */
+#define SOH_TMO (10 * 1000) /* timeout for SOH input (milliseconds) */
+#define SOH1_TMO ( 3 * 1000) /* timeout for the initial SOH input (milliseconds) */
+#define MAX_RETRY 10 /* maximum number of retries */
+
+/*
+ skip until there is no more input
+*/
+LOCAL void purgeInput(void)
+{
+ while (inputByte(IDLE_TMO) >= 0);
+}
+/*
+ asynchronous read processing (without any protocol)
+*/
+LOCAL W textRead(void)
+{
+ W c;
+
+ while ((c = inputByte(0)) < 0);
+ return (c == CTLC || c == CAN) ? E_CANCEL : c;
+}
+/*
+ XMODEM read processing
+*/
+LOCAL W xmodemRead(void)
+{
+ W i, c, ctlch;
+ UB cksum;
+
+ if (blkptr < blksz) return blkbuf[blkptr++];
+
+ c = 0;
+ ctlch = ACK;
+ if (blkno++ == 0) {
+ /* only for the initial packet transfer */
+ outputByte(NAK);
+ c = inputByte(SOH1_TMO);
+ ctlch = -1;
+ }
+
+ for (;;) {
+ /* receiving block */
+ for (i = 0;;) {
+ if (ctlch >= 0) {
+ /* ack/beginning character is transmitted */
+ outputByte(ctlch);
+
+ /* leading letter in the ack is extracted */
+ c = inputByte(SOH_TMO);
+ }
+ ctlch = NAK;
+ if (c == SOH) {blksz = BLK_SZ; break;}
+ if (c == STX) {blksz = XBLK_SZ; break;}
+ if (c == CAN || c == CTLC) { /* cancel transfer */
+ /* Is CAN followed by another CAN? */
+ c = inputByte(IDLE_TMO);
+ if (c < 0 || c == CAN || c == CTLC)
+ return E_CANCEL;
+ } else if (c == EOT) { /* end of transmission */
+ outputByte(ACK);
+ return E_END;
+ }
+ purgeInput(); /* skip data */
+ if (++i >= MAX_RETRY) return E_XMODEM;
+ }
+
+ /* read a block number & check */
+ if ((i = inputByte(RECV_TMO)) < 0) continue;
+ if ((c = inputByte(RECV_TMO)) < 0) continue;
+ if (i + c != 0xff) continue;
+
+ if (i != (blkno & 0xff)) {
+ if (i != ((blkno - 1) & 0xff)) return E_XMODEM;
+ /* skip if the previous block is read */
+ ctlch = ACK;
+ }
+
+ /* read the block itself */
+ for (cksum = 0, i = 0; i < blksz; i++) {
+ if ((c = inputByte(RECV_TMO)) < 0) break;
+ cksum += (blkbuf[i] = c);
+ }
+ if (c < 0) continue;
+
+ /* validate checksum */
+ if (inputByte(RECV_TMO) == cksum && ctlch != ACK) break;
+ }
+ blkptr = 0;
+ return blkbuf[blkptr++];
+}
+/*
+ XMODEM termination processing
+*/
+LOCAL void xmodemEnd(W er)
+{
+ /* finish XMODEM protocol */
+ while (er >= 0) er = xmodemRead();
+
+ if (er != E_END && er != E_CANCEL) {
+ purgeInput(); /* wait until there is no more data */
+ outputByte(CAN); /* transmite two (or more) consecutive CANs */
+ outputByte(CAN);
+ outputByte(CAN);
+ }
+}
+/*
+ load memory image
+*/
+LOCAL W loadImage(void)
+{
+ W i, c;
+ UB buf[512];
+
+ for (i = 0;;) {
+ if ((c = (*readFn)()) >= 0) buf[i++] = c;
+ if (i < sizeof(buf) && c >= 0) continue;
+ if (i > 0) {
+ if (e_addr < loaddr ||
+ e_addr - 1 > hiaddr - i) return E_RANGE;
+ if (writeMem(e_addr, buf, i, 1) != i) return E_MACV;
+ e_addr += i;
+ i = 0;
+ }
+ if (c < 0) return c;
+ }
+}
+/*
+ read a hexadecimal character
+*/
+LOCAL W readHex(void)
+{
+ W c;
+
+ if ((c = (*readFn)()) < 0) return c;
+ if (c >= '0' && c <= '9') return c - '0';
+ if (c >= 'A' && c <= 'F') return c - 'A' + 10;
+ if (c >= 'a' && c <= 'f') return c - 'a' + 10;
+ return E_LOAD;
+}
+/*
+ load S format data
+*/
+LOCAL W loadSform(void)
+{
+ W i, c, bcnt, v, v1, dcnt, rtype;
+ UW addr, a_addr;
+ UB cksum, buf[512];
+
+ a_addr = s_addr; /* real address */
+ s_addr = 0xffffffff; /* highest load address */
+ e_addr = 0; /* lowest load address */
+
+ for (;;) {
+ if ((c = (*readFn)()) < 0) return c;
+
+ if (c != 'S') {
+ if (c == CTLZ) break; /* end */
+ continue;
+ }
+
+ if ((c = (*readFn)()) < 0) return c;
+ switch(c) {
+ case '0': /* header */
+ rtype = 0; break;
+ case '1': /* 2 byte address data */
+ case '2': /* 3 byte address data */
+ case '3': /* 4 byte address data */
+ rtype = c - '0' + 2; break;
+ case '7': /* 4 byte address termination */
+ case '8': /* 3 byte address termination */
+ case '9': /* 2 byte address termination */
+ rtype = -1; break;
+ default: return E_LOADFMT;
+ }
+
+ for (cksum = bcnt = addr = dcnt = i = 0;; i++) {
+ if ((v1 = readHex()) < 0) return v1;
+ if ((v = readHex()) < 0) return v;
+ cksum += (v += (v1 << 4));
+
+ if (i == 0) { /* byte counts */
+ if ((bcnt = v - 1) < 0) return E_LOAD;
+ addr = 0;
+ continue;
+ }
+ if (i > bcnt) { /* checksum */
+ if (cksum != 0xff) return E_LOAD;
+ break;
+ }
+ if (rtype <= 0) continue;
+
+ if (i < rtype) { /* load address */
+ addr = (addr << 8) + v;
+ } else { /* data */
+ buf[dcnt++] = (UB)v;
+ }
+ }
+ if (dcnt > 0) {
+ /* if we have address specification, then the first address */
+ /* to be used as the designated address after suitable adjustment. */
+ if (a_addr != 0) {
+ offset = a_addr - addr;
+ a_addr = 0;
+ }
+ addr += offset;
+ if (addr < loaddr || addr - 1 > hiaddr - dcnt)
+ return E_RANGE;
+ if (writeMem(addr, buf, dcnt, 1) != dcnt)
+ return E_MACV;
+ if (addr < s_addr) s_addr = addr;
+ if ((addr += dcnt) > e_addr) e_addr = addr;
+ }
+ if (rtype < 0) break; /* end */
+ }
+ return E_OK;
+}
+/*
+ loading processing
+*/
+EXPORT ER doLoading(W proto, UW addr, UW *range)
+{
+ ER er;
+
+ e_addr = s_addr = addr; /* load address */
+
+ if (range) { /* range specification */
+ loaddr = range[0]; /* address lower limit */
+ hiaddr = range[1]; /* address upper limit */
+ offset = range[2]; /* address offset */
+ } else {
+ loaddr = 0; /* address lower limit */
+ hiaddr = 0xFFFFFFFF; /* address upper limit */
+ offset = 0; /* address offset */
+ }
+
+ if (proto & P_XMODEM) { /* XMODEM */
+ readFn = (FUNCP)xmodemRead;
+ blkptr = blkno = blksz = 0;
+ } else { /* no protocol */
+ readFn = (FUNCP)textRead;
+ }
+
+ if (proto & P_SFORM) { /* S format */
+ er = loadSform();
+ if (er == E_END) er = E_LOAD;
+ } else { /* memory image */
+ er = loadImage();
+ }
+
+ /* read termination processing */
+ if (proto & P_XMODEM) xmodemEnd(er);
+
+ /* wait until there is no more data */
+ purgeInput();
+
+ if (er == E_END) er = E_OK;
+ DSP_LF;
+ if (er == E_OK) {
+ e_addr--;
+ if (range) {
+ range[0] = s_addr; /* load address */
+ range[1] = e_addr;
+ s_addr -= offset;
+ e_addr -= offset;
+ }
+ DSP_F5(S,"Loaded: ", 08X,s_addr, S," -> ", 08X,e_addr, CH,'\n');
+ }
+ return er;
+}
diff --git a/tkernel_source/monitor/cmdsvc/memory.c b/tkernel_source/monitor/cmdsvc/memory.c
new file mode 100644
index 0000000..f95a8bf
--- /dev/null
+++ b/tkernel_source/monitor/cmdsvc/memory.c
@@ -0,0 +1,170 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * memory.c
+ *
+ * memory & I/O access processing
+ */
+
+#include "cmdsvc.h"
+
+/* multi-type memory pointer */
+typedef union {
+ UW a;
+ UW *w;
+ UH *h;
+ UB *b;
+} MP;
+
+/*
+ read memory
+*/
+EXPORT W readMem(UW addr, void *buf, W len, W unit)
+{
+ W i, n, alen;
+ MP pa, bp;
+
+ /* address misalignment is reported as error */
+ if (addr & (unit - 1)) return 0;
+
+ bp.w = buf;
+ for (alen = 0; alen < len; alen += i) {
+
+ /* memory address check & conversion to physical address */
+ n = chkMemAddr(addr + alen, &pa.a, len - alen, 0);
+ if (n < unit) break; /* illegal address */
+
+ i = 0;
+ switch(unit) {
+ case 4:
+ for (; i < n; i += 4) *bp.w++ = rd_w(pa.w++);
+ break;
+ case 2:
+ for (; i < n; i += 2) *bp.h++ = rd_h(pa.h++);
+ break;
+ default:
+ for (; i < n; i++) *bp.b++ = rd_b(pa.b++);
+ }
+ }
+ return alen;
+}
+/*
+ write memory
+ unit & 0x10 : fill
+*/
+EXPORT W writeMem(UW addr, void *buf, W len, W unit)
+{
+ W i, n, sz, alen;
+ MP pa, bp;
+
+ /* address misalignment is reported as error */
+ sz = unit & 0x0f;
+ if (addr & (sz - 1)) return 0;
+
+ bp.w = buf;
+ for (alen = 0; alen < len; alen += i) {
+
+ /* memory address check & conversion to physical address */
+ n = chkMemAddr(addr + alen, &pa.a, len - alen, 1);
+ if (n < sz) break; /* illegal address */
+
+ i = 0;
+ switch(sz) {
+ case 4:
+ if (unit & 0x10) {
+ for (; i < n; i += 4) wr_w(pa.w++, *bp.w);
+ } else {
+ for (; i < n; i += 4) wr_w(pa.w++, *bp.w++);
+ }
+ break;
+ case 2:
+ if (unit & 0x10) {
+ for (; i < n; i += 2) wr_h(pa.h++, *bp.h);
+ } else {
+ for (; i < n; i += 2) wr_h(pa.h++, *bp.h++);
+ }
+ break;
+ default:
+ if (unit & 0x10) {
+ for (; i < n; i++) wr_b(pa.b++, *bp.b);
+ } else {
+ for (; i < n; i++) wr_b(pa.b++, *bp.b++);
+ }
+ }
+ }
+ return alen;
+}
+/*
+ read character string
+*/
+EXPORT W readMemStr(UW addr, void *buf, W len)
+{
+ W i, n, alen;
+ UW pa;
+
+ for (alen = 0; alen < len; alen += i) {
+ /* memory address check & conversion to physical address */
+ n = chkMemAddr(addr + alen, &pa, len - alen, 0);
+ if (n == 0) break; /* illegal address */
+ for (i = 0; i < n; i++, buf++, pa++) {
+ if ((*(UB*)buf = rd_b((UB*)pa)) == 0) return alen + i;
+ }
+ }
+ return -1;
+}
+/*
+ I/O read
+*/
+EXPORT W readIO(UW addr, UW *data, W unit)
+{
+ W n;
+ UW pa;
+
+ /* address misalignment is reported as error */
+ if (addr & (unit - 1)) return 0;
+
+ /* I/O address check & conversion to physical address */
+ n = chkIOAddr(addr, &pa, unit);
+ if (n < unit) return 0;
+
+ switch(unit) {
+ case 4: *data = in_w(pa); break;
+ case 2: *data = in_h(pa); break;
+ default: *data = in_b(pa);
+ }
+ return unit;
+}
+/*
+ I/O write
+*/
+EXPORT W writeIO(UW addr, UW data, W unit)
+{
+ W n;
+ UW pa;
+
+ /* address misalignment is reported as error */
+ if (addr & (unit - 1)) return 0;
+
+ /* I/O address check & conversion to physical address */
+ n = chkIOAddr(addr, &pa, unit);
+ if (n < unit) return 0;
+
+ switch(unit) {
+ case 4: out_w(pa, data); break;
+ case 2: out_h(pa, data); break;
+ default: out_b(pa, data);
+ }
+ return unit;
+}
diff --git a/tkernel_source/monitor/cmdsvc/src/armv6/break.c b/tkernel_source/monitor/cmdsvc/src/armv6/break.c
deleted file mode 100644
index fc1bed7..0000000
--- a/tkernel_source/monitor/cmdsvc/src/armv6/break.c
+++ /dev/null
@@ -1,560 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * break.c
- *
- * break/trace processing (after ARMv6)
- */
-
-#include "../cmdsvc.h"
-#include <sys/sysinfo.h>
-
-/* SW breakpoint code (BKPT instruction) */
-#define BREAK_ARM 0xE1200070
-#define BREAK_THUMB 0xBE000000
-
-/*
- breakpoint data
-*/
-typedef struct {
- UW addr; /* break address */
- UW code; /* saved data */
- UW atr; /* break attribute */
- H sz; /* code size (2 or 4) */
- UB cmd[L_BPCMD]; /* executed command */
-} BRKPT;
-
-#define MAX_SBP (8) /* maximum number of SW breakpoint */
-#define MAX_IBP (0)
-#define MAX_OBP (0)
-#define MAX_BRKPT (MAX_SBP + MAX_IBP + MAX_OBP)
-
-LOCAL BRKPT brkPt[MAX_BRKPT + 1]; /* breakpoint data */
- /* the last is temorary break */
-
-/*
- step point data
- * used for trace and temporary step processing
-*/
-typedef struct {
- UW addr; /* step address */
- UW code; /* step save data */
- UW pc; /* address of replaced instruction */
- UW inst; /* replaced instruction */
- UW regval; /* replaced register value */
- H reg; /* replaced register number */
- H sz; /* code size ( 2 / 4) */
-} STEPPT;
-
-LOCAL STEPPT stepPt; /* step point data */
-
-/*
- break attribute
-*/
-#define BA_S 0x1000 /* software break */
-#define BA_I 0x2000 /* instruction break */
-#define BA_O 0x4000 /* operand break */
-#define BA_SET 0x8000 /* software break released flag */
-#define BA_PRE 0x0100 /* break before execution */
-#define BA_R 0x0200 /* break on read */
-#define BA_W 0x0400 /* break on write */
-#define BA_RW 0x0600 /* break on read/write */
-#define BA_TMP 0x0800 /* temporary break */
-
-#define MAX_BPATR 1
-
-LOCAL const struct {
- UB name[4]; /* attribute name */
- UW atr; /* attribute code */
-} brkAtr[MAX_BPATR] = {
- {"S ", 0x00000000 | BA_S | BA_PRE}, /* software break */
-};
-
-/*
- trace data
-*/
-LOCAL W traceMode; /* trace mode */
-LOCAL W traceStep; /* number of trace steps */
-LOCAL W stepFlg; /* temporary step execution flag */
-LOCAL union {
- UB b[8];
- UW w[2]; /* to align on word boundary */
- } sbpCode; /* SW break instructions (two) */
-
-/*
- CP14 register manipulation
-*/
-/* no debug comprocessor */
-LOCAL void setDSCR(UW val) {return;}
-LOCAL UW getDSCR(void) {return 0;}
-LOCAL UW getWFAR(void) {return 0;}
-LOCAL void setBVR(W num, UW val) {return;}
-LOCAL void setBCR(W num, UW val) {return;}
-LOCAL UW getBCR(W num) {return 0;}
-LOCAL void setWVR(W num, UW val) {return;}
-LOCAL void setWCR(W num, UW val) {return;}
-LOCAL UW getWCR(W num) {return 0;}
-
-/*
- check CP14 monitor debug mode
-*/
-LOCAL UW CheckCP14(void)
-{
- return getDSCR() & 0x00008000;
-}
-/*
- set CP14 monitor debug mode
-*/
-LOCAL UW EnableCP14(void)
-{
- UW dscr;
-
- dscr = getDSCR();
- dscr |= 0x00008000; /* monitor debug mode on */
- dscr &= ~0x00004000; /* hold debug mode off */
- setDSCR(dscr);
-
- /* return the success/failure of setting */
- return CheckCP14();
-}
-/*
- reset CP14 monitor debug mode
-*/
-LOCAL void DisableCP14(void)
-{
- setDSCR(getDSCR() & ~0x00008000);
- return;
-}
-/*
- extract break attribute
-*/
-EXPORT W getBreakAtr(UB *name)
-{
- W i;
-
- if (name[4] == ' ') {
- for (i = 0; i < MAX_BPATR; i++) {
- if (memcmp(brkAtr[i].name, name, sizeof(UW)) == 0)
- return brkAtr[i].atr;
- }
- }
- return E_BPATR;
-}
-/*
- extract break attribute string (fixed length: 4 characters)
-*/
-LOCAL UB *strBreakAtr(W atr)
-{
- W i;
-static UB str[5];
-
- atr &= ~BA_SET;
-
- for (i = 0; i < MAX_BPATR; i++) {
- if (brkAtr[i].atr == atr) {
- memcpy(str, brkAtr[i].name, 4);
- for (i = 4; str[--i] == ' '; );
- str[i + 1] = '\0';
- return str;
- }
- }
- return NULL;
-}
-/*
- set breakpoint
-*/
-EXPORT ER setBreak(UW addr, W atr, UB *cmd, W cmdlen)
-{
- W ibcnt, obcnt, sbcnt, sz;
- UW code;
- BRKPT *bp, *p;
-
- if (atr == 0) atr = BA_S | BA_PRE; /* default attribute */
-
- /* unaligned address (non-W alignment) is regarded as Thumb instruction */
- sz = (addr & 0x03) ? 2 : 4;
- addr &= ~(sz - 1);
-
- if (atr & BA_TMP) { /* temporary break is used at fixed location */
- bp = &brkPt[MAX_BRKPT];
- } else {
- /* find an empty slot in the table */
- ibcnt = obcnt = sbcnt = 0;
- for (bp = NULL, p = brkPt; p < &brkPt[MAX_BRKPT]; p++) {
- if (p->addr == 0) {if (bp == NULL) bp = p;} /* empty */
- else if (p->addr == addr) bp = p; /* update */
- else if (p->atr & BA_O) obcnt++; /* WP */
- else if (p->atr & BA_I) ibcnt++; /* HW BP */
- else sbcnt++; /* SW BP */
- }
- /* check for the maximum value */
- if (atr & BA_O) {
- if (obcnt >= MAX_OBP) return E_HBPOVR;
- } else if (atr & BA_I) {
- if (ibcnt >= MAX_IBP) return E_HBPOVR;
- } else {
- if (sbcnt >= MAX_SBP) return E_SBPOVR;
- }
- }
-
- if (atr & BA_S) {
- /* validate PC */
- /* if (invalidPC(addr)) return E_BPBAD; */
-
- /*check for read and and write access rights */
- if (readMem(addr, &code, sz, 2) != sz) return E_BPBAD;
- if (writeMem(addr, &sbpCode.b[sz], sz, 2) != sz) return E_BPROM;
- writeMem(addr, &code, sz, 2);
- } else {
- code = 0;
- }
-
- /*set breakpoint */
- bp->addr = addr;
- bp->atr = atr | BA_SET;
- bp->sz = sz;
- bp->code = code;
- memset(bp->cmd, 0, L_BPCMD);
- if (cmdlen > 0) memcpy(bp->cmd, cmd, cmdlen);
- return E_OK;
-}
-/*
- clear breakpoint
-*/
-EXPORT ER clearBreak(UW addr)
-{
- BRKPT *p;
-
- if (addr == 0) { /* clear all breakpoints */
- memset(&brkPt[0], 0, sizeof(brkPt));
- return E_OK;
- }
- for (p = brkPt; p < &brkPt[MAX_BRKPT]; p++) {
- if (p->addr && p->addr == (addr & ~(p->sz - 1))) {
- memset(p, 0, sizeof(BRKPT));
- return E_OK;
- }
- }
- return E_BPUDF;
-}
-/*
- list all breakpoints
-*/
-EXPORT void dspBreak(void)
-{
- BRKPT *p;
-
- for (p = brkPt; p < &brkPt[MAX_BRKPT]; p++) {
- if (p->addr == 0) continue;
- /* THUMB(sz == 2) is displayed using odd address */
- DSP_F3(08X,(p->addr + ((p->sz & 2) >> 1)), CH,' ',
- S,strBreakAtr(p->atr));
- if (p->cmd[0] != '\0') {
- DSP_F3(S," \"", S,p->cmd, CH,'"');
- }
- DSP_LF;
- }
-}
-/*
- initialize breakpoint
-*/
-EXPORT void initBreak(void)
-{
- /* clear all breakpoints */
- memset(&brkPt[0], 0, sizeof(brkPt));
-
- /* clear all step points */
- memset(&stepPt, 0, sizeof(stepPt));
-
- /* initialize others, */
- traceMode = traceStep = stepFlg = 0;
-
- /* SW break instruction (undefined instruction) */
- sbpCode.w[0] = BREAK_THUMB;
- sbpCode.w[1] = BREAK_ARM;
-}
-/*
- release breakpoint temporarily (monitor entry)
-*/
-EXPORT W resetBreak(UW vec)
-{
- W i, n, bpflg;
- UW code, pc;
- BRKPT *p;
-
- pc = getCurPCX(); /* break address has been adjusted */
- bpflg = 0;
-
- /* release if monitor debug mode is used */
- if (CheckCP14()) {
- /* release hardware breakpoint */
- for (i = 0; i < MAX_IBP; i++) {
- setBCR(i, getBCR(i) & ~1);
- }
-
- /* release watchpoint */
- for (i = 0; i < MAX_OBP; i++) {
- setWCR(i, getWCR(i) & ~1);
- }
-
- /* monitor debug mode is set to off later */
- }
-
- /* release steppoints */
- if (stepPt.addr != 0) {
- n = stepPt.sz;
- readMem(stepPt.addr, &code, n, 2);
- if (memcmp(&code, &sbpCode.b[n], n) == 0) {
- if (pc == stepPt.addr) bpflg = 0x100;
- writeMem(stepPt.addr, &stepPt.code, n, 2);
- if (stepPt.pc > 0) {
- /* restore the changed instruction (ARM instruction only) */
- writeMem(stepPt.pc, &stepPt.inst, 4, 2);
- /* restore the changed register */
- pc = getRegister(stepPt.reg);
- setRegister(stepPt.reg, stepPt.regval);
- }
- /* set the NEXT real PC */
- if (bpflg != 0) setCurPCX(pc);
- }
- }
-
- /* in the case of trace/step execution, SW breakpoints have been released */
- if (! (traceMode || stepFlg)) {
-
- /* temporaly release SW/HW breakpoints (including the temporary breakpoints) */
- for (p = brkPt; p <= &brkPt[MAX_BRKPT]; p++) {
- if (p->addr == 0) continue;
-
- if (p->atr & BA_O) {
- if (vec == EIT_DDEBUG)
- bpflg = (p - brkPt) | 0x10;
- } else if (p->atr & BA_I) {
- if (pc == p->addr)
- bpflg = (p - brkPt) | 0x10;
- } else {
- readMem(p->addr, &code, n = p->sz, 2);
- if (memcmp(&code, &sbpCode.b[n], n) == 0) {
- if (pc == p->addr)
- bpflg = (p - brkPt) | 0x10;
- writeMem(p->addr, &p->code, n, 2);
- p->atr |= BA_SET;
- } else {
- p->atr &= ~BA_SET;
- }
- /* clear temporary breakpoint */
- if (p->atr & BA_TMP)
- memset(p, 0, sizeof(BRKPT));
- }
- }
- }
- return bpflg; /* is PC breakpoint? */
-}
-/*
- setting step
-*/
-LOCAL void setStep(UW pc, W mode)
-{
- W n;
- UW cpsr, inst;
-
- /* ARM or THUMB */
- cpsr = getCurCPSR();
-
- /* decode instruction and obtain the next branch target */
- n = getStepAddr(pc, cpsr, (mode == 2) ? 1 : 0, &stepPt.addr, &inst);
-
- if (n >= 0x10) { /* instruction modification */
- /* modify instruction (ARM instruction only) */
- readMem(stepPt.pc = pc, &stepPt.inst, 4, 2);
- writeMem(pc, &inst, 4, 2);
- /* restore the changed register */
- stepPt.reg = (n >> 4) & 0x0F;
- stepPt.regval = getRegister(stepPt.reg);
- /* Set PC witht the content of the replace register */
- setRegister(stepPt.reg, pc + ((cpsr & PSR_T) ? 4 : 8));
- }
- /*set break command */
- stepPt.sz = (n &= 0x0F);
- readMem(stepPt.addr, &stepPt.code, n, 2);
- writeMem(stepPt.addr, &sbpCode.b[n], n, 2);
-}
-/*
- set breakpoint (monitor exit)
-*/
-EXPORT void setupBreak(void)
-{
- W ibcnt, obcnt;
- UW bcr, wcr, pc;
- BRKPT *p;
-
- pc = getCurPCX();
-
- /* clear steppoint */
- memset(&stepPt, 0, sizeof(stepPt));
-
- if (traceMode) { /* trace is executed */
-
- setStep(pc, traceMode); /* set up step */
-
- } else { /* normal execution */
-
- /* if an unexecuted break matches the PC value */
- /* temporarily set up step execution, and execute one instruction only */
- if (stepFlg == 0) {
- for (p = brkPt; p <= &brkPt[MAX_BRKPT]; p++) {
- if (p->addr == pc && (p->atr & BA_PRE)) {
- setStep(pc, 0); /* set up temporary step execution */
- stepFlg = 1;
- return;
- }
- }
- }
-
- ibcnt = obcnt = 0;
-
- /*set breakpoint */
- /* - unless we turn on monitor debug mode, WCR/WVR/BCR/BVR */
- /* cannot be accessed */
- /* - depending on hardware, monitor debug mode cannot be */
- /* set to on */
- /* So try setting monitor debug mode on, and only if it is successful, */
- /* we try to set WCR/WVR/BCR/BVR */
- for (p = brkPt; p <= &brkPt[MAX_BRKPT]; p++) {
- if (p->addr == 0) continue;
-
- if (p->atr & BA_O) {
- if (!EnableCP14()) continue;
- wcr = getWCR(obcnt);
- wcr &= ~0x001FC1FF;
- wcr |= ((p->atr & (BA_RW)) >> 9) << 3;
- switch (p->atr >> 24) { /* LE only */
- case 2: wcr |= 0x060 << (p->addr & 2); break;
- case 4: wcr |= 0x1e0; break;
- default: /* do nothing */ break;
- }
- setWVR(obcnt, p->addr & ~3);
- setWCR(obcnt, wcr | 7);
- obcnt++;
- } else if (p->atr & BA_I) {
- if (!EnableCP14()) continue;
- bcr = getBCR(ibcnt);
- bcr &= ~0x007FC1E7;
- bcr |= (p->addr & 2) ? 0x180 : 0x060; /* LE */
- setBVR(ibcnt, p->addr & ~3);
- setBCR(ibcnt, bcr | 7);
- ibcnt++;
- } else if (p->atr & BA_SET) {
- readMem(p->addr, &p->code, p->sz, 2);
- writeMem(p->addr, &sbpCode.b[p->sz], p->sz, 2);
- }
- }
-
- /* if hardware breakpoint is not used at all */
- /* monitor debug mode is turned off */
- if (ibcnt == 0 && obcnt == 0) DisableCP14();
- }
- stepFlg = 0; /* clear temporary step execution flag */
-}
-/*
- stop tracing
-*/
-EXPORT void stopTrace(void)
-{
- traceMode = traceStep = 0;
-}
-/*
- process program execution
-*/
-EXPORT ER goTrace(W trace, UW pc, UW par)
-{
- W er;
-
- /* set trace mode */
- if ((traceMode = trace) == 0) { /* normal execution */
- /* set temporary breakpoint */
- if (par != 0) {
- er = setBreak(par, BA_S | BA_PRE | BA_TMP, NULL, 0);
- if (er < E_OK) return er;
- }
- } else { /* trace execution */
- traceStep = par;
- }
- setCurPC(pc); /* set execution start address */
- return E_OK;
-}
-/*
- prcess break exception
-
- return 0: continue, 1: command execution (cmd : initial command line)
-*/
-EXPORT W procBreak(W bpflg, UB **cmd)
-{
- B *mes;
- BRKPT *bp;
- UW pc, npc, wfar;
-
- bp = NULL;
-
- if (traceMode) { /* trace execution */
- /*PC holds the next PC value (by resetBreak()) */
- pc = getCurPC();
-
- /* disassembly display (next instruction) */
- disAssemble(&pc, &npc, wrkBuf);
- DSP_F4(08X,pc, S,": ", S,wrkBuf, CH,'\n');
-
- if (-- traceStep > 0) return 0; /* continue */
- stopTrace(); /* stop tracing */
-
- } else { /* breakpoint */
- /* During temporary step execution, then do nothing and continue */
- if (stepFlg) return 0;
-
- pc = getCurPCX(); /* break address has been adjusted */
-
- /* this is not a breakpoint set by b command */
- if ((bpflg & 0xF0) == 0) {
- DSP_F3(S,"Unknown break at H'", 08X,pc, CH,'\n');
- *cmd = NULL;
- return 1;
- }
-
- bp = &brkPt[bpflg & 0xF];
- switch (bp->atr & (BA_S | BA_I | BA_O | BA_R | BA_W)) {
- case BA_S: mes = "S"; break;
- case BA_I: mes = "E"; break;
- case BA_O|BA_R: mes = "R"; break;
- case BA_O|BA_W: mes = "W"; break;
- case BA_O|BA_R|BA_W: mes = "RW"; break;
- default: mes = "?"; break;
- }
-
- if ((bp->atr & BA_O) && CheckCP14()) {
- /* the address of instruction that generated operand break */
- /* is fetched from WFAR */
- wfar = getWFAR();
- wfar -= (getCurCPSR() & PSR_T) ? 4 : 8;
- DSP_F4(S,"Break (", S,mes, S,") at ", 08X,wfar);
- DSP_F3(S," (R15/PC:", 08X,pc, S,")\n");
- } else {
- DSP_F5(S,"Break (", S,mes, S,") at ", 08X,pc, CH,'\n');
- }
- }
-
- /* restore stopped instruction */
- *cmd = (bp && bp->cmd[0] != 0) ? bp->cmd : NULL;
- return 1; /* wait for command */
-}
diff --git a/tkernel_source/monitor/cmdsvc/src/armv6/chkaddr.c b/tkernel_source/monitor/cmdsvc/src/armv6/chkaddr.c
deleted file mode 100644
index 1e88e62..0000000
--- a/tkernel_source/monitor/cmdsvc/src/armv6/chkaddr.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * chkaddr.c
- *
- * Check address
- */
-
-#include "../cmdsvc.h"
-
-LOCAL UW validLA; /* valid logical start address */
-LOCAL UW validSz; /* valid logical address size */
-LOCAL UW mmuStat; /* MMU state */
-
-/*
- Initialize address check data (executed upon monitor entry)
-*/
-EXPORT void initChkAddr(void)
-{
- validLA = validSz = 0; /* clear the previous effective addresses */
- mmuStat = getCP15(1, 0); /* MMU state */
-}
-/*
- Check memory address
- return contiguous range <= len (0 means illegal value)
- * pa physical address to access
-*/
-EXPORT W chkMemAddr(UW addr, UW *pa, W len, W rw)
-{
- const MEMSEG *mp;
- UW n;
-
- if (mmuStat & 0x1) { /* MMU is enabled */
- /* if the prevous check range doesn't include the address, */
- /* if the address is a valid existing address is checked by looking at page table. */
- if (addr < validLA || addr >= validLA + validSz) {
- UW pte, *ppte;
-
- /* Depending on the valid rage of TTBR0 described in TTBCR */
- /* TTBR0/TTBR1(=TopPageTable) is switched */
- pte = 0xfe000000 << (7 - (getCP15(2, 2) & 0x07));
- /* TTBCR */
- ppte = (addr & pte) ? TopPageTable :
- (UW *)(getCP15(2, 0) & ~0x7f); /* TTBR0 */
- pte = ppte[addr >> 20];
-
- validSz = 0;
- switch(pte & 0x3) {
- case 0x2: /* Section Entry */
- pte &= 0xFFF00000; /* Section Address */
- if (rw && AddrMatchMemArea(pte,
- MSA_ROM|MSA_FROM) != NULL)
- errinfo = E_ROM;
- else validSz = 0x100000; /* 1 MB */
- break;
- case 0x1: /* Page Table Entry */
- pte &= 0xFFFFFC00; /* Page Table Address */
- pte = *((UW*)(pte + ((addr >>(12-2))& 0x3FC)));
- switch(pte & 0x3) {
- case 0x1: /* Large Page : 16 KB x 4 */
- validSz = 0x10000; /* 64 KB */
- break;
- case 0x2: /* Small Page : 1 KB x 4 */
- case 0x3: /* Small Page with XN */
- validSz = 0x1000; /* 4 KB */
- break;
- }
- break;
- case 0x3: /* Fine Page Table Entry */
- break; /* unsupported */
- }
- validLA = (validSz) ? (addr & ~(validSz - 1)) : 0;
- }
-
- n = (validSz) ? (validLA + validSz - addr) : 0;
-
- } else { /* MMU is disabled, the unmodified address is used */
- mp = AddrMatchMemArea(addr, MSA_HW);
- if ( mp != NULL ) {
- if ( rw && (mp->attr & (MSA_ROM|MSA_FROM)) != 0 ) {
- n = 0;
- errinfo = E_ROM;
- } else {
- n = mp->end - addr;
- }
- } else {
- n = 0;
- }
- }
- *pa = addr; /* access by logical address */
- return (len > n) ? n : len;
-}
-/*
- I/O address check & conversion to physical address
- return contiguous range <= len (0 means illegal value)
- * pa I/O address to access
-*/
-EXPORT W chkIOAddr(UW addr, UW *pa, W len)
-{
- const MEMSEG *mp;
- UW n;
-
- mp = AddrMatchMemArea(addr, MSA_IO);
- n = ( mp != NULL )? mp->end - addr: 0;
-
- *pa = addr; /* access by logical address */
- return (len > n) ? n : len;
-}
-/*
- Validate PC
- return 0: OK, -1: illegal
-*/
-EXPORT W invalidPC(UW addr)
-{
- /* memory range check is not performed */
- /* an odd address needs to be regarded as THUMB, and so nothing is done here. */
- return 0;
-}
-EXPORT W invalidPC2(UW addr)
-{
- /* memory range check is not performed */
- /* PC of an ARM instruction is always on WORD-boundary */
- return (addr & 0x03) ? -1 : 0;
-}
diff --git a/tkernel_source/monitor/cmdsvc/src/armv6/cpudep.h b/tkernel_source/monitor/cmdsvc/src/armv6/cpudep.h
deleted file mode 100644
index e7ef92d..0000000
--- a/tkernel_source/monitor/cmdsvc/src/armv6/cpudep.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * cpudep.h
- *
- * CPU-dependent definitions(ARM)
- */
-
-#include <tk/sysdef.h>
-
-#ifndef _in_asm_source_
-
-IMPORT W bootFlag; /* boot flag */
-
-/*
- * Memory access through physical address
- * In the case of ARM, actually it is an access by logical address.
- */
-Inline UW rd_w( UW *pa )
-{
- return *pa;
-}
-Inline UH rd_h( UH *pa )
-{
- return *pa;
-}
-Inline UB rd_b( UB *pa )
-{
- return *pa;
-}
-
-Inline void wr_w( UW *pa, UW data )
-{
- *pa = data;
-}
-Inline void wr_h( UH *pa, UH data )
-{
- *pa = data;
-}
-Inline void wr_b( UB *pa, UB data )
-{
- *pa = data;
-}
-
-/*
- * read/write the ARM-specific registered under monitor management
- * read/set the value of registers at the time of monitor entry.
- */
-IMPORT UW getCP15( W reg, W opcd ); /* CP15 register reg: CRn, opcd: Op2 */
-IMPORT UW getCurPCX( void ); /* PC register (unmodified) */
-IMPORT void setCurPCX( UW val ); /* PC register (unmodified) */
-IMPORT UW getCurCPSR( void ); /* CPSR register */
-IMPORT UW getCurSPSR( void ); /* SPSR register */
-
-/*
- * Validate PC address
- * Allow only ARM instructions (on 4 bytes boundary).
- * If addr is valid then return 0, otherwise return -1.
- */
-IMPORT W invalidPC2( UW addr );
-
-/*
- * obtain step address
- */
-IMPORT W getStepAddr( UW pc, UW cpsr, W mode, UW* npc, UW *rep );
-
-#endif /* _in_asm_source_ */
diff --git a/tkernel_source/monitor/cmdsvc/src/armv6/disassemble.c b/tkernel_source/monitor/cmdsvc/src/armv6/disassemble.c
deleted file mode 100644
index 5f27062..0000000
--- a/tkernel_source/monitor/cmdsvc/src/armv6/disassemble.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by T-Engine Forum at 2013/03/04.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * disasemble.c
- *
- * disassember
- */
-
-#include "../cmdsvc.h"
-
-LOCAL UB *make_hex(UB *str, UB byte)
-{
- LOCAL const UB hex[] = "0123456789ABCDEF";
-
- *str++ = hex[(byte >> 4) & 0x0f];
- *str++ = hex[(byte >> 0) & 0x0f];
-
- return str;
-}
-
-/*
- disassembler main body
-
- * disassembly is not fully done. But, during step tracing,
- memory content is shown (this much is implemented).
- the content of *naddr is meaningless
- */
-EXPORT ER disAssemble(UW *saddr, UW *naddr, UB *str)
-{
- W len;
- UW inst, addr;
-
- len = (*saddr & 0x1) ? 2 : 4; /* Thumb or Arm instruction */
- addr = (*saddr &= ~(len - 1)); /* address adjustment */
-
- /* extract op code */
- if (readMem(addr, &inst, len, 2) != len) return E_MACV;
-
- /* binary dump */
- if (len == 4) {
- str = make_hex(str, inst >> 24);
- str = make_hex(str, inst >> 16);
- }
- str = make_hex(str, inst >> 8);
- str = make_hex(str, inst >> 0);
-
- *str = '\0';
-
- return E_OK;
-}
diff --git a/tkernel_source/monitor/cmdsvc/src/armv6/misc.c b/tkernel_source/monitor/cmdsvc/src/armv6/misc.c
deleted file mode 100644
index cc58200..0000000
--- a/tkernel_source/monitor/cmdsvc/src/armv6/misc.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * misc.c
- *
- */
-
-#include "../cmdsvc.h"
-#include <sys/rominfo.h>
-
-/*
- * Invoking user reset initialization routine
- */
-EXPORT void callUserResetInit( void )
-{
- UW wp = (UW)ROMInfo->resetinit;
-
- if ( invalidPC2(wp)
- || !inMemArea(wp, wp+4, MSA_ROM|MSA_FROM)
- || inMemArea(wp, wp+4, MSA_MON) ) return; /* invalid */
-
- callExtProg(ROMInfo->resetinit);
-}
-
-/*
- * Prepare ROM kernel execution
- * It means that we don't execute ROM kernel immediately, but we prepare so that upon return from the ordinary monitor,
- * it gets executed.
- */
-EXPORT ER bootROM( void )
-{
- UW wp = (UW)ROMInfo->kernel;
-
- if ( invalidPC2(wp)
- || !inMemArea(wp, wp+4, MSA_ROM|MSA_FROM)
- || inMemArea(wp, wp+4, MSA_MON) ) return E_NOEXS; /* invalid */
-
- /* set boot configuration */
- setUpBoot(ROMInfo->kernel, NULL);
-
- return E_OK;
-}
diff --git a/tkernel_source/monitor/cmdsvc/src/armv6/monent.c b/tkernel_source/monitor/cmdsvc/src/armv6/monent.c
deleted file mode 100644
index 2cba3d8..0000000
--- a/tkernel_source/monitor/cmdsvc/src/armv6/monent.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * monent.c
- *
- * Entry to monitor
- */
-
-#include "../cmdsvc.h"
-#include <sys/sysinfo.h>
-
-EXPORT W bootFlag; /* boot flag */
-
-/*
- * monitor entry processing
- * vec exception vector number
- */
-EXPORT void entMonitor( UW vec )
-{
- UW v;
- W bpflg;
- UB *cmd;
- UW save_taskmode;
-
- /* update task mode */
- save_taskmode = SCInfo.taskmode;
- SCInfo.taskmode <<= 16;
-
- /* monitor entry processing (flushing cache, etc.) */
- enterMonitor(0);
-
- /* initialize address check data */
- initChkAddr();
-
- /* release breakpoint temporarily */
- bpflg = resetBreak(vec);
-
- bootFlag = 0;
-
- switch ( vec ) {
- case EIT_DEFAULT: /* reset */
- if ( bootSelect() == BS_AUTO ) {
- /* automatic boot */
- if ( bootDisk(NULL) >= E_OK ) break; /* execute boot */
- }
- /* invoke monitor */
- dispTitle(); /* boot message */
- procCommand(NULL, 0); /* command processing */
- break;
-
- case SWI_MONITOR: /* service call */
- /* Execute SVC: Parameters given are, r12(fn), r0, r1, r2, r3 */
- v = procSVC(getRegister(12), getRegister(0),
- getRegister(1), getRegister(2), getRegister(3));
-
- /* At boot time, r0 holds the boot parameter,
- so don't change r0 */
- if ( bootFlag == 0 ) setRegister(0, v); /* result is set to 0 */
- break;
-
- case EIT_IDEBUG: /* debug abort instruction */
- case EIT_DDEBUG: /* debug abort data */
- if ( procBreak(bpflg, &cmd) > 0 ) {
- procCommand(cmd, 0);
- }
- break;
-
- default: /* unsupported instruction exception, interrupt, or traps */
- if ( procEIT(vec) == 0 ) {
- stopTrace(); /* stop tracing */
- procCommand(NULL, 0); /* command processing */
- }
- }
-
- /* set breakpoint */
- setupBreak();
-
- /* monitor exit processing (flushing cache, etc.) */
- leaveMonitor(getCP15(1, 0));
-
- /* restore task mode */
- SCInfo.taskmode = save_taskmode;
-
- return; /* returning leads to user program execution */
-}
diff --git a/tkernel_source/monitor/cmdsvc/src/armv6/monhdr.S b/tkernel_source/monitor/cmdsvc/src/armv6/monhdr.S
deleted file mode 100644
index 6acee3e..0000000
--- a/tkernel_source/monitor/cmdsvc/src/armv6/monhdr.S
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * monhdr.S
- *
- * Monitor handler (after ARMv6)
- */
-
-#define _in_asm_source_
-
-#include <machine.h>
-#include <sys/sysinfo.h>
-#include "cpudep.h"
-
-/*
- * Monitor entry (registered as default handler)
- * +---------------+
- * sp -> |R3 | <- only in the case of interrupt
- * +---------------+
- * |R12=ip |
- * |R14=lr | <- return address from exception / interupt
- * |SPSR |
- * +---------------+
- * registers upon handler invocation
- * r3 = varies according machine type and situation (only in the case of interrupt)
- * ip = vector table address
- * lr = indeterminate
- */
- .text
- .balign 4
- .globl Csym(_defaultHdr)
- .type Csym(_defaultHdr), %function
-Csym(_defaultHdr):
- // save register
- // regStack[0-7] r0 .. r7
- // [8,9] Entry cspr, ip
- // [10] return cspr
- // [11] return r15(pc)
- // [12-18] USR: r8 ..r12, sp, lr
- // [19-26] FIQ: spsr, r8 ..r12, sp, lr
- // [27-29] IRQ: spsr, sp, lr
- // [30-32] ABT: spsr, sp, lr
- // [33-35] UND: spsr, sp, lr
- // [36-38] SVC: spsr, sp, lr
- // [39] CP15: SCTLR (CP15.c1.0.c0.0)
- // [40-42] TTBR0,TTBR1,TTBCR (CP15.c2.0.c0.0 - 2)
- // [43] DACR (CP15.c3.0.c0.0)
- // [44-45] DFSR,IFSR (CP15.c5.0.c0.0 - 1)
- // [46-47] DFAR,IFAR (CP15.c6.0.c0.0,2)
- // [48] CTXIDR (CP15.c13.0.c0.1)
-
- // save r0 .. r7
- ldr lr, =Csym(regStack)
- stmia lr!, {r0-r2} // r0 .. r2
-
- // restore R3 inside stack in the case of interrupt
- mrs r1, cpsr // cpsr -> r1
- and r0, r1, #PSR_M(31)
- cmp r0, #PSR_FIQ
- cmpne r0, #PSR_IRQ
- ldmeqfd sp!, {r3} // in the case of interrupt
-
- stmia lr!, {r3-r7} // r3 .. r7
- mov r7, lr // regStack -> r7
-
- // save the status on entry (cpsr, ip)
- cpsid aif // disable FIQ and IRQ
- stmia r7!, {r1, ip} // Entry cspr & ip saved
-
- // restore ip, lr, spsr from the values inside stack and return
- ldr r2, =EIT_VECTBL
- sub r0, ip, r2
- mov r0, r0, asr #2 // interrupt/exception vector number -> r0
- ldmfd sp!, {ip, lr} // restore ip and lr
- ldmfd sp!, {r2} // r2 <- spsr restored
- stmia r7!, {r2, lr} // save spsr, lr(pc)
-
- // save registers of each mode
- stmia r7, {r8-r12,sp,lr}^ // usr: r8 .. r12,sp,lr
- add r7, r7, #(4*7)
-
- cps #PSR_FIQ
- mrs r3, spsr
- stmia r7!, {r3, r8-r12,sp,lr} // fiq: spsr, r8 .. r12,sp,lr
-
- cps #PSR_IRQ
- mrs r3, spsr
- stmia r7!, {r3, sp, lr} // irq: spsr, sp, lr
-
- cps #PSR_ABT
- mrs r3, spsr
- stmia r7!, {r3, sp, lr} // abt: spsr, sp, lr
-
- cps #PSR_UND
- mrs r3, spsr
- stmia r7!, {r3, sp, lr} // und: spsr, sp, lr
-
- cps #PSR_SVC
- mrs r3, spsr
- stmia r7!, {r3, sp, lr} // svc: spsr, sp, lr
-
- mrc p15, 0, r2, cr1, cr0, 0
- mrc p15, 0, r3, cr2, cr0, 0
- mrc p15, 0, r4, cr2, cr0, 1
- mrc p15, 0, r5, cr2, cr0, 2
- mrc p15, 0, r6, cr3, cr0, 0
- stmia r7!, {r2,r3,r4,r5,r6} // cp15: r1,r2,r3
-
- mrc p15, 0, r2, cr5, cr0, 0
- mrc p15, 0, r3, cr5, cr0, 1
- mrc p15, 0, r4, cr6, cr0, 0
- mrc p15, 0, r5, cr6, cr0, 2
- mrc p15, 0, r6, cr13, cr0, 1 // cp15: r5,r6,r13
- stmia r7!, {r2,r3,r4,r5,r6}
-
- ldr r2, =0xFFFFFFFF
- mcr p15, 0, r2, cr3, cr0, 0 // cp15:r3(domain) manager
-
- // set up stack exclusively used for monitor (SVC mode)
- ldr r2, =__stack_top
- ldr r3, =__stack_bottom // stack exclusively used for monitor
- cmp sp, r2
- cmpcs r3, sp // using monitor stack?
- movcc sp, r3 // switch to monitor stack
-
- // monitor entry: r0 = interrupt/exception vector number (r1 = cpsr) : SVC mode
- bl Csym(entMonitor) // call entMonitor(vec)
-
- // restore registers
- ldr r7, =Csym(regStack) + ((39 + 10) * 4)
-
- ldmdb r7!, {r2,r3,r4,r5,r6} // cp15: r5,r6,r13
- mcr p15, 0, r2, cr5, cr0, 0
- mcr p15, 0, r3, cr5, cr0, 1
- mcr p15, 0, r4, cr6, cr0, 0
- mcr p15, 0, r5, cr6, cr0, 2
- mcr p15, 0, r6, cr13, cr0, 1
-
- ldmdb r7!, {r2,r3,r4,r5,r6} // cp15: r1,r2,r3
-// mcr p15, 0, r2, cr1, cr0, 0 // already restored inside entMonitor
-//RO mcr p15, 0, r3, cr2, cr0, 0 // no need to restore (Read Only)
-//RO mcr p15, 0, r4, cr2, cr0, 1
-//RO mcr p15, 0, r5, cr2, cr0, 2
- mcr p15, 0, r6, cr3, cr0, 0
-
- ldmdb r7!, {r3, sp, lr} // svc: spsr, sp, lr
- msr spsr_fsxc, r3
- mov r1, lr // r1: lr_svc (used for forcible terminal of processes)
-
- cps #PSR_UND
- ldmdb r7!, {r3, sp, lr} // und: spsr, sp, lr
- msr spsr_fsxc, r3
-
- cps #PSR_ABT
- ldmdb r7!, {r3, sp, lr} // abt: spsr, sp, lr
- msr spsr_fsxc, r3
-
- cps #PSR_IRQ
- ldmdb r7!, {r3, sp, lr} // irq: spsr, sp, lr
- msr spsr_fsxc, r3
-
- cps #PSR_FIQ
- ldmdb r7!, {r3, r8-r12,sp,lr} // fiq: spsr, r8 .. r12,sp,lr
- msr spsr_fsxc, r3
-
- sub r7, r7, #(4*7)
- ldmia r7, {r8-r12,sp,lr}^ // usr: r8 .. r12,sp,lr
-
- // restore status on etry
- ldmdb r7!, {r0, r2, r3, r4} // r0:Entry cpsr, r2:Entry ip
- // r3:cpsr(spsr), r4:pc(lr)
- msr cpsr_fsxc, r0 // entry cpsr
- stmfd sp!, {r3} // spsr -> stack
- stmfd sp!, {r4} // pc(lr) -> stack
-
- // do we have request for forcible termination of processe(es)?
- ldr r4, =Csym(killProcReq)
- ldr r0, [r4]
- tst r0, #0xff
- beq no_kill // no request
- mov r0, #0
- str r0, [r4] // clear forcible termination request
-
- // restore to the state on entry completely, and then push lr_svc
- stmfd sp!, {r1, ip} // sp -> lr_svc, ip
- mov ip, r2 // restore ip
- ldmdb r7, {r0-r7} // r0 .. r7
-
- swi #SWI_KILLPROC // forcible termination of processes request
- nop // do not return
- nop
-
- no_kill:
- ldmdb r7, {r0-r7} // r0 .. r7
-
- // return from monitor
- rfefd sp!
-
-/* ------------------------------------------------------------------------ */
-
-/*
- * calling an external program
- * W callExtProg( FP entry )
- */
- .text
- .balign 4
- .globl Csym(callExtProg)
- .type Csym(callExtProg), %function
-Csym(callExtProg):
- stmfd sp!, {r4-r10, fp, lr} // save registers
- blx r0 // call entry(void)
- ldmfd sp!, {r4-r10, fp, pc} // restore registers
diff --git a/tkernel_source/monitor/cmdsvc/src/armv6/register.c b/tkernel_source/monitor/cmdsvc/src/armv6/register.c
deleted file mode 100644
index 2e24f18..0000000
--- a/tkernel_source/monitor/cmdsvc/src/armv6/register.c
+++ /dev/null
@@ -1,430 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by T-Engine Forum at 2013/03/04.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * register.c
- *
- * Register-related operations (after ARMV6)
- */
-
-#include "../cmdsvc.h"
-#include <sys/sysinfo.h>
-
-EXPORT UW regStack[39 + 10 + 2];
-
-/*
- register definition table
-
- * registers are saved to regStack on entry to the monitor.
- The value in register ID follows the order saved in register stack (below).
- (See eitent.S)
-
- regStack[0-7] r0 .. r7
- [8,9] Entry cspr, ip
- [10] return cspr
- [11] return r15(pc)
- [12-18] USR: r8 ..r12, sp, lr
- [19-26] FIQ: spsr, r8 ..r12, sp, lr
- [27-29] IRQ: spsr, sp, lr
- [30-32] ABT: spsr, sp, lr
- [33-35] UND: spsr, sp, lr
- [36-38] SVC: spsr, sp, lr
-
- [39] CP15: SCTLR (CP15.c1.0.c0.0)
- [40-42] TTBR0,TTBR1,TTBCR (CP15.c2.0.c0.0 - 2)
- [43] DACR (CP15.c3.0.c0.0)
- [44-45] DFSR,IFSR (CP15.c5.0.c0.0 - 1)
- [46-47] DFAR,IFAR (CP15.c6.0.c0.0,2)
- [48] CTXIDR (CP15.c13.0.c0.1)
-*/
-
-#define L_REGNM 8
-typedef struct {
- UB name[L_REGNM]; /* register name */
- UW id; /* register ID */
-} REGTAB;
-
-#define R_GEN 0x001000 /* general register */
-#define R_CTL 0x002000 /* control register */
-#define R_GRP 0x010000 /* register group */
-
-#define R_LF 0x080000 /* forced linefeed */
-#define R_GAP 0x040000 /* empty line */
-
-#define R_ONLY 0x100 /* disable setup */
-#define SPEC(n) (0x200 | (n)) /* special */
-
-#define ixCPSR 10 /* CPSR index */
-#define ixPC 11 /* PC index */
-
-#define ixUSR 12
-#define ixFIQ (19 + 1) /* FIQ: SPSR,R8-R14 */
-#define ixIRQ (27 - 4) /* IRQ: SPSR,R13,R14 */
-#define ixABT (30 - 4) /* ABT: SPSR,R13,R14 */
-#define ixUND (33 - 4) /* UND: SPSR,R13,R14 */
-#define ixSVC (36 - 4) /* SVC: SPSR,R13,R14 */
-#define ixSP_SVC (ixSVC + 5) /* SVC SP index */
-
-#define ixCP15 39 /* CP15 index */
-#define ixCP15R1 (ixCP15 + 0)
-
-#define N_ACTREGS (16 + 7 + 7 + 8 + 7 + 10)
-#define N_REGS (N_ACTREGS + 3)
-
-LOCAL const REGTAB regTab[N_REGS] = {
- {"R0 ", R_GEN + 0x00 }, /* 0 */
- {"R1 ", R_GEN + 0x01 }, /* 1 */
- {"R2 ", R_GEN + 0x02 }, /* 2 */
- {"R3 ", R_GEN + 0x03 + R_LF }, /* 3 */
- {"R4 ", R_GEN + 0x04 }, /* 4 */
- {"R5 ", R_GEN + 0x05 }, /* 5 */
- {"R6 ", R_GEN + 0x06 }, /* 6 */
- {"R7 ", R_GEN + 0x07 + R_LF }, /* 7 */
- {"R8 ", R_GEN + SPEC(0x00) }, /* 8 */
- {"R9 ", R_GEN + SPEC(0x01) }, /* 9 */
- {"R10/SL ", R_GEN + SPEC(0x02) }, /* 10 */
- {"R11/FP ", R_GEN + SPEC(0x03) + R_LF }, /* 11 */
- {"R12/IP ", R_GEN + SPEC(0x04) }, /* 12 */
- {"R13/SP ", R_GEN + SPEC(0x05) }, /* 13 */
- {"R14/LR ", R_GEN + SPEC(0x06) }, /* 14 */
- {"R15/PC ", R_GEN + ixPC + R_LF }, /* 15 */
-
- {"R8_USR ", R_GEN + ixUSR + 0 + R_GAP }, /* 16 */
- {"R9_USR ", R_GEN + ixUSR + 1 }, /* 17 */
- {"R10_USR ", R_GEN + ixUSR + 2 }, /* 18 */
- {"R11_USR ", R_GEN + ixUSR + 3 + R_LF }, /* 19 */
- {"R12_USR ", R_GEN + ixUSR + 4 }, /* 20 */
- {"R13_USR ", R_GEN + ixUSR + 5 }, /* 21 */
- {"R14_USR ", R_GEN + ixUSR + 6 + R_LF }, /* 22 */
-
- {"R8_FIQ ", R_GEN + ixFIQ + 0 }, /* 23 */
- {"R9_FIQ ", R_GEN + ixFIQ + 1 }, /* 24 */
- {"R10_FIQ ", R_GEN + ixFIQ + 2 }, /* 25 */
- {"R11_FIQ ", R_GEN + ixFIQ + 3 + R_LF }, /* 26 */
- {"R12_FIQ ", R_GEN + ixFIQ + 4 }, /* 27 */
- {"R13_FIQ ", R_GEN + ixFIQ + 5 }, /* 28 */
- {"R14_FIQ ", R_GEN + ixFIQ + 6 + R_LF }, /* 29 */
-
- {"R13_IRQ ", R_GEN + ixIRQ + 5 }, /* 30 */
- {"R14_IRQ ", R_GEN + ixIRQ + 6 }, /* 31 */
- {"R13_SVC ", R_GEN + ixSVC + 5 }, /* 32 */
- {"R14_SVC ", R_GEN + ixSVC + 6 + R_LF }, /* 33 */
- {"R13_ABT ", R_GEN + ixABT + 5 }, /* 34 */
- {"R14_ABT ", R_GEN + ixABT + 6 }, /* 35 */
- {"R13_UND ", R_GEN + ixUND + 5 }, /* 36 */
- {"R14_UND ", R_GEN + ixUND + 6 + R_LF }, /* 37 */
-
- {"CPSR ", R_CTL + ixCPSR + R_GAP }, /* 38 */
- {"SPSR ", R_CTL + SPEC(0x08) }, /* 39 */
- {"SPSR_FIQ", R_CTL + ixFIQ - 1 }, /* 40 */
- {"SPSR_IRQ", R_CTL + ixIRQ + 4 + R_LF }, /* 41 */
- {"SPSR_SVC", R_CTL + ixSVC + 4 }, /* 42 */
- {"SPSR_ABT", R_CTL + ixABT + 4 }, /* 43 */
- {"SPSR_UND", R_CTL + ixUND + 4 + R_LF }, /* 44 */
-
- {"SCTLR ", R_CTL + SPEC(0x0F) + 0 + R_GAP }, /* 45 */
- {"TTBR0 ", R_CTL + ixCP15 + 1 + R_ONLY }, /* 46 */
- {"TTBR1 ", R_CTL + ixCP15 + 2 + R_ONLY }, /* 47 */
- {"TTBCR ", R_CTL + ixCP15 + 3 + R_ONLY + R_LF}, /* 48 */
- {"DACR ", R_CTL + ixCP15 + 4 }, /* 49 */
- {"DFSR ", R_CTL + ixCP15 + 5 }, /* 50 */
- {"IFSR ", R_CTL + ixCP15 + 6 }, /* 51 */
- {"DFAR ", R_CTL + ixCP15 + 7 + R_LF }, /* 52 */
- {"IFAR ", R_CTL + ixCP15 + 8 }, /* 53 */
- {"CTXIDR ", R_CTL + ixCP15 + 9 + R_LF }, /* 54 */
-
- {"G ", R_GRP|R_GEN },
- {"C ", R_GRP|R_CTL },
- {"A ", R_GRP|R_GEN|R_CTL },
-};
-/*
- Searching register name
-*/
-EXPORT W searchRegister(UB *name, W grp)
-{
- W i, n, a;
- UB bf[L_REGNM];
- REGTAB *p;
-
- if (name[L_REGNM] != ' ') return -1;
-
- for (p = (REGTAB*)regTab, i = 0; i < N_REGS; p++, i++) {
- for (n = 0; n < L_REGNM; n++) if (p->name[n] == '/') break;
- if (n == L_REGNM) { /* no separator '/' -> a single register name */
- if (memcmp(name, p->name, L_REGNM)) continue;
- } else { /* has alias */
- /* check the name(s) after the separator */
- memset(bf, ' ', sizeof(bf));
- memcpy(bf, p->name + (n + 1), L_REGNM - (n + 1));
- a = memcmp(name, bf, L_REGNM - n);
-
- /* check the name before the separator */
- memset(bf, ' ', sizeof(bf));
- memcpy(bf, p->name, n);
- if (a && memcmp(name, bf, n + 1)) continue;
- }
- if (grp == 0 && (p->id & R_GRP)) break;
- return i;
- }
- return -1;
-}
-/*
- obtain CPU mode index
-*/
-LOCAL W ixCpuMode(void)
-{
- /* obtain mode */
- switch(regStack[ixCPSR] & PSR_M(31)) {
- case PSR_USR:
- case PSR_SYS: return ixUSR;
- case PSR_FIQ: return ixFIQ;
- case PSR_IRQ: return ixIRQ;
- case PSR_SVC: return ixSVC;
- case PSR_ABT: return ixABT;
- case PSR_UND: return ixUND;
- }
- return 0;
-}
-/*
- obtain register value
-*/
-EXPORT UW getRegister(W regno)
-{
- W i, ix;
-
- i = regTab[regno].id & (R_GRP | 0x3ff);
-
- /* normal register */
- if (i < SPEC(0)) return regStack[i & 0xff];
-
- /* obtain mode */
- ix = ixCpuMode();
-
- /* special register */
- switch(i) {
- case SPEC(0x00): /* R8 */
- case SPEC(0x01): /* R9 */
- case SPEC(0x02): /* R10 */
- case SPEC(0x03): /* R11 */
- case SPEC(0x04): /* R12 */
- if (ix != ixFIQ) ix = ixUSR;
- case SPEC(0x05): /* R13 */
- case SPEC(0x06): /* R14 */
- return regStack[ix + i - SPEC(0)];
- case SPEC(0x08): /* SPSR */
- if (ix == ixUSR) return 0; /* undefined */
- if (ix == ixFIQ) ix -= 5;
- return regStack[ix + 4];
- case SPEC(0x0F): /* CP15 R1 */
- return regStack[ixCP15R1];
- }
- /* retur 0 on error */
- return 0;
-}
-/*
- Set register value
-*/
-EXPORT ER setRegister(W regno, UW val)
-{
- W i, ix;
-
- i = regTab[regno].id & (R_GRP | 0x3ff);
- if (i & R_ONLY) return E_RONLY; /* cannot be set */
-
- if (i < SPEC(0)) { /* normal register */
- regStack[i & 0xff] = val;
- return 0;
- }
-
- /* obtain mode */
- ix = ixCpuMode();
-
- /* special register */
- switch(i) {
- case SPEC(0x00): /* R8 */
- case SPEC(0x01): /* R9 */
- case SPEC(0x02): /* R10 */
- case SPEC(0x03): /* R11 */
- case SPEC(0x04): /* R12 */
- if (ix != ixFIQ) ix = ixUSR;
- case SPEC(0x05): /* R13 */
- case SPEC(0x06): /* R14 */
- regStack[ix + i - SPEC(0x00)] = val;
- break;
- case SPEC(0x08): /* SPSR */
- if (ix == ixUSR) break; /* undefined */
- if (ix == ixFIQ) ix -= 5;
- regStack[ix + 4] = val;
- break;
- case SPEC(0x0F): /* CP15 R1 */
- regStack[ixCP15R1] &= MASK_CACHEMMU;
- regStack[ixCP15R1] |= val & VALID_CACHEMMU;
- break;
- default:
- return E_PAR;
- }
- return 0;
-}
-/*
- List the values of register (group)
- regno < 0 : default group (not specified)
-*/
-EXPORT void dispRegister(W regno)
-{
- W i, j, n, id, rid;
-
- if (regno >= N_REGS) return;
-
- id = (regno < 0) ? (R_GRP | R_GEN) : regTab[regno].id;
-
- for (n = i = 0; i < N_ACTREGS; i++) {
- rid = regTab[i].id;
- if (!(i == regno || ((id & R_GRP) && (rid & id)))) continue;
- if (n != 0 && (rid & R_GAP)) DSP_LF;
- if (n++ & 0x0f) DSP_S(" ");
- for (j = 0; j < L_REGNM; j++) DSP_CH(regTab[i].name[j]);
- DSP_F2(S,": ", 08X,getRegister(i));
- if (rid & R_LF) {DSP_LF; n = 0x10;}
- if ((id & R_GRP) == 0) break;
- }
- if (n & 0x0f) DSP_LF;
-}
-/*
- obtain CPSR register value
-*/
-EXPORT UW getCurCPSR(void)
-{
- return regStack[ixCPSR];
-}
-/*
- obtain SPSR register value
-*/
-EXPORT UW getCurSPSR(void)
-{
- return getRegister(39);
-}
-/*
- obtain PC register value
-*/
-EXPORT UW getCurPC(void)
-{
- /* set LSB = 1 for Thumb mode. */
- return regStack[ixPC] | ((regStack[ixCPSR] & PSR_T) ? 1 : 0);
-}
-EXPORT UW getCurPCX(void)
-{
- return regStack[ixPC];
-}
-EXPORT UW getCP15(W reg, W opcd)
-{
- W i, d;
- LOCAL const UH reg_op[] = {
- 0x1000, 0x2000, 0x2001, 0x2002, 0x3000, 0x5000, 0x5001, 0x6000,
- 0x6002, 0xd001,
- };
-
- d = ((reg & 0x0f) << 12) | (opcd & 0x0fff);
-
- for (i = 0; i < sizeof(reg_op) / sizeof(UH); i++) {
- if (reg_op[i] == d) return regStack[ixCP15 + i];
- }
- return 0;
-}
-/*
- Set PC register value
-*/
-EXPORT void setCurPC(UW val)
-{
- if (regStack[ixPC] != val) {
- /* Thumb Bit is changed according to the LSB value of PC. */
- if (val & 0x3) regStack[ixCPSR] |= PSR_T;
- else regStack[ixCPSR] &= ~PSR_T;
- regStack[ixPC] = val & ~0x1;
- }
-}
-EXPORT void setCurPCX(UW val)
-{
- /* Thumb Bit is not changed. */
- regStack[ixPC] = val & ~0x1;
-}
-/*
- Set registers for BOOT
-*/
-EXPORT void setUpBoot( void *start, BootInfo *bootinfo )
-{
- bootFlag = 1; /* suppress the setting register R0 upon exit of the monitor */
-
- regStack[ixCPSR] = PSR_I | PSR_F | PSR_SVC;
- regStack[0] = (UW)bootinfo; /* R0 boot parameter */
- regStack[ixPC] = (UW)start; /* PC start address */
- regStack[ixSP_SVC] = (UW)&__stack_bottom; /* SP monitor stack */
-
- /* MMU enabled, Cache / Write Buffer not enabled */
- regStack[ixCP15R1] &= MASK_CACHEMMU;
- regStack[ixCP15R1] |= ENB_MMUONLY;
-
- /* system initialization processing */
- resetSystem(1);
-}
-/*
- Check whether we can use KILL command
-*/
-EXPORT W isKillValid(void)
-{
- /* Has TRAP for KILL been define? */
- if ( SCArea->intvec[SWI_KILLPROC] == NULL ) return -1;
- return 0;
-}
-
-#ifdef REF_TKOBJECT
-/*
- Check whether T-Kernel/DS functions can be executed?
-*/
-EXPORT W isTKDSValid(void)
-{
- /* Has TRAP for T-Kernel/DS been defined? */
- if ( SCArea->intvec[SWI_DEBUG] == NULL ) return -1;
- return 0;
-}
-
-/*
- Display register of tasks
-*/
-EXPORT W PrintTaskRegister( int (*prfn)( const char *format, ... ),
- T_REGS *gr, T_EIT *er, T_CREGS *cr )
-{
-/*
- * PC: 12345678 CPSR:12345678 TMF:12345678
- * R0: 12345678 R1: 12345678 R2: 12345678 R3: 12345678
- * R4: 12345678 R5: 12345678 R6: 12345678 R7: 12345678
- * R8: 12345678 R9: 12345678 R10:12345678 R11:12345678
- * IP: 12345678 LR: 12345678
- * USP:12345678 SSP:12345678 LSID:1234 UATB:12345678
- */
- (*prfn)("PC: %08x CPSR:%08x TMF:%08x\n",
- (UW)er->pc, er->cpsr, er->taskmode);
- (*prfn)("R0: %08x R1: %08x R2: %08x R3: %08x\n",
- gr->r[0], gr->r[1], gr->r[2], gr->r[3]);
- (*prfn)("R4: %08x R5: %08x R6: %08x R7: %08x\n",
- gr->r[4], gr->r[5], gr->r[6], gr->r[7]);
- (*prfn)("R8: %08x R9: %08x R10:%08x R11:%08x\n",
- gr->r[8], gr->r[9], gr->r[10], gr->r[11]);
- (*prfn)("IP: %08x LR: %08x\n",
- gr->r[12], (UW)gr->lr);
- (*prfn)("USP:%08x SSP:%08x LSID:%-4d UATB:%08x\n",
- (UW)cr->usp, (UW)cr->ssp, cr->lsid, (UW)cr->uatb);
- return 6; /* number of display lines */
-}
-#endif /* REF_TKOBJECT */
diff --git a/tkernel_source/monitor/cmdsvc/src/armv6/step.c b/tkernel_source/monitor/cmdsvc/src/armv6/step.c
deleted file mode 100644
index 6b1310d..0000000
--- a/tkernel_source/monitor/cmdsvc/src/armv6/step.c
+++ /dev/null
@@ -1,499 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by T-Engine Forum at 2013/03/04.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * step.c
- *
- * calculate step address
- */
-
-#include "../cmdsvc.h"
-
-#define aINSTSZ 4 /* ARM instruction size */
-#define tINSTSZ 2 /* THUMB instruction size */
-#define REGBIT(reg) (1 << (reg)) /* register bit */
-#define REGSZ 4 /* register size */
-#define regPC 15 /* PC register */
-#define regSP 13 /* SP register */
-
-LOCAL UW curCPSR; /* cpsr */
-LOCAL UW nextPC; /* the next PC value */
-LOCAL W nextLen; /* size of the next instruction(2 or 4) */
-LOCAL UW repInst; /* instruction to replace */
-LOCAL W repReg; /* register to be replaced */
-LOCAL W trcNext; /* NEXT trace mode */
-
-/*
- extraction of fields of an instruction
-*/
-LOCAL UW getInstField(UW mask, W sht)
-{
- return (repInst & mask) >> sht;
-}
-/*
- set the register field of the instruction to be replaced
-*/
-LOCAL void setRepInst(UW mask, W sht)
-{
- repInst = (repInst & ~mask) | ((repReg & 0xF) << sht);
-}
-/*
- Obtain an unused register for replacement
-*/
-LOCAL W getRepReg(UW reg)
-{
- W i;
-
- for (i = 0; i < 16 && (reg & 0x1); i++, reg >>= 1);
- return i + 0x10; /* register number + flag */
-}
-/*
- Validate instruction execution condition
-*/
-LOCAL W checkCond(W cond)
-{
- UW sr = curCPSR;
-
- switch(cond) {
- case 0: /* EQ: z */
- if (sr & PSR_Z) return 1; break;
- case 1: /* NE: !z */
- if (!(sr & PSR_Z)) return 1; break;
- case 2: /* CS: c */
- if (sr & PSR_C) return 1; break;
- case 3: /* CC: !c */
- if (!(sr & PSR_C)) return 1; break;
- case 4: /* MI: n */
- if (sr & PSR_N) return 1; break;
- case 5: /* PL: !n */
- if (!(sr & PSR_N)) return 1; break;
- case 6: /* VS: v */
- if (sr & PSR_V) return 1; break;
- case 7: /* VC: !v */
- if (!(sr & PSR_V)) return 1; break;
- case 8: /* HI: c && !z */
- if ((sr & (PSR_C | PSR_Z)) == PSR_C) return 1; break;
- case 9: /* LS: !c || z */
- if (!(sr& PSR_C) || (sr & PSR_Z)) return 1; break;
- case 12: /* GT: !z && (n == v) */
- if (sr & PSR_Z) return 0;
- case 10: /* GE: n == v */
- sr &= PSR_N | PSR_V;
- if (sr == 0 || sr == (PSR_N | PSR_V)) return 1; break;
- case 13: /* LE: z || (n != v) */
- if (sr & PSR_Z) return 1;
- case 11: /* LT: n != v */
- sr &= PSR_N | PSR_V;
- if (sr == PSR_N || sr == PSR_V) return 1; break;
- case 14: /* AL: */
- case 15: /* NV: */
- return 1;
- }
- return 0;
-}
-/*
- non-branching instruction
-*/
-LOCAL void noBranch(UW inst)
-{
-}
-/*
- ARM: Bcond / BLX(1) instruction
-*/
-LOCAL void armBInst(UW inst)
-{
- W off;
-
- /* BL is not handled during NEXT trace */
- if (trcNext) {
- if (inst & 0x01000000) return; /* BL */
- if (inst >= 0xF0000000) return; /* BLX(1) */
- }
- off = (inst & 0x00FFFFFF) << 2;
- if (off & 0x02000000) off -= 0x04000000; /* sign extension */
- nextPC += aINSTSZ + off;
-
- if (inst >= 0xF0000000) { /* BLX(1) */
- nextPC += getInstField(0x01000000, 24) << 1;
- /* adjust for Thumb mode (on two bytes boundary) */
- nextLen = tINSTSZ; /* THUMB mode */
- }
-}
-/*
- ARM: BX / BLX(2) instruction
-*/
-LOCAL void armBxInst(UW inst)
-{
- /* BL is not handled during NEXT trace */
- if (trcNext) {
- if (inst & 0x00000020) return; /* BLX(2) */
- }
- inst &= 0x0000000F;
- if (inst == regPC) {
- nextPC += aINSTSZ;
- } else {
- nextPC = getRegister(inst);
- }
- if (nextPC & 1) nextLen = tINSTSZ; /* THUMB mode */
-}
-/*
- ARM: data processing instruction rd = pc
-*/
-LOCAL void armOpInst(UW inst)
-{
- W rn, rm;
- UW usereg;
-
- /* TST, TEQ, CMP, CMPN instructions are not handled */
- rm = inst & 0x01E00000;
- if (rm >= 0x01000000 && rm <= 0x01600000) return;
-
- /* OP1 register */
- rn = getInstField(0x000F0000, 16);
- usereg = REGBIT(rn);
-
- /* OP2 register */
- if (!(inst & 0x02000000)) {
- rm = getInstField(0x0000000F, 0);
- usereg |= REGBIT(rm);
- if (inst & 0x00000010) /* shift length register */
- usereg |= REGBIT(getInstField(0x00000F00, 8));
- }
- /*register to be replaced */
- repReg = getRepReg(usereg);
-
- /* Dest register replacement */
- setRepInst(0x0000F000, 12);
-
- /* OP1 register replacement */
- if (rn == regPC) setRepInst(0x000F0000, 16);
-
- /* OP2 register replacement */
- if (rm == regPC) setRepInst(0x0000000F, 0);
-
- /* if S bit is set, we obtain the next mode from spsr. */
- if ((inst & 0x00100000) && (getCurSPSR() & PSR_T)) nextLen = tINSTSZ;
-}
-/*
- ARM: LDR pc instruction
-*/
-LOCAL void armLdrInst(UW inst)
-{
- W rn, roff;
- UW usereg;
-
- /* base register */
- rn = getInstField(0x000F0000, 16);
- usereg = REGBIT(rn);
-
- /* OFF register */
- roff = 0;
- if (inst & 0x02000000) {
- roff = getInstField(0x0000000F, 0);
- usereg |= REGBIT(roff);
- }
-
- /*register to be replaced */
- repReg = getRepReg(usereg);
-
- /* Dest register replacement */
- setRepInst(0x0000F000, 12);
-
- /* base register replacement */
- if (rn == regPC) setRepInst(0x000F0000, 16);
-
- /* offset register replacement */
- if (roff == regPC) setRepInst(0x0000000F, 0);
-}
-/*
- ARM: LDM {pc} instruction
-*/
-LOCAL void armLdmInst(UW inst)
-{
- W i, off;
- UW baddr;
-
- /* memory base address */
- baddr = getRegister(getInstField(0x000F0000, 16));
-
- /* obtain PC address offset */
- off = (inst & 0x01000000) ? REGSZ : 0; /* preindex */
-
- if (inst & 0x00800000) { /* UP */
- for (i = 0; i < regPC; i++) {
- if (inst & REGBIT(i)) off += REGSZ;
- }
- baddr += off;
- } else { /* DOWN */
- baddr -= off;
- }
-
- /* Extract the value set to PC */
- readMem(baddr, &nextPC, REGSZ, 2);
-
- /* if S bit is set, we obtain the next mode from spsr. */
- if ((inst & 0x00400000) && (getCurSPSR() & PSR_T)) nextLen = tINSTSZ;
-}
-/*
- ARM: MRS / MRC instruction rd = pc
-*/
-LOCAL void armMrcsInst(UW inst)
-{
- /* register to be replaced */
- repReg = getRepReg(0);
-
- /* Dest register replacement */
- setRepInst(0x0000F000, 12);
-}
-#if CPU_ARMv6
-/*
- ARM: RFE instruction
-*/
-LOCAL void armRfeInst(UW inst)
-{
- W off;
- UW baddr, saddr, paddr, spsr;
-
- /* memory base address */
- baddr = getRegister(getInstField(0x000F0000, 16));
-
- /* obtain PC address offset */
- off = (inst & 0x01000000) ? REGSZ : 0; /* preindex */
-
- if (inst & 0x00800000) { /* UP */
- paddr = baddr + off;
- saddr = baddr + off + REGSZ;
- } else { /* DOWN */
- paddr = baddr - off - REGSZ;
- saddr = baddr - off;
- }
-
- /* Extract the value set to PC */
- readMem(paddr, &nextPC, REGSZ, 2);
-
- /* obtain the next mode from the saved spsr inside stack. */
- readMem(saddr, &spsr, REGSZ, 2);
- if (spsr & PSR_T) nextLen = tINSTSZ;
-}
-#endif
-/*
- THUMB: Bcond instruction
-*/
-LOCAL void thumbBcondInst(UW inst)
-{
- W cond, off;
-
- cond = getInstField(0x0F00, 8);
-
- /* undefined instruction is not supported */
- if (cond == 14) return;
-
- /* check conditions */
- if (!checkCond(cond)) return;
-
- off = (inst & 0x00FF) << 1;
- if (off >= 0x100) off -= 0x200; /* sign extension */
- nextPC += tINSTSZ + off;
-}
-/*
- THUMB: B instruction
-*/
-LOCAL void thumbBInst(UW inst)
-{
- W off;
-
- off = (inst & 0x07FF) << 1;
- if (off >= 0x800) off -= 0x1000; /* sign extension */
- nextPC += tINSTSZ + off;
-}
-/*
- THUMB: BX / BLX(2) instruction
-*/
-LOCAL void thumbBxInst(UW inst)
-{
- /* BL is not handled during NEXT trace */
- if (inst & 0x0080) { /* BLX(2) */
- if (trcNext) return;
- }
- inst = getInstField(0x0078, 3);
- if (inst == regPC) {
- nextPC += tINSTSZ;
- } else {
- nextPC = getRegister(inst); /* including Hi register */
- }
- if (!(nextPC & 1)) nextLen = aINSTSZ;
-}
-/*
- THUMB: BL / BLX(1) instruction
-*/
-LOCAL void thumbBlInst(UW inst)
-{
- W off;
- UH inst2;
-
- /* BL is not handled during NEXT trace */
- if (trcNext) return;
-
- /* Extract 2nd instruction */
- readMem(nextPC, &inst2, tINSTSZ, 2);
-
- off = (inst & 0x07FF) << 12;
- if (off >= 0x400000) off -= 0x800000; /* sign extension */
- nextPC += tINSTSZ + off + ((inst2 & 0x07FF) << 1);
- if (!(inst2 & 0x1000)) nextLen = aINSTSZ; /* BLX(1) */
-}
-/*
- THUMB: ADD|CMP|MOV Rd/Rn,Rm instruction rd = pc
-*/
-LOCAL void thumbOp6Inst(UW inst)
-{
- UW op, dreg, mreg;
-
- op = inst & 0x0300;
- if (op == 0x0100) return; /* compare instruction */
-
- dreg = getInstField(0x0007, 0);
- if (inst & 0x0080) dreg |= 0x8; /* Hi register */
- if (dreg != regPC) return; /* not PC register */
-
- mreg = getInstField(0x0078, 3); /* including Hi register */
- nextPC = getRegister(mreg) & ~(tINSTSZ - 1);
-
- /* calculate PC */
- if (op == 0x0000) nextPC += getRegister(dreg); /* ADD */
-}
-/*
- THUMB: POP instruction pc
-*/
-LOCAL void thumbPopInst(UW inst)
-{
- W i;
- UW sp;
-
- sp = getRegister(regSP);
- for (i = 0; i < 8; i++) {
- if (inst & REGBIT(i)) sp += REGSZ;
- }
- /* extract PC */
- readMem(sp, &nextPC, REGSZ, 2);
-}
-
-/* Arm instruction decode table */
-typedef struct {
- UW mask; /* mask */
- UW code; /* code */
- void (*calcNextPC)(UW inst); /* calculate PC */
-} INST_T;
-
-LOCAL const INST_T instArm[] = {
- { 0xFFFFFFFF, 0xE1A00000, noBranch}, /* NOP */
- { 0xFFF000F0, 0xE1200070, noBranch}, /* BKPT(ARM5T) */
- { 0x0FFFFFF0, 0x012FFF10, armBxInst}, /* BX */
- { 0xFE000000, 0xFA000000, armBInst}, /* BLX(1)(ARM5T) */
- { 0x0FF000F0, 0x01200030, armBxInst}, /* BLX(2)(ARM5T) */
- { 0x0E000000, 0x0A000000, armBInst}, /* B,BL */
- { 0x0F000000, 0x0F000000, noBranch}, /* SWI */
- { 0x0C10F000, 0x0410F000, armLdrInst}, /* LDR pc */
- { 0x0E108000, 0x08108000, armLdmInst}, /* LDM {pc} */
-/* { 0x0F000010, 0x0E000000, noBranch}, */ /* CDP */
-/* { 0x0E000000, 0x0C000000, noBranch}, */ /* LDC/STC */
- { 0x0F10F010, 0x0E10F010, armMrcsInst}, /* MRC pc */
- { 0x0FBFFFFF, 0x010FF000, armMrcsInst}, /* MRS pc */
-/* { 0x0F0000F0, 0x00000090, noBranch},*/ /* MULL */
- { 0x0E000090, 0x00000090, noBranch}, /* LDR/STR Half/SByte */
-/* { 0x0DB0F000, 0x0120F000, noBranch},*/ /* MSR */
-/* { 0x0FB00FF0, 0x01000090, noBranch},*/ /* SWP */
- { 0x0C00F000, 0x0000F000, armOpInst}, /* ADD/SUB.. rd = pc */
-#if CPU_ARMv6
- { 0xFE50FFFF, 0xF8100A00, armRfeInst}, /* RFE(ARMv6) */
-#endif
- { 0 }
-};
-
-/* Thumb instruction decode table */
-LOCAL const INST_T instThumb[] = {
- /* { 0xF801, 0xE800, thumbBlInst}, // BLX(1)(ARM5T) 2Nd Inst */
- { 0xFF00, 0xBE00, noBranch}, /* BKPT(ARM5T) */
- { 0xFFFF, 0x46C0, noBranch}, /* NOP */
- { 0xFF00, 0xDF00, noBranch}, /* SWI */
- { 0xF800, 0xE000, thumbBInst}, /* B <label> */
- { 0xF000, 0xD000, thumbBcondInst},/* B<cond> <label> */
- { 0xF000, 0xF000, thumbBlInst}, /* BL,BLX(1)(ARM5T) */
- { 0xFF80, 0x4780, thumbBxInst}, /* BLX(2)(ARM5T) */
- { 0xFF00, 0x4700, thumbBxInst}, /* BX */
-#if 0
- { 0xFC00, 0x1800, noBranch}, /* OP(1)ADD|SUB Rd,Rn,Rm */
- { 0xFC00, 0x1C00, noBranch}, /* OP(2)ADD|SUB Rd,Rn,#imm3 */
- { 0xE000, 0x2000, noBranch}, /* OP(3)<OP> Rd/Rn,#imm8 */
- { 0xE000, 0x0000, noBranch}, /* OP(4)LSL|LSR|ASR Rd, Rn, Rn,#shift */
- { 0xFC00, 0x4000, noBranch}, /* OP(5)<OP> Rd/Rn,Rm/Rs */
-#endif
- { 0xFC00, 0x4400, thumbOp6Inst}, /* OP(6)ADD|CMP|MOV Rd/Rn,Rm */
-#if 0
- { 0xF000, 0xA000, noBranch}, /* OP(7)ADD Rd,SP|PC,#imm8 */
- { 0xFF00, 0xB000, noBranch}, /* OP(8)ADD|SUB SP,SP,#imm7 */
- { 0xE000, 0x6000, noBranch}, /* LS(1)LDR|STR(B) Rd,[Rn,#off5] */
- { 0xF000, 0x8000, noBranch}, /* LS(2)LDRH|STRH Rd,[Rn,#off5] */
- { 0xF000, 0x5000, noBranch}, /* LS(3)LDR|STR(S){H|B} Rd,[Rn,Rm] */
- { 0xF800, 0x4800, noBranch}, /* LS(4)LDR Rd,[PC,#off8] */
- { 0xF000, 0x9000, noBranch}, /* LS(5)LDR|STR Rd,[SP,#off8] */
- { 0xF000, 0xC000, noBranch}, /* LDMIA|STMIA Rn!,{<reg list>} */
-#endif
- { 0xFD00, 0xBD00, thumbPopInst}, /* POP {<reg list,PC}>} */
- { 0 }
-};
-/*
- Obtain the next step address
-*/
-EXPORT W getStepAddr(UW pc, UW cpsr, W mode, UW* npc, UW *rep)
-{
- W len;
- UW inst;
- INST_T *tab;
-
- /* set mode */
- len = (cpsr & PSR_T) ? tINSTSZ : aINSTSZ;
- curCPSR = cpsr; /* cpsr */
- repReg = 0; /* register to replace */
- repInst = 0; /* instruction to replace */
- nextPC = pc + len; /* the next PC value for non-branching instruction */
- nextLen = len; /* size of the next instruction */
- trcNext = mode; /* NEXT trace */
-
- /* extract op code */
- if (readMem(pc, &inst, len, 2) != len) goto EXIT;
- repInst = inst; /* instruction to replace */
-
- if (len == 4) { /* ARM instruction */
- /* check the conditional execution */
- if (!checkCond(getInstField(0xF0000000, 28))) goto EXIT;
- tab = (INST_T*)instArm;
- } else { /* THUMB instruction */
- tab = (INST_T*)instThumb;
- inst &= 0xFFFF;
- }
-
- /* search instruction and calculate next PC */
- for ( ; tab->mask != 0; tab++) {
- if ((inst & tab->mask) == tab->code) {
- (*(tab->calcNextPC))(inst);
- break;
- }
- }
-EXIT:
- *npc = nextPC & ~(nextLen - 1);
- *rep = repInst;
- return nextLen | (repReg << 4);
-}
diff --git a/tkernel_source/monitor/cmdsvc/src/boot.c b/tkernel_source/monitor/cmdsvc/src/boot.c
deleted file mode 100644
index 0e182a3..0000000
--- a/tkernel_source/monitor/cmdsvc/src/boot.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * boot.c
- *
- * boot processing
- */
-
-#include "cmdsvc.h"
-
-/*
- * boot information
- * Information passed to primary boot loader (PBOOT).
- * This address (&bootinfo) is passed to the primary boot loader and is directly referenced.
- */
-LOCAL BootInfo bootInfo;
-
-/*
- * Loading of the primary bootloader (PBOOT).
- * return value boot partition number
- */
-LOCAL W loadPBoot( const UB *devnm, DISKCB **dcb_p )
-{
- W retry = 2;
- W pno;
- DISKCB *dcb;
- ER err;
-
- while ( --retry >= 0 ) {
-
- /* opening of a disk device */
- pno = openDisk(devnm, &dcb);
- if ( pno < E_OK ) {
- err = pno;
- if ( err == E_IO ) continue; /* retry */
- return err;
- }
-
- /* If there is no partition specification in the device name, we assume the boot partition. */
- if ( pno == 0 ) pno = dcb->boot;
-
- /* read the boot block inside the target partiion */
- err = (*dcb->rwdisk)(dcb, dcb->part[pno].sblk, 1,
- PBootAddr, FALSE);
- if ( err < E_OK ) {
- if ( err == E_IO ) continue; /* retry */
- return err;
- }
-
- /* check the signature in the boot block */
- if ( *(UH*)(PBootAddr + 510) != BootSignature ) return E_BOOT;
-
- *dcb_p = dcb;
- return pno;
- }
-
- return E_IO;
-}
-
-/*
- * disk boot
- * devnm device name (possibly with the partition number)
- * if it is NULL, the standard search order is used to look for a bootable device.
- * return value error code
- */
-EXPORT ER bootDisk( const UB *devnm )
-{
- DISKCB *dcb;
- W pno, i, c;
- ER err;
-
- if ( devnm != NULL ) {
- /* boot from the specified device */
- pno = loadPBoot(devnm, &dcb);
- if ( pno < E_OK ) return pno;
- } else {
- /* Boot using the standard boot order */
- pno = E_BOOT;
- for ( i = 0;; i++ ) {
- devnm = bootDevice(i);
- if ( devnm == NULL ) break; /* end is seen */
-
- pno = loadPBoot(devnm, &dcb);
- if ( pno >= 0 ) break;
- }
- }
- if ( pno >= 0 ) {
- /* Length of the device name without the partition number */
- i = strlen(devnm);
- c = devnm[i - 1];
- if ( i >= 2 && c >= '0' && c <= '3' ) --i;
-
- /* Set boot information */
- strncpy(bootInfo.devnm, devnm, L_DEVNM);
- bootInfo.devnm[i] = '\0'; /* erase partition number */
- bootInfo.part = pno - 1;
- bootInfo.start = dcb->part[pno].sblk;
- bootInfo.secsz = dcb->blksz;
-
- /* prepare for primary boot execution */
- setUpBoot(PBootAddr, &bootInfo);
-
- } else {
- /* if boot from disk fails
- try invoking ROM kernel */
- err = bootROM();
- if ( err < E_OK ) {
- if ( err != E_ABORT ) err = pno;
- return err;
- }
- }
-
- return E_OK;
-}
diff --git a/tkernel_source/monitor/cmdsvc/src/cmdsvc.h b/tkernel_source/monitor/cmdsvc/src/cmdsvc.h
deleted file mode 100644
index e10e236..0000000
--- a/tkernel_source/monitor/cmdsvc/src/cmdsvc.h
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by T-Engine Forum at 2013/03/01.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * cmdsvc.h
- *
- * T-Monitor command / SVC common processing definitions
- */
-
-#include <tmonitor.h>
-#include <tm/tmonitor.h>
-
-#if CPU_ARMv6
-# include "armv6/cpudep.h"
-#endif
-
-/* ======================================================================== */
-/*
- * Hardware-independent
- */
-
-#define L_LINE 256 /* number of characters per line */
-IMPORT UB lineBuf[L_LINE]; /* line buffer */
-
-#define WRKBUF_SZ 1024 /* must be larger than or equal to 1024 */
-IMPORT UB wrkBuf[WRKBUF_SZ]; /* work buffer for various operations */
-
-#define L_BPCMD 80 /* breakpooint command length */
-
-IMPORT W errinfo; /* error information */
-
-/*
- * display boot message
- */
-IMPORT void dispTitle( void );
-
-/*
- * command execution
- * cmd command string
- * if it is NULL, we are wainting for command input
- * fin = 0 : execute cmd and then wait for command input
- * > 0 : execute cmd and return
- * < 0 : execute cmd and return (ignore execution such as GO,STEP, etc.)
- * if cmd = NULL, fin is ignored. (equivalent to fin = 0)
- */
-IMPORT void procCommand( UB *cmd, W fin );
-
-/*
- * loading from serial line
- * proto [P_XMODEM] | [P_SFORM] (other protocols are ignored)
- * P_XMODEM XMODEM
- * not specified no control sequence
- * P_SFORM S-Record format
- * not specficied memory image (binary data)
- * addr load address
- * In the case of P_SFORM, the initial ooad address is set to addr.
- * Loading is done with the above adjustment. If addr = 0, adjustment is not madem, but
- * load it to data address.
- * range valid load range
- * range[0] start address of the valid load range
- * range[1] end address of the valid load range
- * range[2] load offset
- * load offset is valid only when P_SFORM is used and addr = 0.
- * Its value is the sum of the load address added with the range[2] offset value.
- * This is where loading takes place.
- * range[0] and range[1] will return the final starting and loading address after the loading.
- *
- * if range = NULL, below is assumed.
- * range[0] = 0x00000000
- * range[1] = 0xffffffff
- * range[2] = 0
- * return value error code
- */
-IMPORT ER doLoading( W proto, UW addr, UW range[3] );
-
-/* load option (LOAD commands, etc.) */
-#define P_XMODEM 0x20 /* XMODEM */
-#define P_TEXT 0x10 /* no protocol */
-#define P_SFORM 0x02 /* S-Format */
-#define P_MEMIMG 0x01 /* memory image */
-
-/*
- * Flash ROM disk write
- * blksz = 0 set up
- * Prepare writing to ROM disk and return the maximum ROM size
- * in sz (bytes).
- * Return the address to which the data to be written to ROM disk should be loaded.
- * blksz > 0 written
- * blksz ROM disk block size
- * sz number of written blocks
- * return value error code
- */
-IMPORT W writeRda( UW blksz, UW *sz );
-
-/*
- * disk boot
- * devnm device name (possibly with the partition number)
- * if it is NULL, the standard search order is used to look for a bootable device.
- * return value error code
- */
-IMPORT ER bootDisk( const UB *devnm );
-
-/*
- * monitor service call
- * fno function code
- * p1-p4 parameters
- * return value return value of the service call
- */
-IMPORT W procSVC( W fno, W p1, W p2, W p3, W p4 );
-
-/* ======================================================================== */
-/*
- * Hardware-dependent
- */
-
-/*
- * disassember
- * saddr pass the address where the instruction to be disassembled is.
- * returns the adjusted address that points at the start of the instruction.
- * naddr returns the address of the next instruction. (if it is NULL, value is not returned)
- * str the buffer to store the disassembled instruction string (must be long enough)
- * return value error code
- */
-IMPORT ER disAssemble( UW *saddr, UW *naddr, UB *str );
-
-/*
- * examine and obtain the breakpoint attribute
- * examine the breakpoint attribute string specified by `name', and if it is legal,
- * return its attribute code as return value.
- * In the case of illegal attribute string, return an error (E_BPATR).
- */
-IMPORT W getBreakAtr( UB *name );
-
-/*
- * set breakpoint
- * addr address where breakpoint is set
- * atr breakpoint attribute
- * cmd command that is to be executed at the breakpoint (valid only when cmdlen > 0)
- * cmdlen cmd length
- * return value error code
- */
-IMPORT ER setBreak( UW addr, W atr, UB *cmd, W cmdlen );
-
-/*
- * release breakpoint
- * addr address where breakpoint is to be released
- * if it is 0, then release all breakpoints
- * return value error code
- */
-IMPORT ER clearBreak( UW addr );
-
-/*
- * list all breakpoints
- */
-IMPORT void dspBreak( void );
-
-/*
- * release breakpoint temporarily (monitor entry)
- * return value if the current PC is not a breakpoint, returns 0.
- * if it is a breakpoint, returns non-zero value.
- */
-IMPORT W resetBreak( UW vec );
-
-/*
- * set breakpoints (monitor exit)
- */
-IMPORT void setupBreak( void );
-
-/*
- * forcibly stop trace
- */
-IMPORT void stopTrace( void );
-
-/*
- * trace or normal execution
- * trace 0 : GO command
- * 1 : STEP command
- * 2 : NEXT command
- * pc execution start address
- * par in the case of GO
- * tempoary breakpoint address (if 0, then no temporary breakpoionts)
- * in the case of STEP/NEXT
- * number of steps (0 is regarded as 1)
- * return value error code
- */
-IMPORT ER goTrace( W trace, UW pc, UW par );
-
-/*
- * break processing
- * bpflg return the value returned by resetBreak() as is.
- * cmd return the command to be executed at the breakpoint.
- * return value 0 : return monitor immediately and contineu executing the user program.
- * 1 : enter command processing of the monitor and execute cmd.
- */
-IMPORT W procBreak( W bpflg, UB **cmd );
-
-/*
- * search register
- * Return the register number (0 and upward) for the register name `name'.
- * grp 0 : exclude group names from the search.
- * 1 : include the group names in the search/
- * name is L_REGNM bytes long, and if the result is not long enough, the remaining part is filled with space.
- * L_REGNM is machine-dependent, but should be less than or equal to L_SYMBOL.
- * if the name is invalid (not found), return -1.
- */
-IMPORT W searchRegister( UB *name, W grp );
-
-/*
- * obtain / set register value
- * regno register number
- * val value to set
- * return value obtained set value(if there is an error, 0).
- * * set : error code
- */
-IMPORT UW getRegister( W regno );
-IMPORT ER setRegister( W regno, UW val );
-
-/*
- * display register value
- * display the register or register group specified by `regno'.
- * if regno < 0, thendisplay the default register group.
- */
-IMPORT void dispRegister( W regno );
-
-/*
- * obtain / set the current PC register
- */
-IMPORT UW getCurPC( void );
-IMPORT void setCurPC( UW val );
-
-/*
- * prepare to execute the boot program
- * pass boot info to a boot program and start it from the address, `start'.
- *
- * It means that we don't execute ROM kernel immediately, but we prepare so that upon return from the ordinary monitor,
- * it gets executed.
- */
-IMPORT void setUpBoot( void *start, BootInfo *bootinfo );
-
-/*
- * Prepare ROM kernel execution
- * It means that we don't execute ROM kernel immediately, but we prepare so that upon return from the ordinary monitor,
- * it gets executed.
- */
-IMPORT ER bootROM( void );
-
-/*
- * Initialize address check data (executed upon monitor entry)
- */
-IMPORT void initChkAddr( void );
-
-/*
- * validate memory address
- * check whether access to area starting from logical address, addr, and has the length of len bytes,
- * return the corresponding physical address of addr in pa.
- * rw = 0 for read / rw = 1 for write is checked for the access right check.
- * Returns the length of accessible bytes for a consecutive region that starts from addr.
- * if addr is inaccessible, then the size for the accesible region is 0.
- * So, 0 is returned. In this case, error code is set to a global variable errinfo.
- * the address returned to pa is machine-depdenent, and may not be a physical address always.
- */
-IMPORT W chkMemAddr( UW addr, UW *pa, W len, W rw );
-
-/*
- * validate I/O address
- * heck whether we can access a region from an I/O address (logical address in the case of memory mapped I/O), with the len bytes length,
- * the I/O address (physical address if memory mapped I/O is used) is returned
- * in pa.
- * Returns the length of accessible bytes for a consecutive region that starts from addr.
- * if addr is inaccessible, then the size for the accesible region is 0.
- * So, 0 is returned.
- * * the address returned to pa is machine-depdenent, and, in the case of memory mapped I/O.
- * may not be a physical address always. if memory mapped I/O is not used,
- * generally speaking, pa will return addr unmodiifed.
- */
-IMPORT W chkIOAddr( UW addr, UW *pa, W len );
-
-/*
- * Validate PC address
- * If addr is valid then return 0, otherwise return -1.
- */
-IMPORT W invalidPC( UW addr );
-
-/*
- * Check whehter kill command can be executed
- * If it can be executed, return 0, and if not, return -1.
- */
-IMPORT W isKillValid( void );
-
-/*
- * calling an external program
- */
-IMPORT W callExtProg( FP entry );
-
-/* ------------------------------------------------------------------------ */
diff --git a/tkernel_source/monitor/cmdsvc/src/command.c b/tkernel_source/monitor/cmdsvc/src/command.c
deleted file mode 100644
index f8b2ffa..0000000
--- a/tkernel_source/monitor/cmdsvc/src/command.c
+++ /dev/null
@@ -1,1274 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by T-Engine Forum at 2013/03/04.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * command.c
- *
- * command processing
- */
-
-#include "cmdsvc.h"
-#include "help.h"
-#include <tk/dbgspt.h>
-
-#define DEF_MEM_SIZE 64 /* default memory dump size */
-#define DEF_DA_STEP 16 /* default disassbmle size */
-#define MAX_DSP_CNT 64 /* maximum cut off count for display */
-#define MAX_RANGE 0x1000000 /* maximum range (16 MB) */
-#define IMPLICIT_SIZE 0x1000 /* implicit size specification */
-
-EXPORT UB lineBuf[L_LINE]; /* line buffer */
-EXPORT W killProcReq; /* request to forcibly kill a process */
-
-#define L_SYMBOL 23 /* effective symbol length */
-#define SETDT_SZ 128 /* data size */
-
-#define CMD_FINISH (9999) /* command end specification */
-
-EXPORT W errinfo; /* error information */
-LOCAL W errcode; /* error code */
-
-LOCAL UW dAddr; /* D address command */
-LOCAL UW mAddr; /* M command address */
-LOCAL UW daAddr; /* DA command address */
-LOCAL UW cAddr; /* the current start address */
-LOCAL W cLen; /* the current memory byte length */
-
-LOCAL W token; /* token type */
-LOCAL UW tokenVal; /* numeric token / register number */
-LOCAL UB *tokenStr; /* character string / symbol item pointer */
-LOCAL W tokenLen; /* character string / symbol item length */
-LOCAL UB tokenSym[L_SYMBOL + 1]; /* symbol item string(capital letters) */
-LOCAL UB symExt[2]; /* extended symbol letters */
-LOCAL UB *lptr; /* line pointer */
-
-#define PROMPT "TM> " /* prompt */
-
-/* item type */
-#define tEOL 0x00 /* line end */
-#define tEOC 0x01 /* end of command */
-#define tDLM 0x02 /* delimiter */
-#define tSIZ 0x11 /* size specification */
-#define tOPADD 0x12 /* + operator */
-#define tOPSUB 0x13 /* - operator */
-#define tOPMUL 0x14 /* * operator */
-#define tOPDIV 0x15 /* / operator */
-#define tOPIND 0x16 /* & operator */
-#define tEOD 0x17 /* end of data */
-#define tUP 0x18 /* previous data */
-#define tSYM 0x20 /* symbol */
-#define tNUM 0x21 /* numeric value */
-#define tSTR 0x22 /* character string */
-#define tERRR 0x100 /* error */
-#define tERCH 0x100 /* error: illegal character */
-#define tERNUM 0x101 /* error: illegal numeric form */
-
-/* character classficiation */
-#define isSpace(c) ((c) && (c) <= ' ')
-#define isNum(c) ((c) >= '0' && (c) <= '9')
-#define isAlpha(c) ( ((c) >= 'A' && (c) <= 'Z') ||\
- ((c) >= 'a' && (c) <= 'z') )
-#define isAlNum(c) (isNum(c) || isAlpha(c))
-#define isSym(c) (isAlpha(c) || c == '$' || c == '_' ||\
- c == '?' || c == '@')
-#define isExtSym(c) ((c) && ((c) == symExt[0] || (c) == symExt[1]))
-
-/* alignment adjustment */
-#define ALIGN_L(v, unit) ((v) & ~((unit) - 1))
-#define ALIGN_U(v, unit) (((v) + (unit) - 1) & ~((unit) - 1))
-
-/* error return */
-#define return_er(er) return (errcode = er)
-#define er_return(er) {errcode = er; return;}
-#define oer_return(er) {if ((er) == E_NOEXS)\
- errcode = E_ONOEXS;\
- else errcode = er;\
- return;}
-
-#define DB16 0x00000 /* default base number */
-#define DB10 0x10000
-
-/*
- display error message
-*/
-LOCAL void dspError(void)
-{
- UB *mp = NULL;
-
- if (token >= tERRR) { /* priortize the item error */
- switch(token) {
- case tERCH: mp = "Illegal Character"; break;
- case tERNUM: mp = "Illegal Number Format"; break;
- }
- } else {
- if (errinfo < 0) errcode = errinfo;
- switch(errcode) {
- case E_MACV: mp = "Illegal Address"; break;
- case E_ROM: mp = "ROM Address"; break;
- case E_LESS: if (token <= tEOC)
- {mp = "Less Parameter"; break;}
- case E_PAR: mp = "Illegal Parameter"; break;
- case E_ID: mp = "Illegal ID Number"; break;
- case E_CTX: mp = "Context Error"; break;
- case E_LIMIT: mp = "Too Many Parameters"; break;
- case E_OBJ: mp = "Abnormal Object Status"; break;
- case E_NOSPT: mp = "Not Supported"; break;
- case E_NOEXS: mp = "Unknown Device"; break;
- case E_IO: mp = "I/O Error"; break;
- case E_RONLY: mp = "Read Only"; break;
- case E_NOMDA: mp = "No Media"; break;
- case E_PROTECT: mp = "Write Protected"; break;
-
- case E_CMD: mp = "Unknown Command"; break;
- case E_RANGE: mp = "Illegal Address Range"; break;
- case E_EMPTY: mp = "Empty String"; break;
- case E_ILREG: mp = "Unknown Register Name"; break;
- case E_PC: mp = "Illegal PC Value"; break;
- case E_BOOT: mp = "No Bootable Disk"; break;
-
- case E_PROTO: mp = "Unknown Load Protocol"; break;
- case E_NOADDR: mp = "No Load Address"; break;
- case E_LOADFMT: mp = "Illegal S-Format Record"; break;
- case E_LOAD: mp = "Loading Error"; break;
- case E_CANCEL: mp = "Loading Cancelled"; break;
- case E_XMODEM: mp = "XMODEM Protocol Error"; break;
-
- case E_BPATR: mp = "Unknown Break Point Attribute"; break;
- case E_BPBAD: mp = "Illegal Break Point"; break;
- case E_BPDSLT: mp = "Break Point at Delayed Slot"; break;
- case E_BPROM: mp = "Break Point in ROM"; break;
- case E_BPCMD: mp = "Too Long Break Point Command"; break;
- case E_BPUDF: mp = "Undefined Break Point"; break;
- case E_SBPOVR: mp = "Too Many Software Break Points"; break;
- case E_HBPOVR: mp = "Too Many Hardware Break Points"; break;
-
- case E_ONOEXS: mp = "Noexistent Object"; break;
- }
- }
- if (mp) {
- DSP_F3(S,"ERR: ", S,mp, CH,'\n');
- } else {
- DSP_F3(S,"ERR: [", 08X,errcode, S,"]\n");
- }
-}
-/*
- input of a line
-*/
-LOCAL W getLine(UB *msg)
-{
- if (msg) DSP_S(msg); /* display prompt */
- memset(lineBuf, 0, sizeof(lineBuf)); /* clear buffer */
- return getString(lptr = lineBuf); /* input a line and initialize the line pointer */
-}
-/*
- skip spaces
-*/
-LOCAL void skipSpace(void)
-{
- while (isSpace(*lptr)) lptr++;
-}
-/*
- extract hexadecimal value
-*/
-LOCAL W getHexVal(UB **ptr)
-{
- W c;
- UW v;
- UB *p;
-
- p = *ptr;
- for (v = 0; ((c = *p) >= '0' && c <= '9') ||
- (c >= 'A' && c <= 'F') || (c >= 'a' && c <= 'f'); p++) {
- if (v >= 0x10000000) break; /* overflow */
- v <<= 4;
- v += (c >= 'a' ? (c - 'a' + 10) :
- (c >= 'A' ? (c - 'A' + 10) : ( c - '0')));
- }
- *ptr = p;
- return v;
-}
-/*
- extract item
-
- numerical constant: H'<digit> 0x<digit> hexadecimal
- D'<digital> decimal (base 10)
- Q'<digit> octal (base 8)
- B'<digit> binary(base 2)
- <digit> '<digit> hexadecimal(base 16)
- character constant: "<character>.." only ASCII characters are allowed
- symbol: <letter$_><letter$_digit>..
- operator: + addition
- - subtraction
- * multiplication
- / division
- & indirect reference
- separator: ,
- special symbol: ; EndOfCommand(same as EndOfLine)
- # size specificication
- . end of data
- ^ UP (return to previous line)
-*/
-LOCAL W getToken(W defbase)
-{
- W c, i, base;
-
- tokenVal = 0;
- skipSpace();
- if ((c = *lptr) == 0) {i = tEOL; goto EXIT;}
- lptr++;
-
- if (c == ';') {i = tEOC; goto EXIT;}
- if (c == ',') {i = tDLM; goto EXIT;}
- if (c == '#') {i = tSIZ; goto EXIT;}
- if (c == '.') {i = tEOD; goto EXIT;}
- if (c == '^') {i = tUP; goto EXIT;}
- if (c == '+') {i = tOPADD; goto EXIT;}
- if (c == '-') {i = tOPSUB; goto EXIT;}
- if (c == '*') {i = tOPMUL; goto EXIT;}
- if (c == '/') {i = tOPDIV; goto EXIT;}
- if (c == '&') {i = tOPIND; goto EXIT;}
-
- if (c == '"') { /* character string */
- for (tokenStr = lptr; (c = *lptr) && c != '"'; lptr++);
- tokenLen = lptr - tokenStr;
- if (c) lptr++;
- i = tSTR;
- goto EXIT;
- }
-
- if (*lptr == '\'') { /* number with prefix */
- if (c == 'Q' || c == 'q') {base = 8; goto NUMVAL;}
- if (c == 'B' || c == 'b') {base = 2; goto NUMVAL;}
- if (c == 'D' || c == 'd') {base = 10;
-NUMVAL:
- while ((c = *++lptr) >= '0' && c < base + '0')
- tokenVal = tokenVal * base + c - '0';
- goto NUMEXIT;
- }
- if (c == 'H' || c == 'h') goto HEXVAL;
- }
-
- if (isNum(c)) { /* simple number */
- if (c != '0' || (*lptr != 'x' && *lptr != 'X')) {
- lptr -= 2;
- if (defbase == DB10) {base = 10; goto NUMVAL;}
- }
- goto HEXVAL;
- }
-
- if (c == '\'') { /* hexadecimal number */
- lptr--;
-HEXVAL:
- lptr++;
- tokenVal = getHexVal(&lptr);
- c = *lptr;
-NUMEXIT:
- /* if the end of the numeric value is alphanumeric letter, then it is regarded as illegal numeric format. */
- i = (isSym(c) || isNum(c)) ? tERNUM : tNUM;
- goto EXIT;
- }
-
- if (isSym(c)) { /* symbol */
- tokenStr = --lptr;
- for (i = 0; isSym(c) || isNum(c) || isExtSym(c); c = *++lptr) {
- /* set to tokenSym[] in capital letters */
- if (i < L_SYMBOL) {
- if (c >= 'a' && c <= 'z') c -= 'a' - 'A';
- tokenSym[i++] = c;
- }
- }
- /* Fill the rest of tokenSym[] with space */
- while (i < L_SYMBOL) tokenSym[i++] = ' ';
-
- tokenLen = lptr - tokenStr;
- i = tSYM;
- goto EXIT;
- }
- /* other: illegal character error */
- i = tERCH;
-EXIT:
- return token = i;
-}
-/*
- check for end of command
-*/
-LOCAL W isnotEOC(void)
-{
- if (token <= tEOC) return 0;
- return_er(E_PAR);
-}
-/*
- check for separator (1)
-*/
-LOCAL W isDLM(void)
-{
- if (token == tDLM) {getToken(0); return 1;}
- return 0;
-}
-/*
- check for separator (2)
-*/
-LOCAL W isnotDLM(void)
-{
- if (isDLM()) return 0;
- return_er(E_LESS);
-}
-/*
- obtain numeric parameter (with performing + - * / operations)
-
- [+|-] {symbol|numeric value} [{+|-|* |/} {symbol|numeric value}].. {,|EOL}
-*/
-LOCAL W getNumber(W defbase, W *val)
-{
- W op, v;
- UB *p;
-
- /* process leading + and - */
- if ((op = token) == tOPADD || op == tOPSUB) getToken(defbase);
-
- for (*val = 0; ;) {
- if (token == tSYM) { /* register name */
- if ((v = searchRegister(tokenSym, 0)) >= 0) {
- tokenVal = getRegister(v);
- } else { /* hexadecimal value */
- if (tokenSym[L_SYMBOL - 1] != ' ') break;
- p = tokenSym;
- tokenVal = getHexVal(&p);
- if (*p != ' ') break;
- }
- } else if (token != tNUM) {
- return_er(E_LESS); /* non-numeric value */
- }
-
- /* Performing + - * / operations */
- if (op == tOPADD) *val += tokenVal;
- else if (op == tOPSUB) *val -= tokenVal;
- else if (op == tOPMUL) *val *= tokenVal;
- else if (op == tOPDIV) *val /= tokenVal;
- else *val = tokenVal;
-
- /* & operation */
- while (getToken(defbase) == tOPIND) {
- if (readMem(*val, &v, 4, 4) != 4) return_er(E_MACV);
- *val = v;
- }
-
- /* extract the next item: if the next item is among "+ - * /" then continue processing */
- if (token < tOPADD || token > tOPDIV) break;
- op = token;
- getToken(defbase);
- }
- if (token > tDLM) return_er(E_LESS);
- return 0;
-}
-/*
- obtain address range parameter
-
- [start_addr][,{end_addr|#count}]
- cAddr = start_addr
- cLen = count
-
- flg 0x01 start_addr cannot be omitted
- 0x02 end_addr|#count (cannot be omitted)
-*/
-LOCAL W getAddrRange(W unit, W flg, W defsz)
-{
- W sizeflg;
-
- /* start address */
- if (token > tDLM) {
- if (getNumber(0, &cAddr)) return E_LESS;
- } else {
- if (flg & 0x01) return_er(E_LESS); /* cannot be omitted */
- }
-
- /* align start address */
- cAddr = ALIGN_L(cAddr, unit);
-
- /* end address */
- cLen = defsz;
- if (token == tDLM) {
- sizeflg = 0;
- if (getToken(0) == tSIZ) {
- getToken(0);
- sizeflg++;
- }
- if (getNumber(0, (UW*)&cLen)) return E_LESS;
- if (sizeflg == 0) { /* end address: up to "+ size" */
- if ((UW)cLen >= cAddr || (UW)cLen >= IMPLICIT_SIZE)
- /* truncate (using the size as unit) */
- cLen = ((W)((UW)cLen - cAddr) + unit) / unit;
- }
- cLen *= unit;
- } else {
- if (flg & 0x02) return_er(E_LESS); /* cannot be omitted */
- }
-
- /* validate address range */
- if (cLen <= 0 || cLen > MAX_RANGE) return_er(E_RANGE);
- if (((cLen + cAddr - 1) ^ cAddr) & 0x80000000) {
- cLen = (0x80000000 - (cAddr & 0x7fffffff)) / unit;
- if ((cLen *= unit) == 0) return_er(E_RANGE);
- }
- return 0;
-}
-/*
- extract set data address
-
- {character string | numeric parameter}[, {character string | numeric parameter}]...EOC
-*/
-LOCAL W getSetData(UB *buf, W unit)
-{
- W n, k;
- UW num;
-
- for (n = 0; ;) {
- if (token == tSTR) { /* character string */
- if (tokenLen == 0) return_er(E_EMPTY);
-
- /* Fill with 0 using 'unit' as data unit. */
- k = ALIGN_U(tokenLen, unit);
- if (n + k > SETDT_SZ) return_er(E_LIMIT);
- memcpy(&buf[n], tokenStr, tokenLen);
- n += tokenLen;
- if ((k -= tokenLen) > 0) memset(&buf[n], 0, k);
- n += k;
- getToken(0);
- } else { /* numeric parameter */
- if (n + unit > SETDT_SZ) return_er(E_LIMIT);
- if (getNumber(0, &num)) return E_LESS;
- switch (unit) {
- case 4: *((UW*)&buf[n]) = (UW)num; break;
- case 2: *((UH*)&buf[n]) = (UH)num; break;
- default: buf[n] = (UB)num;
- }
- n += unit;
- }
- if (token <= tEOC) break;
- if (isnotDLM()) return E_LESS;
- }
- if (n == 0) return_er(E_EMPTY);
- return n; /* data length */
-}
-/*
- memory read (with error message)
-*/
-LOCAL W reaMemory(UW addr, void *dt, W len, W unit)
-{
- W n;
-
- if ((n = readMem(addr, dt, len, unit)) == len) return 0;
- DSP_F3(S,"ERR: Memory Read at H'", 08X,(addr+n), CH,'\n');
- return -1;
-}
-/*
- memory write (with error message)
-*/
-LOCAL W wriMemory(UW addr, void *dt, W len, W unit)
-{
- W n;
-
- if ((n = writeMem(addr, dt, len, unit)) == len) return 0;
- DSP_F3(S,"ERR: Memory Write at H'", 08X,(addr+n), CH,'\n');
- return -1;
-}
-/*
- display memory content
-*/
-LOCAL void dspMemory(void *p, W unit)
-{
- switch (unit) {
- case 4: DSP_F2(08X,*((UW*)p), CH,' '); break;
- case 2: DSP_F2(04X,*((UH*)p), CH,' '); break;
- default: DSP_F2(02X,*((UB*)p), CH,' ');
- }
-}
-/*
- memroy dump command processing
-
- D [start_addr][,{end_addr|#data_cnt}]
- DB [start_addr][,{end_addr|#data_cnt}]
- DH [start_addr][,{end_addr|#data_cnt}]
- DW [start_addr][,{end_addr|#data_cnt}]
-*/
-LOCAL void cmdDump(W unit)
-{
- W i, n, k;
- UB *cp, *ep;
-
- /* extract address range */
- cAddr = dAddr;
- if (getAddrRange(unit, 0x00, DEF_MEM_SIZE) || isnotEOC()) return;
-
- /* dump memory content */
- ep = cp = wrkBuf;
- for (dAddr = cAddr, i = 0; i < cLen;) {
- /* display address */
- if ((i % 16) == 0) DSP_F2(08X,dAddr, S,": ");
-
- /* obtain memory content */
- if (cp >= ep) {
- if ((n = cLen - i) > WRKBUF_SZ) n = WRKBUF_SZ;
- k = readMem(dAddr, cp = wrkBuf, n, unit);
- if (n != k) {
- errcode = E_MACV;
- cLen = i + k;
- }
- ep = cp + k;
- }
- /* display memory content */
- if (i < cLen) {
- dspMemory(cp, unit);
- cp += unit;
- dAddr += unit;
- i += unit;
- }
- /* display character */
- if ((n = i % 16) == 0 || i >= cLen) {
- k = 16 - n;
- if (n) { /* move forward to where we start character dump */
- n = k / unit * (unit * 2 + 1);
- while (n-- > 0) DSP_CH(' ');
- }
- k = (i % 16) ? (i % 16) : 16;
- for (cp -= k; cAddr < dAddr; cAddr++) {
- n = *cp++;
- DSP_CH((n >= ' ' && n < 0x7f) ? n : '.');
- }
- DSP_LF;
- }
- if (checkAbort()) {DSP_LF; break;}
- }
-}
-/*
- memory update command processing
-
- M [start_addr][,data]..
- MB [start_addr][,data]..
- MH [start_addr][,data]..
- MW [start_addr][,data]..
-*/
-LOCAL void cmdModify(W unit)
-{
- W n;
- UB buf[4];
- UB svbuf[L_LINE];
- UB *svlptr, svtoken;
- UB dt[SETDT_SZ];
-
- /* start address */
- cAddr = mAddr;
- if (token > tDLM && getNumber(0, &cAddr)) return;
-
- /* align address */
- cAddr = ALIGN_L(cAddr, unit);
-
- if (token <= tEOC) { /* interactive processing */
- /* save command line */
- memcpy(svbuf, lineBuf, L_LINE);
- svlptr = lptr;
- svtoken = token;
-
- for (;;) {
- DSP_F2(08X,cAddr, S,": "); /* display address */
- if (reaMemory(cAddr, buf, unit, unit)) break;
- dspMemory(buf, unit); /* display data */
-
- if (getLine("-> ") < 0) break; /* input set data */
- if (getToken(0) == tEOD) break; /* end of data */
- if (token <= tEOC) cAddr += unit; /* skip */
- else if (token == tUP) cAddr -= unit; /* previous */
- else if ((n = getSetData(dt, unit)) < 0) break;
- else {
- if (wriMemory(cAddr, dt, n, unit)) break;
- cAddr += n;
- }
- }
- /* restore command line */
- memcpy(lineBuf, svbuf, L_LINE);
- lptr = svlptr;
- token = svtoken;
- if (errcode == E_LESS) errcode = E_PAR;
-
- } else if (! isnotDLM()) { /* set data processing */
- if ((n = getSetData(dt, unit)) > 0) {
- if (wriMemory(cAddr, dt, n, unit) == 0) cAddr += n;
- }
- }
- mAddr = cAddr;
-}
-/*
- memory embedding command processing
-
- F start_addr,{end_addr|#data_cnt}[,data]..
- FB start_addr,{end_addr|#data_cnt}[,data]..
- FH start_addr,{end_addr|#data_cnt}[,data]..
- FW start_addr,{end_addr|#data_cnt}[,data]..
-*/
-LOCAL void cmdFill(W unit)
-{
- W n;
- UB dt[SETDT_SZ];
-
- /* extract address range */
- if (getAddrRange(unit, 0x03, DEF_MEM_SIZE)) return;
-
- /* extract set data */
- if (token <= tEOC) {
- memset(dt, 0, sizeof(UW)); /* 0 by default */
- n = unit;
- } else {
- if (isnotDLM()) return;
- if ((n = getSetData(dt, unit)) < 0) return;
- }
-
- /* embed set data into memory */
- if (n == unit) { /* fast processing */
- wriMemory(cAddr, dt, cLen, unit | 0x10);
- } else { /* ordinary mode */
- for (; cLen > 0; cLen -= n, cAddr += n) {
- if (n > cLen) n = cLen;
- if (wriMemory(cAddr, dt, n, unit)) break;
- }
- }
-}
-/*
- memory search command processing
-
- SC start_addr,{end_addr|#data_cnt},search_data..
- SCB start_addr,{end_addr|#data_cnt},search_data..
- SCH start_addr,{end_addr|#data_cnt},search_data..
- SCW start_addr,{end_addr|#data_cnt},search_data..
-*/
-LOCAL void cmdSearch(W unit)
-{
- W n, len, cnt, ofs;
- UB *cp, *ep;
- UB dt[SETDT_SZ];
-
- /* extract address range */
- if (getAddrRange(unit, 0x01, DEF_MEM_SIZE) || isnotDLM()) return;
-
- /* extract search data */
- if ((len = getSetData(dt, unit)) < 0) return;
-
- ep = cp = wrkBuf;
- for (ofs = cnt = 0; ; ) {
- /* obtain memory content */
- if (cp >= ep) {
- if ((n = WRKBUF_SZ - ofs) > cLen) n = cLen;
- if (ofs + n < len) break; /* end */
- if (reaMemory(cAddr, &wrkBuf[ofs], n, unit)) break;
- cAddr += n;
- cLen -= n;
- ep = (cp = wrkBuf) + ofs + n;
- }
- /* check if the leading byte matches */
- for ( ; cp < ep && *cp != dt[0]; cp += unit);
- if ((ofs = ep - cp) < len) {
- /* if enough data is not there, move to the beginning of buffer. */
- if (ofs > 0) memcpy(wrkBuf, ep = cp, ofs);
- continue;
- }
- /* check for the matching of whole data */
- if (memcmp(cp, dt, len) == 0) {
- if (++cnt > MAX_DSP_CNT) {
- DSP_S("..More..\n");
- break;
- }
- DSP_F2(08X,(cAddr - (ep - cp)), S,":\n");
- }
- /* next */
- cp += unit;
- ofs = 0;
- if (checkAbort()) break;
- }
-}
-/*
- memory comparison / move command processing
-
- CMP start_addr,{end_addr|#data_cnt},target_addr
- MOV start_addr,{end_addr|#data_cnt},target_addr
-*/
-LOCAL void cmdCmpMov(W mov)
-{
- UW dst;
- W i, n, cnt;
-#define BFSZ (WRKBUF_SZ / 2)
-
- /* extract address range */
- if (getAddrRange(1, 0x01, DEF_MEM_SIZE) || isnotDLM()) return;
-
- /* transfer / compare target */
- if (getNumber(0, &dst) || isnotEOC()) return;
-
- if (mov) { /* memory transfer */
- for (; (n = cLen) > 0 && checkAbort() == 0;
- cAddr += n, dst += n, cLen -= n) {
- if (n > WRKBUF_SZ) n = WRKBUF_SZ;
- if (reaMemory(cAddr, wrkBuf, n, 1)) break;
- if (wriMemory(dst, wrkBuf, n, 1)) break;
- }
-
- } else { /* memory comparison */
- for (cnt = 0; (n = cLen) > 0 && checkAbort() == 0;
- cAddr += n, dst += n, cLen -= n) {
- if (n > BFSZ) n = BFSZ;
- if (reaMemory(cAddr, wrkBuf, n, 1)) break;
- if (reaMemory(dst, &wrkBuf[BFSZ], n, 1)) break;
- if (memcmp(wrkBuf, &wrkBuf[BFSZ], n) == 0) continue;
- for (i = 0; i < n; i++) {
- if (wrkBuf[i] == wrkBuf[BFSZ + i]) continue;
- if (++cnt > MAX_DSP_CNT) {
- DSP_S("..More..\n");
- cLen = 0; /* terminate */
- break;
- }
- DSP_F4(08X,(cAddr + i), S,": ",
- 02X,wrkBuf[i], S," -> ");
- DSP_F4(08X,(dst + i), S,": ",
- 02X,(wrkBuf[BFSZ + i]), CH,'\n');
- }
- }
- }
-}
-/*
- I/O port input and output command processing
-
- IB/IH/IW port
- OB/OH/OW port, data
-*/
-LOCAL void cmdIO(W unit)
-{
- UW port, data;
- UB *dir;
-
- /* extract port number */
- if (getNumber(0, &port)) return;
-
- if (unit & 0x10) { /* output command */
- if (!isDLM()) er_return(E_LESS);
- if (getNumber(0, &data) || isnotEOC()) return;
- if (writeIO(port, data, unit &= 0x0f) == 0) er_return(E_MACV);
- dir = "<--";
- } else { /* input command */
- if (isnotEOC()) return;
- if (readIO(port, &data, unit) == 0) er_return(E_MACV);
- dir = "-->";
- }
- /* display result */
- DSP_F2(S,"Port ", 08X,port);
- switch (unit) {
- case 4: DSP_F5(S,":W ", S,dir, CH,' ', 08X,(UW)data, CH,'\n');
- break;
- case 2: DSP_F5(S,":H ", S,dir, CH,' ', 04X,(UH)data, CH,'\n');
- break;
- default:DSP_F5(S,":B ", S,dir, CH,' ', 02X,(UB)data, CH,'\n');
- break;
- }
-}
-/*
- disasseble command processing
-
- DA [start_addr][,steps]
-*/
-LOCAL void cmdDisasm(void)
-{
- er_return(E_NOSPT);
-}
-/*
- display / set register command processing
-
- R [register_name[,data]]
-*/
-LOCAL void cmdRegister(void)
-{
- W rno;
- UW num;
-
- if (token <= tEOC) { /* ordinary register dump */
- dispRegister(-1);
-
- } else { /* extract register name */
- if (token != tSYM || (rno = searchRegister(tokenSym, 1)) < 0)
- er_return(E_ILREG);
-
- if (getToken(0) <= tEOC) { /* display register */
- dispRegister(rno);
-
- } else if (!isnotDLM() && !getNumber(0, &num)) { /* set register */
- if (!isnotEOC())
- er_return(setRegister(rno, num));
- }
-
-
- }
-}
-/*
- execute / trace command processing
-
- G [start_addr][,end_addr]
- S/N [start_addr][,steps]
-*/
-LOCAL void cmdGoTrace(W trace)
-{
- UW pc, par;
-
- /* extract execution address */
- pc = getCurPC();
- if (token > tDLM && getNumber(0, &pc)) return;
- if (invalidPC(pc)) er_return(E_PC);
-
- /* extract end address or number of steps */
- par = 0;
- if (isDLM()) {
- if (getNumber(0, &par)) return;
- if (trace == 0 && invalidPC(par)) er_return(E_MACV);
- }
- if (isnotEOC()) return;
-
- if (trace && par <= 0) par = 1; /* number of steps */
-
- /*execute program */
- errcode = goTrace(trace, pc, par);
- if (errcode >= E_OK) errcode = CMD_FINISH; /*command process termination */
-}
-/*
- display / set breakpoint command processing
-
- B [break_addr[,break_attr][,commands]]
-*/
-LOCAL void cmdBreak( void )
-{
- UW addr;
- W atr, cmdlen;
- UB *cmd;
-
- if (token <= tEOC) { /* display breakpoint */
- dspBreak();
- return;
- }
-
- /* extract breakpoint address */
- if (getNumber(0, &addr)) return;
-
- /* extract break attribute and command */
- atr = cmdlen = 0;
- cmd = NULL;
- while (token == tDLM) {
- /* "+:" are handled as symbols */
- symExt[0] = '+'; symExt[1] = ':';
- getToken(0);
- symExt[0] = symExt[1] = '\0';
- if (token == tSYM) {
- if (atr) break;
- if ((atr = getBreakAtr(tokenSym)) < 0)
- er_return(E_BPATR);
- } else if (token == tSTR) {
- if (cmdlen) break;
- if ((cmdlen = tokenLen) > L_BPCMD) er_return(E_BPCMD);
- cmd = tokenStr;
- }
- getToken(0);
- }
-
- /*set breakpoint */
- if (! isnotEOC()) {
- if ((atr = setBreak(addr, atr, cmd, cmdlen))) er_return(atr);
- }
-}
-/*
- clear breakpoint command processing
-
- BC [break_addr][,break_addr]..
-*/
-LOCAL void cmdBrkClr(void)
-{
- UW addr;
-
- if (token <= tEOC) {
- clearBreak(0); /* clear all */
- } else {
- do { /* clear individual breakpoint */
- if (getNumber(0, &addr)) return;
- if (clearBreak(addr) < 0) er_return(E_BPUDF);
- } while (isDLM());
- isnotEOC();
- }
-}
-/*
- download command processing
-
- LO protocol[,loading_addr]
-*/
-LOCAL void cmdLoad(void)
-{
- W i, par;
- UW addr;
-LOCAL const struct {
- UB nm[2];
- UH par;
-} proto[] = {
- {"S ", P_TEXT | P_SFORM},
- {"XS", P_XMODEM | P_SFORM},
- {"XM", P_XMODEM | P_MEMIMG},
- {" ", 0x00}
-};
-
- /* extract protocol */
- if (token != tSYM) er_return(E_LESS);
-
- par = 0;
- if (tokenSym[2] == ' ') {
- for (i = 0; proto[i].par != 0; i++) {
- if (memcmp(tokenSym, proto[i].nm, sizeof(UH)) == 0) {
- par = proto[i].par;
- break;
- }
- }
- }
- if (par == 0) er_return(E_PROTO);
-
- /* extract start address */
- getToken(0);
- if (isDLM()) {
- if (getNumber(0, &addr)) return;
- } else {
- addr = 0;
- if (par & P_MEMIMG) er_return(E_NOADDR);
- }
- if (isnotEOC()) return;
-
- /* execute loading */
- errcode = doLoading(par, addr, NULL);
-}
-/*
- backtrace command processing
-
- BTR
-*/
-LOCAL void cmdBackTrace(void)
-{
- er_return(E_NOSPT);
-}
-/*
- disk command processing
-
- RD device, sblk, nblk, addr
- WD device, sblk, nblk, addr
- ID device
- BD [device]
-*/
-LOCAL void cmdDisk(W kind)
-{
- W i;
- UW par[3], blksz, nblks;
- UB c, devnm[L_DEVNM + 1];
-
- /* extract device name */
- if (token <= tEOC) {
- if (kind != 3) er_return(E_LESS);
- devnm[0] = '\0';
- } else {
- if (token != tSYM || tokenLen > L_DEVNM) er_return(E_LESS);
- /* device names are to be given in lower case letters */
- for (i = 0; i < tokenLen; i++) {
- c = tokenSym[i];
- if (c >= 'A' && c <= 'Z') c += 'a' - 'A';
- devnm[i] = c;
- }
- devnm[i] = '\0';
- getToken(0);
- }
-
- /* extract parameters */
- if (kind <= 1) {
- for (i = 0; i < 3; i++) {
- if (isnotDLM()) return;
- if (getNumber(0, &par[i])) return;
- }
- }
- if (isnotEOC()) return;
-
- switch(kind) {
- case 0: /* ReadDisk */
- case 1: /* WriteDisk */
- errcode = rwDisk(devnm, par[0], par[1], (void*)par[2], kind);
- break;
- case 2: /* InfoDisk */
- errcode = infoDisk(devnm, &blksz, &nblks);
- if (errcode >= E_OK) {
- DSP_S(devnm);
- DSP_F5(S,": Bytes/block: ", D,blksz,
- S," Total blocks: ", D,nblks, CH,'\n');
- }
- break;
- case 3: /* BootDisk */
- errcode = bootDisk(( devnm[0] == '\0' )? NULL: devnm);
- if (errcode >= E_OK) errcode = CMD_FINISH; /* Fin */
- break;
- }
-}
-/*
- exit command processing
-
- EX [par]
-*/
-LOCAL void cmdExit(void)
-{
- W par;
-
- /* extract parameters */
- if (token <= tDLM) par = 0;
- else if (getNumber(0, &par)) return;
-
- DSP_S((par < 0) ? "** System Reset\n" : "** System Power Off\n");
- waitMsec(100); /* give extra time for draining the remaining output */
-
- sysExit(par); /* system reset or power off (never returnes) */
-}
-/*
- forcible kill process command processing
-
- KILL
-*/
-LOCAL void cmdKill(void)
-{
- if (isnotEOC()) return;
- if (isKillValid() == 0) {
- killProcReq = 1;
- errcode = CMD_FINISH;
- }
-}
-/*
- FROM write command processing
-
- WROM
-*/
-LOCAL void cmdWrom(void)
-{
- UW addr, data;
- W nsec;
-
- /* extract parameters */
- if (getNumber(0, &addr)) return;
- if (isnotDLM() || getNumber(0, &data)) return;
- if (isnotDLM() || getNumber(0, &nsec)) return;
- if (isnotEOC()) return;
- errcode = writeFrom(addr, data, nsec, 1);
-}
-/*
- FLASH ROM load command processing
-
- FLLO [attr]
-*/
-LOCAL void cmdFlashLoad(void)
-{
- W i, proto, mode;
- UW addr[3];
-
- proto = P_TEXT | P_SFORM;
- mode = 0;
-
- /* extract attributes */
- if (token > tEOC) {
- if (token != tSYM) er_return(E_PAR);
- for (i = 0; i < L_SYMBOL; i++) {
- switch(tokenSym[i]) {
- case 'X': proto = P_XMODEM | P_SFORM; break;
- case 'E': mode = 1; break;
- case ' ': i = L_SYMBOL; break;
- default: er_return(E_PAR);
- }
- }
- getToken(0);
- if (isnotEOC()) return;
- }
-
- /* execute loading */
- setupFlashLoad(0, addr);
- i = addr[1] - addr[0] + 1;
- if (mode) {
- DSP_S("Fill Loading RAM Area with 0xFF\n");
- memset((void*)addr[0], 0xFF, i);
- } else {
- DSP_S("Copy Flash ROM Image to RAM Area\n");
- memcpy((void*)addr[0], (void*)(addr[0] - addr[2]), i);
- }
- DSP_S("> Load S-Format Data of Flash ROM\n");
- errcode = doLoading(proto, 0, addr);
- if (errcode < 0) return;
-
- /* FLASH ROM write */
- setupFlashLoad(-1, addr);
- DSP_F5(S,"Writing Flash ROM at ", 08X,addr[0],
- S," [", D,addr[2], S," blks] ... wait\n");
- errcode = writeFrom(addr[0], addr[1], addr[2], -1);
-}
-/*
- command table
-*/
-typedef struct {
- UB fnm[12]; /* full command name */
- UB snm[4]; /* abbreviated command name */
- FP func; /* processing function */
- W para; /* parameter information and other */
- const HELP *help; /* help message */
-} CMDTAB;
-
-#define IGN_TRACE 0x1000
-
-LOCAL void cmdHelp(void);
-
-LOCAL const CMDTAB cmdTab[] = {
- {"DUMP ","D ", cmdDump, 1, &helpD },
- {"DUMPBYTE ","DB ", cmdDump, 1, &helpDB },
- {"DUMPHALF ","DH ", cmdDump, 2, &helpDH },
- {"DUMPWORD ","DW ", cmdDump, 4, &helpDW },
- {"MODIFY ","M ", cmdModify, 1, &helpM },
- {"MODIFYBYTE ","MB ", cmdModify, 1, &helpMB },
- {"MODIFYHALF ","MH ", cmdModify, 2, &helpMH },
- {"MODIFYWORD ","MW ", cmdModify, 4, &helpMW },
- {"FILL ","F ", cmdFill, 1, &helpF },
- {"FILLBYTE ","FB ", cmdFill, 1, &helpFB },
- {"FILLHALF ","FH ", cmdFill, 2, &helpFH },
- {"FILLWORD ","FW ", cmdFill, 4, &helpFW },
- {"SEARCH ","SC ", cmdSearch, 1, &helpSC },
- {"SEARCHBYTE ","SCB ", cmdSearch, 1, &helpSCB },
- {"SEARCHHALF ","SCH ", cmdSearch, 2, &helpSCH },
- {"SEARCHWORD ","SCW ", cmdSearch, 4, &helpSCW },
- {"COMPARE ","CMP ", cmdCmpMov, 0, &helpCMP },
- {"MOVE ","MOV ", cmdCmpMov, 1, &helpMOV },
- {"INPUTBYTE ","IB ", cmdIO, 1, &helpIB },
- {"INPUTHALF ","IH ", cmdIO, 2, &helpIH },
- {"INPUTWORD ","IW ", cmdIO, 4, &helpIW },
- {"OUTPUTBYTE ","OB ", cmdIO, 0x11, &helpOB },
- {"OUTPUTHALF ","OH ", cmdIO, 0x12, &helpOH },
- {"OUTPUTWORD ","OW ", cmdIO, 0x14, &helpOW },
- {"DISASSEMBLE ","DA ", cmdDisasm, 0, &helpDA },
- {"REGISTER ","R ", cmdRegister, 0, &helpR },
- {"BREAKPOINT ","B ", cmdBreak, 0, &helpB },
- {"BREAKCLEAR ","BC ", cmdBrkClr, 0, &helpBC },
- {"GO ","G ", cmdGoTrace, 0 | IGN_TRACE, &helpG },
- {"STEP ","S ", cmdGoTrace, 1 | IGN_TRACE, &helpS },
- {"NEXT ","N ", cmdGoTrace, 2 | IGN_TRACE, &helpN },
- {"BACKTRACE ","BTR ", cmdBackTrace, 0, &helpBTR },
- {"LOAD ","LO ", cmdLoad, 0, &helpLO },
- {"READDISK ","RD ", cmdDisk, 0, &helpRD },
- {"WRITEDISK ","WD ", cmdDisk, 1, &helpWD },
- {"INFODISK ","ID ", cmdDisk, 2, &helpID },
- {"BOOTDISK ","BD ", cmdDisk, 3, &helpBD },
- {"KILL ","KILL", cmdKill, 0, &helpKILL },
- {"WRITEROM ","WROM", cmdWrom, 0, &helpWROM },
- {"FLASHLOAD ","FLLO", cmdFlashLoad, 0, &helpFLLO },
- {"HELP ","H ", cmdHelp, 0, &helpH },
- {"HELP ","? ", cmdHelp, 0, &helpH },
- {"EXIT ","EX ", cmdExit, 0, &helpEX },
- { } /* end */
-};
-/*
- searching command
-*/
-LOCAL W searchCommand(void)
-{
- W i;
-
- if (token == tSYM && tokenSym[12] == ' ') {
- for (i = 0; cmdTab[i].func != NULL; i++) {
- if (memcmp(cmdTab[i].fnm, tokenSym, 12) == 0 ||
- (tokenSym[4] == ' ' &&
- memcmp(cmdTab[i].snm, tokenSym, sizeof(UW)) == 0) )
- return i;
- }
- }
- return E_CMD;
-}
-/*
- help command pcrocessing
-
- H(?) [command]
-*/
-LOCAL void cmdHelp(void)
-{
- W i;
-
- i = searchCommand();
- printHelp(( i < 0 )? &helpALL: cmdTab[i].help);
-}
-/*
- command interpreter
-
- cmd : initial command line (if NULL : none)
- fin : 0 = continue, 1 = finish (command execution)
- < 0 : trace command execution
-*/
-EXPORT void procCommand(UB *cmd, W fin)
-{
- W i, par;
-
- /* initialize command input */
- if (cmd) {
- strcpy(lptr = lineBuf, cmd);
- token = tEOC;
- } else {
- token = tEOL;
- fin = 0;
- }
-
- /* set DA address to PC */
- daAddr = getCurPC();
-
- for (;;) {
- /* skip the remainder of the previous command */
- while (token > tEOC) getToken(0);
-
- /* input a command line */
- if (token == tEOL) {
- if (fin) break; /* end */
- if (getLine(PROMPT) <= 0) continue;
- }
-
- /* skip comment */
- skipSpace();
- if (*lptr == '*') {
- getToken(0);
- continue;
- }
- /* extract command */
- if (getToken(0) <= tEOC) continue; /* skip empty line */
-
- /* searching command */
- errcode = errinfo = 0;
- if ((i = searchCommand()) < 0) {
- errcode = E_CMD;
- } else {
- if (checkAbort()) continue;
- par = cmdTab[i].para;
-
- /* if there is an initial command, the execution command is ignored */
- if (fin < 0 && (par & IGN_TRACE)) continue;
-
- /* read-ahead of parameters */
- getToken(0);
-
- /* command execution */
- (*(cmdTab[i].func))(par & 0xff);
- }
- if (errcode == CMD_FINISH) break; /* finish */
-
- /* display error */
- if (errcode < 0) dspError();
- }
-}
diff --git a/tkernel_source/monitor/cmdsvc/src/console.c b/tkernel_source/monitor/cmdsvc/src/console.c
deleted file mode 100644
index ea95744..0000000
--- a/tkernel_source/monitor/cmdsvc/src/console.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * console.c
- *
- * console I/O
- */
-
-#include "cmdsvc.h"
-
-/* control characters */
-#define BS ('H'-'@')
-#define CAN ('X'-'@')
-#define CTLC ('C'-'@')
-#define DEL (0x7f)
-#define CR (0x0d)
-#define LF (0x0a)
-#define XOFF ('S'-'@')
-#define XON ('Q'-'@')
-#define ERASE ('K'-'@')
-#define CAN2 ('U'-'@')
-#define TAB ('I'-'@')
-#define ESC ('['-'@')
-#define CUR_UP ('P'-'@') /* or ESC [ A */
-#define CUR_DWN ('N'-'@') /* or ESC [ B */
-#define CUR_FWD ('F'-'@') /* or ESC [ C */
-#define CUR_BWD ('B'-'@') /* or ESC [ D */
-
-#define HISTBUF_SZ 1024 /* history buffer size */
-
-LOCAL UB hist[HISTBUF_SZ]; /* history buffer */
-LOCAL W CTRL_C_IN; /* CTRL-C input flag */
-LOCAL W XOFF_IN; /* XOFF input flag */
-LOCAL const UB Digit[] = "0123456789ABCDEF";
-
-/*
- * detect CTRL-C
- * check if there is a history of control-C input to the console
- * history is cleared
- * return value TRUE : CTRL-C input exists
- * FALSE : CTRL-C input is absent
- */
-EXPORT BOOL checkAbort( void )
-{
- if (CTRL_C_IN) {CTRL_C_IN = 0; return TRUE;}
- return FALSE;
-}
-
-/*
- * console output (one character)
- * XON/XOFF flow control
- * check for CTRL-C input
- * return value 0 : normal
- * -1 : CTRL-C input exists
- */
-EXPORT W putChar( W c )
-{
- W ch;
-
- if (XOFF_IN || (ch = getSIO(0)) == XOFF) {
- while ((ch = getSIO(1)) != XON && ch != CTLC);
- XOFF_IN = 0;
- }
- if (ch == CTLC) {CTRL_C_IN++; return -1;}
- if (c == LF) putSIO(CR);
- putSIO(c);
- return 0;
-}
-
-/*
- * console output (character string)
- * XON/XOFF flow control
- * check for CTRL-C input
- * return value 0 : normal
- * -1 : CTRL-C input exists
- */
-EXPORT W putString( const UB *str )
-{
- UB c;
-
- while ((c = *str++)) {
- if (putChar(c) < 0) return -1;
- }
- return 0;
-}
-
-/*
- * console output (hexadecimal: 2, 4, or 8 columns)
- * XON/XOFF flow control
- * check for CTRL-C input
- * return value 0 : normal
- * -1 : CTRL-C input exists
- */
-EXPORT W putHex2( UB val )
-{
- if (putChar(Digit[(val >> 4) & 0x0f]) < 0) return -1;
- if (putChar(Digit[(val >> 0) & 0x0f]) < 0) return -1;
- return 0;
-}
-
-EXPORT W putHex4( UH val )
-{
- if (putHex2(val >> 8) < 0) return -1;
- if (putHex2(val >> 0) < 0) return -1;
- return 0;
-}
-
-EXPORT W putHex8( UW val )
-{
- if (putHex2(val >> 24) < 0) return -1;
- if (putHex2(val >> 16) < 0) return -1;
- if (putHex2(val >> 8) < 0) return -1;
- if (putHex2(val >> 0) < 0) return -1;
- return 0;
-}
-
-/*
- * console output (decimal: 10 columns/zero-suppress supported)
- * XON/XOFF flow control
- * check for CTRL-C input
- * return value 0 : normal
- * -1 : CTRL-C input exists
- */
-EXPORT W putDec( UW val )
-{
- W i;
- UB d[11]; /* required columns for displaying 32-bit maximum cardinal(4,294,967,295) +1 */
-
- for (i = 0; i < sizeof(d); i++) {
- d[i] = Digit[val % 10];
- val /= 10;
- if (!val) break;
- }
-
- for (; i >= 0; i--) {
- if (putChar(d[i]) < 0) return -1;
- }
-
- return 0;
-}
-
-/*
- * console input (one character)
- * if wait = TRUE, wait for input if FALSE, do not wait.
- * return value >= 0 : character
- * -1 : no input
- */
-EXPORT W getChar( BOOL wait )
-{
- W c;
-
- for (;;) {
- if ((c = getSIO(0)) == XOFF) XOFF_IN = 1;
- else if (c != -1 || !wait) break;
- }
- return c;
-}
-
-/*
- * consle input (character string)
- * line input with editing
- * return value >= 0 : number of input characters
- * -1 : CTRL-C was detected
- */
-EXPORT W getString( UB *str )
-{
- W i, c, c1;
- W cp, ep, hp, esc;
- W len;
-
- CTRL_C_IN = 0;
- c = c1 = 0;
- cp = ep = esc = 0;
- hp = -1;
-
- while (ep < L_LINE - 2) {
- if ((c = getSIO(0)) <= 0) continue;
- len = 1;
- if (c & 0x80) { /* EUC 2 bytes characters */
- if (c1 == 0) {c1 = c; continue;}
- c |= c1 << 8;
- c1 = 0;
- len = 2;
- }
- if (c == ESC) {esc = 1; continue;}
-
- if (esc) { /* ESC sequence */
- if (esc == 1) {
- esc = (c == '[') ? 2 : 0;
- continue;
- }
- esc = 0;
- if (c == 'A') c = CUR_UP;
- else if (c == 'B') c = CUR_DWN;
- else if (c == 'C') c = CUR_FWD;
- else if (c == 'D') c = CUR_BWD;
- else continue;
- }
- if (c == CUR_FWD) {
- if (cp < ep) {
- if (str[cp] & 0x80) putSIO(str[cp++]);
- putSIO(str[cp++]);
- }
- continue;
- }
- if (c == CUR_BWD) {
- if (cp > 0) {
- if (str[--cp] & 0x80) {putSIO(BS); cp--;}
- putSIO(BS);
- }
- continue;
- }
- if (c == CUR_UP || c == CUR_DWN) { /* history is recalled */
- if (c == CUR_DWN) {
- if (hp <= 0) continue;
- for (hp--; (--hp) > 0 && hist[hp];);
- if (hp) hp++;
- } else {
- i = hp < 0 ? 0 : (strlen(&hist[hp]) + hp + 1);
- if (hist[i] == '\0') continue;
- hp = i;
- }
- for (; cp > 0; cp--) putSIO(BS);
- for (i = strlen(&hist[hp]); cp < i; cp++)
- putSIO(str[cp] = hist[hp + cp]);
- c = ERASE;
- }
- if (c == BS || c == DEL) {
- if (cp <= 0) continue;
- len = (str[cp - 1] & 0x80) ? 2 : 1;
- if (cp < ep) memcpy(&str[cp - len], &str[cp], ep - cp);
- for (i = 0; i < len; i++)
- {str[--ep] = ' '; putSIO(BS);}
- cp -= len;
- for (i = cp; i < ep + len; i++) putSIO(str[i]);
- for (; i > cp; i--) putSIO(BS);
- continue;
- }
- if (c == CAN || c == CAN2) {
- for (; cp > 0; cp--) putSIO(BS);
- c = ERASE;
- }
- if (c == ERASE) {
- for (i = cp; i < ep; i++) putSIO(' ');
- for (; i > cp; i--) putSIO(BS);
- ep = cp;
- continue;
- }
-
- if (c == CR || c == LF) break;
-
- if (c == CTLC) {
- CTRL_C_IN++;
- break;
- }
-
- if (c < ' ' && c != TAB) continue;
-
- if (cp < ep) memmove(&str[cp + len], &str[cp], ep - cp);
- if (len == 2) {
- str[cp + 1] = c & 0xff;
- c = (c >> 8) & 0xff;
- }
- str[cp] = c;
- for (ep += len, i = cp; i < ep; i++) putSIO(str[i]);
- for (cp += len; i > cp; i--) putSIO(BS);
- }
- putSIO(CR); /* echo back */
- putSIO(LF);
- str[ep] = '\0';
- if (c == CTLC) return -1;
-
- if (ep) { /* add to history buffer */
- i = ep + 1;
- memmove(&hist[i], hist, HISTBUF_SZ - i);
- memcpy(hist, str, i);
- hist[HISTBUF_SZ - 2] = '\0';
- hist[HISTBUF_SZ - 1] = '\0';
- }
- return ep;
-}
diff --git a/tkernel_source/monitor/cmdsvc/src/help.h b/tkernel_source/monitor/cmdsvc/src/help.h
deleted file mode 100644
index 1af3a5d..0000000
--- a/tkernel_source/monitor/cmdsvc/src/help.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * help.h
- *
- * help message definitions
- */
-
-/*
- * help message definitions
- */
-typedef struct help HELP;
-struct help {
- void (*prfn)( const HELP* ); /* display function */
- const UB *msg; /* message */
-};
-
-/*
- * display help message
- */
-IMPORT void printHelp( const HELP *help );
-
-/*
- * help message data
- */
-IMPORT const HELP helpALL;
-IMPORT const HELP helpD, helpDB, helpDH, helpDW;
-IMPORT const HELP helpM, helpMB, helpMH, helpMW;
-IMPORT const HELP helpF, helpFB, helpFH, helpFW;
-IMPORT const HELP helpSC, helpSCB, helpSCH, helpSCW;
-IMPORT const HELP helpCMP, helpMOV;
-IMPORT const HELP helpIB, helpIH, helpIW;
-IMPORT const HELP helpOB, helpOH, helpOW;
-IMPORT const HELP helpDA, helpR, helpB, helpBC;
-IMPORT const HELP helpG, helpS, helpN, helpBTR, helpLO;
-IMPORT const HELP helpRD, helpWD, helpID, helpBD;
-IMPORT const HELP helpKILL, helpWROM, helpFLLO;
-IMPORT const HELP helpH, helpEX;
diff --git a/tkernel_source/monitor/cmdsvc/src/helpmsg.c b/tkernel_source/monitor/cmdsvc/src/helpmsg.c
deleted file mode 100644
index a71424b..0000000
--- a/tkernel_source/monitor/cmdsvc/src/helpmsg.c
+++ /dev/null
@@ -1,392 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * helpmsg.c
- *
- * command help message
- */
-
-#include "cmdsvc.h"
-#include "help.h"
-
-/*
- * display help message
- */
-EXPORT void printHelp( const HELP *help )
-{
- (*help->prfn)(help);
-}
-
-/*
- * display simple help message
- */
-LOCAL void prSimpleHelp( const HELP *help )
-{
- DSP_S(help->msg);
-}
-
-/*
- * display help message for dump command
- */
-LOCAL void prDumpHelp( const HELP *help )
-{
- const UB *p1 = help->msg;
- const UB *p2;
-
- for (; *p1; p1++);
- p2 = ++p1;
- for (; *p2; p2++);
- p2++;
- DSP_F5(S,"Dump", S,help->msg,
- S,"(D", S,p1, S,") [start_addr][,{end_addr|#data_cnt}] ");
- DSP_F3(S,": Dump Memory in ", S,p2, CH,'\n');
-}
-
-/*
- * display help message for modify command
- */
-LOCAL void prModifyHelp( const HELP *help )
-{
- const UB *p1 = help->msg;
- const UB *p2;
-
- for (; *p1; p1++);
- p2 = ++p1;
- for (; *p2; p2++);
- p2++;
- DSP_F5(S,"Modify", S,help->msg,
- S,"(M", S,p1, S,") [start_addr][,data].. ");
- DSP_F3(S,": Modify Memory in ", S,p2, CH,'\n');
-}
-
-/*
- * display help message for fill command
- */
-LOCAL void prFillHelp( const HELP *help )
-{
- const UB *p1 = help->msg;
- const UB *p2;
-
- for (; *p1; p1++);
- p2 = ++p1;
- for (; *p2; p2++);
- p2++;
- DSP_F5(S,"Fill", S,help->msg,
- S,"(F", S,p1, S,") start_addr,{end_addr|#data_cnt}[,data].. ");
- DSP_F3(S,": Fill Memory in ", S,p2, CH,'\n');
-}
-
-/*
- * display help message for search command
- */
-LOCAL void prSearchHelp( const HELP *help )
-{
- const UB *p1 = help->msg;
- const UB *p2;
-
- for (; *p1; p1++);
- p2 = ++p1;
- for (; *p2; p2++);
- p2++;
- DSP_F5(S,"Search", S,help->msg,
- S,"(SC", S,p1,
- S,") start_addr,{end_addr|#data_cnt},data[,data].. ");
- DSP_F3(S,": Search Memory in ", S,p2, CH,'\n');
-}
-
-/*
- * display help message for input command
- */
-LOCAL void prInputHelp( const HELP *help )
-{
- const UB *p = help->msg;
-
- for (; *p; p++);
- p++;
- DSP_F5(S,"Input", S,help->msg, S,"(I", S,p, S,") port ");
- DSP_F3(S,": Input ", S,help->msg, S," from I/O port\n");
-}
-
-/*
- * display help message for output command
- */
-LOCAL void prOutputHelp( const HELP *help )
-{
- const UB *p = help->msg;
-
- for (; *p; p++);
- p++;
- DSP_F5(S,"Output", S,help->msg, S,"(O", S,p, S,") port,data ");
- DSP_F3(S,": Output ", S,help->msg, S," to I/O port\n");
-}
-
-/*
- * display help message with disk name listing
- */
-LOCAL void prDiskHelp( const HELP *help )
-{
- const UB *devnm;
- UW attr;
- W i;
-
- DSP_S(help->msg);
- DSP_S(" device :");
- for ( i = 0;; ++i ) {
- devnm = ( help == &helpBD )? bootDevice(i): diskList(i, &attr);
- if ( devnm == NULL ) break;
-
- /* exclude devices that can not be specified */
- if ( help == &helpWD && (attr & DA_RONLY) != 0 ) continue;
- DSP_F2(CH,' ', S,devnm);
- }
- DSP_LF;
-}
-
-/*
- * display help message for WROM command
- */
-LOCAL void prWRomHelp( const HELP *help )
-{
- const MEMSEG *rom, *ram;
- UW ram_top, sz;
-
- rom = MemArea(MSA_FROM, 1);
- ram = MemArea(MSA_OS, 1);
- if ( rom == NULL || ram == NULL ) {
- DSP_S("Not Supported\n");
- return;
- }
-
- ram_top = (ram->top + FROM_SECSZ - 1) & ~(FROM_SECSZ - 1);
- sz = rom->end - rom->top;
- if ( sz > ram->end - ram_top ) sz = ram->end - ram_top;
-
- DSP_S(help->msg);
- DSP_F5(S," rom_addr : 0x", 08X,rom->top,
- S," - 0x", 08X,(rom->end-FROM_SECSZ), CH,'\n');
- DSP_F5(S," data_ram_addr : 0x", 08X,ram_top,
- S," - 0x", 08X,(ram->end-FROM_SECSZ), CH,'\n');
- DSP_F5(S," block_count : 1 - ", D,(sz / FROM_SECSZ),
- S," (1 block = ", D,(FROM_SECSZ / 1024), S,"KB)\n");
-}
-
-/* ------------------------------------------------------------------------ */
-
-EXPORT const HELP helpALL = { prSimpleHelp,
- "--- Command List : \"? command\" for details ---\n"
- "DumpByte/Half/Word(D/DB/DH/DW) ModifyByte/Half/Word(M/MB/MH/MW)\n"
- "FillByte/Half/Word(F/FB/FH/FW) SearchByte/Half/Word(SC/SCB/SCH/SCW)\n"
- "InputByte/Half/Word(IB/IH/IW) OutputByte/Half/Word(OB/OH/OW)\n"
- "Compare(CMP) Move(MOV) Disassemble(DA) Register(R)\n"
- "Go(G) Step(S) Next(N) BreakPoint(B) BreakClear(BC)\n"
- "BackTrace(BTR) Kill(KILL) Load(LO)"
- "\n"
- "BootDisk(BD) ReadDisk(RD) WriteDisk(WD) InfoDisk(ID)\n"
- "WriteROM(WROM) FlashLoad(FLLO) Exit(EX) Help(H/?)\n"
-};
-
-EXPORT const HELP helpD = { prDumpHelp,
- "\0\0Byte"
-};
-
-EXPORT const HELP helpDB = { prDumpHelp,
- "Byte\0B\0Byte"
-};
-
-EXPORT const HELP helpDH = { prDumpHelp,
- "Half\0H\0Half"
-};
-
-EXPORT const HELP helpDW = { prDumpHelp,
- "Word\0W\0Word"
-};
-
-EXPORT const HELP helpM = { prModifyHelp,
- "\0\0Byte"
-};
-
-EXPORT const HELP helpMB = { prModifyHelp,
- "Byte\0B\0Byte"
-};
-
-EXPORT const HELP helpMH = { prModifyHelp,
- "Half\0H\0Half"
-};
-
-EXPORT const HELP helpMW = { prModifyHelp,
- "Word\0W\0Word"
-};
-
-EXPORT const HELP helpF = { prFillHelp,
- "\0\0Byte"
-};
-
-EXPORT const HELP helpFB = { prFillHelp,
- "Byte\0B\0Byte"
-};
-
-EXPORT const HELP helpFH = { prFillHelp,
- "Half\0H\0Half"
-};
-
-EXPORT const HELP helpFW = { prFillHelp,
- "Word\0W\0Word"
-};
-
-EXPORT const HELP helpSC = { prSearchHelp,
- "\0\0Byte"
-};
-
-EXPORT const HELP helpSCB = { prSearchHelp,
- "Byte\0B\0Byte"
-};
-
-EXPORT const HELP helpSCH = { prSearchHelp,
- "Half\0H\0Half"
-};
-
-EXPORT const HELP helpSCW = { prSearchHelp,
- "Word\0W\0Word"
-};
-
-EXPORT const HELP helpCMP = { prSimpleHelp,
- "Compare(CMP) start_addr,{end_addr|#byte_cnt},compare_addr : "
- "Compare Memory\n"
-};
-
-EXPORT const HELP helpMOV = { prSimpleHelp,
- "Move(MOV) start_addr,{end_addr|#byte_cnt},dest_addr : Move Memory\n"
-};
-
-EXPORT const HELP helpIB = { prInputHelp,
- "Byte\0B"
-};
-
-EXPORT const HELP helpIH = { prInputHelp,
- "Half\0H"
-};
-
-EXPORT const HELP helpIW = { prInputHelp,
- "Word\0W"
-};
-
-EXPORT const HELP helpOB = { prOutputHelp,
- "Byte\0B"
-};
-
-EXPORT const HELP helpOH = { prOutputHelp,
- "Half\0H"
-};
-
-EXPORT const HELP helpOW = { prOutputHelp,
- "Word\0W"
-};
-
-EXPORT const HELP helpDA = { prSimpleHelp,
- "Disassemble(DA) [start_addr][,step_cnt] : Disassemble\n"
- " Not Supported\n"
-};
-
-EXPORT const HELP helpR = { prSimpleHelp,
- "Register(R) [register_name[,data]] : Register Dump / Modify\n"
-};
-
-EXPORT const HELP helpG = { prSimpleHelp,
- "Go(G) [start_addr][,break_addr] : Go Program\n"
-};
-
-EXPORT const HELP helpB = { prSimpleHelp,
- "BreakPoint(B) [break_addr[,break_attr][,\"command\"]] : Set Break Point\n"
- " break_attr : S\n"
-};
-
-EXPORT const HELP helpBC = { prSimpleHelp,
- "BreakClear(BC) [break_addr][,break_addr].. : Clear Break Point\n"
-};
-
-EXPORT const HELP helpS = { prSimpleHelp,
- "Step(S) [start_addr][,step_cnt] : Step Trace Program\n"
-};
-
-EXPORT const HELP helpN = { prSimpleHelp,
- "Next(N) [start_addr][,step_cnt] : Next Trace Program\n"
-};
-
-EXPORT const HELP helpBTR = { prSimpleHelp,
- "BackTrace(BTR) [frame_pointer] : Display Backtrace\n"
- " Not Supported\n"
-};
-
-EXPORT const HELP helpLO = { prSimpleHelp,
- "Load(LO) {S|XS|XM} [,load addr] : Load Program / Data\n"
- " S : Load s-format data (no protocol)\n"
- " XM : Load memory image (XMODEM protocol)\n"
- " XS : Load s-format data (XMODEM protocol)\n"
-};
-
-EXPORT const HELP helpRD = { prDiskHelp,
- "ReadDisk(RD) device, start_block, nblocks, mem_addr : Read Disk Blocks\n"
-};
-
-EXPORT const HELP helpWD = { prDiskHelp,
- "WriteDisk(WD) device, start_block, nblocks, mem_addr : Write Disk Blocks\n"
-};
-
-EXPORT const HELP helpID = { prDiskHelp,
- "InfoDisk(ID) device : Display Disk Information\n"
-};
-
-EXPORT const HELP helpBD = { prDiskHelp,
- "BootDisk(BD) [device] : Boot from Disk\n"
-};
-
-EXPORT const HELP helpKILL = { prSimpleHelp,
- "Kill : Kill Process and Continue\n"
-};
-
-EXPORT const HELP helpH = { prSimpleHelp,
- "Help(H/?) [command_name] : Help Message\n"
-};
-
-EXPORT const HELP helpEX = { prSimpleHelp,
- "Exit(EX) [0] : System Power Off\n"
- "Exit(EX) -1 : System Reset (Restart)\n"
-};
-
-EXPORT const HELP helpWROM = { prWRomHelp,
- "WriteROM(WROM) rom_addr, data_ram_addr, block_count : "
- "Write Flash ROM blocks\n"
-};
-
-EXPORT const HELP helpFLLO = { prSimpleHelp,
- "FlashLoad(FLLO) [attr] : Load S-Format Data & Write Flash ROM\n"
- " attr: X Use XMODEM protocol\n"
- " E Fill write blocks with 0xFF\n"
- " Default : Overwrite original Flash ROM Image\n"
-};
-
-/* ======================================================================== */
-
-/*
- * display boot message
- */
-EXPORT void dispTitle( void )
-{
- int i;
-
- DSP_S("\n\n");
- for ( i = 0; Title[i] != NULL; i++ ) DSP_S(Title[i]);
- DSP_S("\n\n");
-}
diff --git a/tkernel_source/monitor/cmdsvc/src/load.c b/tkernel_source/monitor/cmdsvc/src/load.c
deleted file mode 100644
index 292a47c..0000000
--- a/tkernel_source/monitor/cmdsvc/src/load.c
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * load.c
- *
- * load processing
- */
-
-#include "cmdsvc.h"
-
-LOCAL UW s_addr; /* start address */
-LOCAL UW e_addr; /* end address + 1 */
-LOCAL UW offset; /* address offset */
-LOCAL UW loaddr; /* address lower limit */
-LOCAL UW hiaddr; /* address upper limit */
-LOCAL W blkno; /* block number */
-LOCAL W blkptr; /* read pointer */
-#define XBLK_SZ 1024 /* XMODEM block size (extended) */
-#define BLK_SZ 128 /* XMODEM block size */
-#define blkbuf wrkBuf /* block buffer */
-LOCAL W blksz; /* block size */
-
-LOCAL FUNCP readFn; /* read function */
-
-#define inputByte(tmo) getSIO(tmo) /* input one byte */
-#define outputByte(c) putSIO(c) /* output one byte */
-
-/* XMODEM control codes */
-#define SOH (0x01)
-#define STX (0x02)
-#define EOT (0x04)
-#define ACK (0x06)
-#define NAK (0x15)
-#define CAN (0x18)
-#define CTLC ('C' - '@')
-#define CTLZ ('Z' - '@')
-
-/* XMODEM time out specification
- * wait for SOH : 10 seconds / 10 retries
- * timeout between two characters : 1 seconds
- *
- * how to cope with communication software (mainly for TeraTerm) that does not start automatic transfer
- * (this falls outside XMODEM specification)
- * Since the timeout value for SOH is 10 seconds, the initial transfer always seem to wait for 10 seconds.
- * The initial timeout for SOH is set to 3 seconds (only for the very first transfer.)
- */
-#define IDLE_TMO ( 1 * 1000) /* idle wait(milliseconds) */
-#define RECV_TMO ( 1 * 1000) /* timeout for data input (milliseconds) */
-#define SOH_TMO (10 * 1000) /* timeout for SOH input (milliseconds) */
-#define SOH1_TMO ( 3 * 1000) /* timeout for the initial SOH input (milliseconds) */
-#define MAX_RETRY 10 /* maximum number of retries */
-
-/*
- skip until there is no more input
-*/
-LOCAL void purgeInput(void)
-{
- while (inputByte(IDLE_TMO) >= 0);
-}
-/*
- asynchronous read processing (without any protocol)
-*/
-LOCAL W textRead(void)
-{
- W c;
-
- while ((c = inputByte(0)) < 0);
- return (c == CTLC || c == CAN) ? E_CANCEL : c;
-}
-/*
- XMODEM read processing
-*/
-LOCAL W xmodemRead(void)
-{
- W i, c, ctlch;
- UB cksum;
-
- if (blkptr < blksz) return blkbuf[blkptr++];
-
- c = 0;
- ctlch = ACK;
- if (blkno++ == 0) {
- /* only for the initial packet transfer */
- outputByte(NAK);
- c = inputByte(SOH1_TMO);
- ctlch = -1;
- }
-
- for (;;) {
- /* receiving block */
- for (i = 0;;) {
- if (ctlch >= 0) {
- /* ack/beginning character is transmitted */
- outputByte(ctlch);
-
- /* leading letter in the ack is extracted */
- c = inputByte(SOH_TMO);
- }
- ctlch = NAK;
- if (c == SOH) {blksz = BLK_SZ; break;}
- if (c == STX) {blksz = XBLK_SZ; break;}
- if (c == CAN || c == CTLC) { /* cancel transfer */
- /* Is CAN followed by another CAN? */
- c = inputByte(IDLE_TMO);
- if (c < 0 || c == CAN || c == CTLC)
- return E_CANCEL;
- } else if (c == EOT) { /* end of transmission */
- outputByte(ACK);
- return E_END;
- }
- purgeInput(); /* skip data */
- if (++i >= MAX_RETRY) return E_XMODEM;
- }
-
- /* read a block number & check */
- if ((i = inputByte(RECV_TMO)) < 0) continue;
- if ((c = inputByte(RECV_TMO)) < 0) continue;
- if (i + c != 0xff) continue;
-
- if (i != (blkno & 0xff)) {
- if (i != ((blkno - 1) & 0xff)) return E_XMODEM;
- /* skip if the previous block is read */
- ctlch = ACK;
- }
-
- /* read the block itself */
- for (cksum = 0, i = 0; i < blksz; i++) {
- if ((c = inputByte(RECV_TMO)) < 0) break;
- cksum += (blkbuf[i] = c);
- }
- if (c < 0) continue;
-
- /* validate checksum */
- if (inputByte(RECV_TMO) == cksum && ctlch != ACK) break;
- }
- blkptr = 0;
- return blkbuf[blkptr++];
-}
-/*
- XMODEM termination processing
-*/
-LOCAL void xmodemEnd(W er)
-{
- /* finish XMODEM protocol */
- while (er >= 0) er = xmodemRead();
-
- if (er != E_END && er != E_CANCEL) {
- purgeInput(); /* wait until there is no more data */
- outputByte(CAN); /* transmite two (or more) consecutive CANs */
- outputByte(CAN);
- outputByte(CAN);
- }
-}
-/*
- load memory image
-*/
-LOCAL W loadImage(void)
-{
- W i, c;
- UB buf[512];
-
- for (i = 0;;) {
- if ((c = (*readFn)()) >= 0) buf[i++] = c;
- if (i < sizeof(buf) && c >= 0) continue;
- if (i > 0) {
- if (e_addr < loaddr ||
- e_addr - 1 > hiaddr - i) return E_RANGE;
- if (writeMem(e_addr, buf, i, 1) != i) return E_MACV;
- e_addr += i;
- i = 0;
- }
- if (c < 0) return c;
- }
-}
-/*
- read a hexadecimal character
-*/
-LOCAL W readHex(void)
-{
- W c;
-
- if ((c = (*readFn)()) < 0) return c;
- if (c >= '0' && c <= '9') return c - '0';
- if (c >= 'A' && c <= 'F') return c - 'A' + 10;
- if (c >= 'a' && c <= 'f') return c - 'a' + 10;
- return E_LOAD;
-}
-/*
- load S format data
-*/
-LOCAL W loadSform(void)
-{
- W i, c, bcnt, v, v1, dcnt, rtype;
- UW addr, a_addr;
- UB cksum, buf[512];
-
- a_addr = s_addr; /* real address */
- s_addr = 0xffffffff; /* highest load address */
- e_addr = 0; /* lowest load address */
-
- for (;;) {
- if ((c = (*readFn)()) < 0) return c;
-
- if (c != 'S') {
- if (c == CTLZ) break; /* end */
- continue;
- }
-
- if ((c = (*readFn)()) < 0) return c;
- switch(c) {
- case '0': /* header */
- rtype = 0; break;
- case '1': /* 2 byte address data */
- case '2': /* 3 byte address data */
- case '3': /* 4 byte address data */
- rtype = c - '0' + 2; break;
- case '7': /* 4 byte address termination */
- case '8': /* 3 byte address termination */
- case '9': /* 2 byte address termination */
- rtype = -1; break;
- default: return E_LOADFMT;
- }
-
- for (cksum = bcnt = addr = dcnt = i = 0;; i++) {
- if ((v1 = readHex()) < 0) return v1;
- if ((v = readHex()) < 0) return v;
- cksum += (v += (v1 << 4));
-
- if (i == 0) { /* byte counts */
- if ((bcnt = v - 1) < 0) return E_LOAD;
- addr = 0;
- continue;
- }
- if (i > bcnt) { /* checksum */
- if (cksum != 0xff) return E_LOAD;
- break;
- }
- if (rtype <= 0) continue;
-
- if (i < rtype) { /* load address */
- addr = (addr << 8) + v;
- } else { /* data */
- buf[dcnt++] = (UB)v;
- }
- }
- if (dcnt > 0) {
- /* if we have address specification, then the first address */
- /* to be used as the designated address after suitable adjustment. */
- if (a_addr != 0) {
- offset = a_addr - addr;
- a_addr = 0;
- }
- addr += offset;
- if (addr < loaddr || addr - 1 > hiaddr - dcnt)
- return E_RANGE;
- if (writeMem(addr, buf, dcnt, 1) != dcnt)
- return E_MACV;
- if (addr < s_addr) s_addr = addr;
- if ((addr += dcnt) > e_addr) e_addr = addr;
- }
- if (rtype < 0) break; /* end */
- }
- return E_OK;
-}
-/*
- loading processing
-*/
-EXPORT ER doLoading(W proto, UW addr, UW *range)
-{
- ER er;
-
- e_addr = s_addr = addr; /* load address */
-
- if (range) { /* range specification */
- loaddr = range[0]; /* address lower limit */
- hiaddr = range[1]; /* address upper limit */
- offset = range[2]; /* address offset */
- } else {
- loaddr = 0; /* address lower limit */
- hiaddr = 0xFFFFFFFF; /* address upper limit */
- offset = 0; /* address offset */
- }
-
- if (proto & P_XMODEM) { /* XMODEM */
- readFn = (FUNCP)xmodemRead;
- blkptr = blkno = blksz = 0;
- } else { /* no protocol */
- readFn = (FUNCP)textRead;
- }
-
- if (proto & P_SFORM) { /* S format */
- er = loadSform();
- if (er == E_END) er = E_LOAD;
- } else { /* memory image */
- er = loadImage();
- }
-
- /* read termination processing */
- if (proto & P_XMODEM) xmodemEnd(er);
-
- /* wait until there is no more data */
- purgeInput();
-
- if (er == E_END) er = E_OK;
- DSP_LF;
- if (er == E_OK) {
- e_addr--;
- if (range) {
- range[0] = s_addr; /* load address */
- range[1] = e_addr;
- s_addr -= offset;
- e_addr -= offset;
- }
- DSP_F5(S,"Loaded: ", 08X,s_addr, S," -> ", 08X,e_addr, CH,'\n');
- }
- return er;
-}
diff --git a/tkernel_source/monitor/cmdsvc/src/memory.c b/tkernel_source/monitor/cmdsvc/src/memory.c
deleted file mode 100644
index f95a8bf..0000000
--- a/tkernel_source/monitor/cmdsvc/src/memory.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * memory.c
- *
- * memory & I/O access processing
- */
-
-#include "cmdsvc.h"
-
-/* multi-type memory pointer */
-typedef union {
- UW a;
- UW *w;
- UH *h;
- UB *b;
-} MP;
-
-/*
- read memory
-*/
-EXPORT W readMem(UW addr, void *buf, W len, W unit)
-{
- W i, n, alen;
- MP pa, bp;
-
- /* address misalignment is reported as error */
- if (addr & (unit - 1)) return 0;
-
- bp.w = buf;
- for (alen = 0; alen < len; alen += i) {
-
- /* memory address check & conversion to physical address */
- n = chkMemAddr(addr + alen, &pa.a, len - alen, 0);
- if (n < unit) break; /* illegal address */
-
- i = 0;
- switch(unit) {
- case 4:
- for (; i < n; i += 4) *bp.w++ = rd_w(pa.w++);
- break;
- case 2:
- for (; i < n; i += 2) *bp.h++ = rd_h(pa.h++);
- break;
- default:
- for (; i < n; i++) *bp.b++ = rd_b(pa.b++);
- }
- }
- return alen;
-}
-/*
- write memory
- unit & 0x10 : fill
-*/
-EXPORT W writeMem(UW addr, void *buf, W len, W unit)
-{
- W i, n, sz, alen;
- MP pa, bp;
-
- /* address misalignment is reported as error */
- sz = unit & 0x0f;
- if (addr & (sz - 1)) return 0;
-
- bp.w = buf;
- for (alen = 0; alen < len; alen += i) {
-
- /* memory address check & conversion to physical address */
- n = chkMemAddr(addr + alen, &pa.a, len - alen, 1);
- if (n < sz) break; /* illegal address */
-
- i = 0;
- switch(sz) {
- case 4:
- if (unit & 0x10) {
- for (; i < n; i += 4) wr_w(pa.w++, *bp.w);
- } else {
- for (; i < n; i += 4) wr_w(pa.w++, *bp.w++);
- }
- break;
- case 2:
- if (unit & 0x10) {
- for (; i < n; i += 2) wr_h(pa.h++, *bp.h);
- } else {
- for (; i < n; i += 2) wr_h(pa.h++, *bp.h++);
- }
- break;
- default:
- if (unit & 0x10) {
- for (; i < n; i++) wr_b(pa.b++, *bp.b);
- } else {
- for (; i < n; i++) wr_b(pa.b++, *bp.b++);
- }
- }
- }
- return alen;
-}
-/*
- read character string
-*/
-EXPORT W readMemStr(UW addr, void *buf, W len)
-{
- W i, n, alen;
- UW pa;
-
- for (alen = 0; alen < len; alen += i) {
- /* memory address check & conversion to physical address */
- n = chkMemAddr(addr + alen, &pa, len - alen, 0);
- if (n == 0) break; /* illegal address */
- for (i = 0; i < n; i++, buf++, pa++) {
- if ((*(UB*)buf = rd_b((UB*)pa)) == 0) return alen + i;
- }
- }
- return -1;
-}
-/*
- I/O read
-*/
-EXPORT W readIO(UW addr, UW *data, W unit)
-{
- W n;
- UW pa;
-
- /* address misalignment is reported as error */
- if (addr & (unit - 1)) return 0;
-
- /* I/O address check & conversion to physical address */
- n = chkIOAddr(addr, &pa, unit);
- if (n < unit) return 0;
-
- switch(unit) {
- case 4: *data = in_w(pa); break;
- case 2: *data = in_h(pa); break;
- default: *data = in_b(pa);
- }
- return unit;
-}
-/*
- I/O write
-*/
-EXPORT W writeIO(UW addr, UW data, W unit)
-{
- W n;
- UW pa;
-
- /* address misalignment is reported as error */
- if (addr & (unit - 1)) return 0;
-
- /* I/O address check & conversion to physical address */
- n = chkIOAddr(addr, &pa, unit);
- if (n < unit) return 0;
-
- switch(unit) {
- case 4: out_w(pa, data); break;
- case 2: out_h(pa, data); break;
- default: out_b(pa, data);
- }
- return unit;
-}
diff --git a/tkernel_source/monitor/cmdsvc/src/string.c b/tkernel_source/monitor/cmdsvc/src/string.c
deleted file mode 100644
index 57841bd..0000000
--- a/tkernel_source/monitor/cmdsvc/src/string.c
+++ /dev/null
@@ -1,262 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Added by T-Engine Forum at 2013/03/11.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * string.c
- * Standard string / memory operations used for t-monitor
- */
-
-#include <tmonitor.h>
-
-/* memory access size */
-#define MASZ (sizeof(unsigned long))
-#define MAMSK (MASZ - 1)
-
-/* memory access pointer */
-typedef union {
- unsigned char *cp;
- unsigned long *lp;
- unsigned long lv;
-} MPTR;
-
-/*
- * memset : fill memory area
- */
-void* memset( void *s, int c, size_t n )
-{
- MPTR m;
- size_t cnt;
- unsigned long val;
-
- m.cp = (unsigned char *)s;
- val = (unsigned char)c;
-
- cnt = m.lv & MAMSK;
- if ( cnt > 0 ) {
- /* Not aligned in WASZ bytes */
- if ( n < MASZ * 2) {
- cnt = n;
- } else {
- cnt = MASZ - cnt;
- }
- /* Fill preceding bytes to align */
- n -= cnt;
- do {
- *m.cp++ = (unsigned char)val;
- } while ( --cnt > 0 );
- }
-
- /* Fill in WASZ bytes unit */
- if ( n >= MASZ ) {
- cnt = n / MASZ;
- n &= MAMSK;
- val |= val << 8;
- val |= val << 16;
- do {
- *m.lp++ = val;
- } while ( --cnt > 0 );
- }
-
- /* Fill trailing bytes */
- while ( n-- > 0 ) {
- *m.cp++ = (unsigned char)val;
- }
- return s;
-}
-
-/*
- * memcmp : perform memory comparison
- */
-int memcmp( const void *s1, const void *s2, size_t n )
-{
- int result;
- const unsigned char *p1 = s1;
- const unsigned char *p2 = s2;
-
- while ( n-- > 0 ) {
- result = *p1++ - *p2++;
- if ( result != 0 ) return result;
- }
- return 0;
-}
-
-/*
- * memcpy : copy memory
- */
-void* memcpy( void *dst, const void *src, size_t n )
-{
- MPTR s, d;
- size_t cnt;
-
- d.cp = (unsigned char *)dst;
- s.cp = (unsigned char *)src;
-
- if ( ( (s.lv | d.lv) & MAMSK ) != 0 ) {
- /* Not aligned in WASZ bytes */
- if ( ( (s.lv ^ d.lv) & MAMSK ) != 0 || n < MASZ * 2) {
- /* Full copy in a byte unit */
- cnt = n;
- } else {
- /* Copy preceding bytes to align */
- cnt = MASZ - (s.lv & MAMSK);
- }
- /* Copy in a byte unit */
- n -= cnt;
- do {
- *d.cp++ = *s.cp++;
- } while ( --cnt > 0 );
- }
-
- /* Copy in WASZ bytes unit */
- if ( n >= MASZ ) {
- cnt = n / MASZ;
- n &= MAMSK;
- do {
- *d.lp++ = *s.lp++;
- } while ( --cnt > 0 );
- }
-
- /* Copy trailing bytes */
- while ( n-- > 0 ) {
- *d.cp++ = *s.cp++;
- }
- return dst;
-}
-
-/*
- * memmove : move memory
- */
-void* memmove( void *dst, const void *src, size_t n )
-{
- MPTR s, d;
- size_t cnt;
-
- d.cp = (unsigned char *)dst;
- s.cp = (unsigned char *)src;
-
- if ( d.cp < s.cp ) { /* Copy forward */
- if ( ( (s.lv | d.lv) & MAMSK ) != 0 ) {
- if ( ( (s.lv ^ d.lv) & MAMSK ) != 0 || n < MASZ * 2 ) {
- cnt = n;
- } else {
- cnt = MASZ - (s.lv & MAMSK);
- }
- n -= cnt;
- do {
- *d.cp++ = *s.cp++;
- } while ( --cnt > 0 );
- }
- if ( n >= MASZ ) {
- cnt = n / MASZ;
- n &= MAMSK;
- do {
- *d.lp++ = *s.lp++;
- } while ( --cnt > 0 );
- }
- while ( n-- > 0 ) {
- *d.cp++ = *s.cp++;
- }
- } else { /* Copy backward */
- s.cp += n;
- d.cp += n;
- if ( ( (s.lv | d.lv) & MAMSK ) != 0 ) {
- if ( ( (s.lv ^ d.lv) & MAMSK ) != 0 || n < MASZ * 2 ) {
- cnt = n;
- } else {
- cnt = s.lv & MAMSK;
- }
- n -= cnt;
- do {
- *--d.cp = *--s.cp;
- } while ( --cnt > 0 );
- }
- if ( n >= MASZ ) {
- cnt = n / MASZ;
- n &= MAMSK;
- do {
- *--d.lp = *--s.lp;
- } while ( --cnt > 0 );
- }
- while ( n-- > 0 ) {
- *--d.cp = *--s.cp;
- }
- }
- return dst;
-}
-
-/*
- * strlen : get text string length
- */
-size_t strlen( const char *s )
-{
- char *cp = (char *)s;
-
- while ( *cp != '\0' ) cp++;
- return (size_t)(cp - s);
-}
-
-/*
- * strcmp : perform text string comparison
- */
-int strcmp( const char *s1, const char *s2 )
-{
- for ( ; *s1 == *s2; s1++, s2++ ) {
- if ( *s1 == '\0' ) return 0;
- }
- return (unsigned char)*s1 - (unsigned char)*s2;
-}
-
-/*
- * strncmp : perform text string comparison of specified length
- */
-int strncmp( const char *s1, const char *s2, size_t n )
-{
- int result;
-
- while ( n-- > 0 ) {
- result = (unsigned char)*s1 - (unsigned char)*s2++;
- if ( result != 0 ) return result;
- if ( *s1++ == '\0' ) break;
- }
- return 0;
-}
-
-/*
- * strcpy : copy text string
- */
-char* strcpy( char *dst, const char *src )
-{
- char *dp = dst;
-
- while ( (*dp++ = *src++) != '\0' );
- return dst;
-}
-
-/*
- * strncpy : copy text string of specified length
- */
-char* strncpy( char *dst, const char *src, size_t n )
-{
- char *dp = dst;
-
- while ( n-- > 0 ) {
- if ( (*dp++ = *src++) == '\0' ) {
- while ( n-- > 0 ) *dp++ = '\0';
- break;
- }
- }
- return dst;
-}
-
diff --git a/tkernel_source/monitor/cmdsvc/src/svc.c b/tkernel_source/monitor/cmdsvc/src/svc.c
deleted file mode 100644
index 565dcdc..0000000
--- a/tkernel_source/monitor/cmdsvc/src/svc.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * svc.c
- *
- * service call
- */
-
-#include "cmdsvc.h"
-#include <sys/rominfo.h>
-
-/*
- * submodule extended SVC function
- * fno function code
- * p1-p3 parameter(s)
- * er returns error code
- * return value if the function is handled, returns TRUE.
- * if not, returns FALSE
- */
-typedef BOOL (*ESVCFUNC)( W fno, W p1, W p2, W p3, W *er );
-
-/*
- * use weak attribute to call only the linked submodule.
- * `weak' is a gcc-specific function and so other methods (using "#if" for example) need to be employed with other compilers.
- *
- */
-#ifdef __GNUC__
-#define WEAK __attribute__ ((weak))
-#else
-#define WEAK
-#endif
-
-/*
- * submodule
- */
-IMPORT BOOL memDiskSVC( W fno, W p1, W p2, W p3, W *er ) WEAK;
-IMPORT BOOL pciSVC( W fno, W p1, W p2, W p3, W *er ) WEAK;
-IMPORT BOOL usbSVC( W fno, W p1, W p2, W p3, W *er ) WEAK;
-IMPORT BOOL sysExtSVC( W fno, W p1, W p2, W p3, W *er ) WEAK;
-
-/*
- * calling submodule extended SVC function
- */
-LOCAL BOOL callSubModuleSVC( ESVCFUNC func, W fno, W p1, W p2, W p3, W *er )
-{
- if ( func == NULL ) return FALSE;
-
- return (*func)(fno, p1, p2, p3, er);
-}
-
-#define CALL_ESVC(func) callSubModuleSVC(func, fno, p1, p2, p3, &er)
-
-/*
- * extended service call processing
- */
-LOCAL W procExtSVC( W fno, W p1, W p2, W p3 )
-{
- W er;
-
- switch ( fno ) {
- case TMEF_PORTBPS: /* debug port speed (bps) */
- er = ConPortBps;
- break;
-
- case TMEF_DIPSW: /* DIPSW status */
- er = getDipSw();
- break;
-
- case TMEF_WROM: /* Flash ROM write */
- er = writeFrom(p1, p2, p3, 0);
- break;
-
- default:
- CALL_ESVC(sysExtSVC) ||
- CALL_ESVC(usbSVC) ||
- CALL_ESVC(pciSVC) ||
- CALL_ESVC(memDiskSVC) ||
- (er = E_PAR);
- }
-
- return er;
-}
-
-/* ------------------------------------------------------------------------ */
-
-/*
- * service call
- */
-EXPORT W procSVC( W fno, W p1, W p2, W p3, W p4 )
-{
- W er = E_OK;
- W n;
-
- switch ( fno ) {
- case TM_MONITOR: /* void tm_monitor( void ) */
- procCommand(NULL, 0);
- break;
-
- case TM_GETCHAR: /* INT tm_getchar( INT wait ) */
- er = getChar(p1);
- break;
-
- case TM_PUTCHAR: /* INT tm_putchar( INT c ) */
- er = putChar(p1);
- break;
-
- case TM_GETLINE: /* INT tm_getline( UB *buff ) */
- er = getString(wrkBuf);
- if ( er < 0 ) break;
- n = er + 1;
- if ( writeMem(p1, wrkBuf, n, 1) != n ) er = E_MACV;
- break;
-
- case TM_PUTSTRING: /* INT tm_putstring( const UB *buff ) */
- n = readMemStr(p1, wrkBuf, WRKBUF_SZ);
- if ( n < 0 ) { er = E_MACV; break; }
- er = putString(wrkBuf);
- break;
-
- case TM_COMMAND: /* INT tm_command( const UB *buff ) */
- n = readMemStr(p1, lineBuf, L_LINE);
- if ( n < 0 ) { er = E_MACV; break; }
- procCommand(( n == 0 )? NULL: lineBuf, 1);
- break;
-
- case TM_READDISK:
- case TM_WRITEDISK:
- case TM_INFODISK:
- /* INT tm_readdisk( const UB *dev, INT sec, INT nsec, void *addr )
- * INT tm_writedisk( const UB *dev, INT sec, INT nsec, void *addr )
- * INT tm_infodisk( const UB *dev, INT *blksz, INT *nblks )
- */
- n = readMemStr(p1, lineBuf, L_LINE);
- if ( n < 0 ) { er = E_MACV; break; }
-
- if ( fno == TM_INFODISK ) {
- er = infoDisk(lineBuf, (UW*)p2, (UW*)p3);
- } else {
- n = ( fno == TM_READDISK )? 0: 1;
- er = rwDisk(lineBuf, p2, p3, (void*)p4, n);
- }
- break;
-
- case TM_EXIT: /* void tm_exit( INT mode ) */
- sysExit(p1); /* do not return */
- break;
-
- case TM_EXTSVC:
- /* INT tm_extsvc( INT fno, INT par1, INT par2, INT par3 ) */
- er = procExtSVC(p1, p2, p3, p4);
- break;
-
- default:
- er = E_PAR;
- }
-
- return er;
-}
diff --git a/tkernel_source/monitor/cmdsvc/src/wrkbuf.c b/tkernel_source/monitor/cmdsvc/src/wrkbuf.c
deleted file mode 100644
index 6742edd..0000000
--- a/tkernel_source/monitor/cmdsvc/src/wrkbuf.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * wrkbuf.c
- *
- * work buffer
- *
- * this is in an independent separate file so that we can specify the layout at link-time.
- * this is also used to store FlashROM writing program.
- *
- */
-
-#include "cmdsvc.h"
-
-EXPORT UB wrkBuf[WRKBUF_SZ];
diff --git a/tkernel_source/monitor/cmdsvc/svc.c b/tkernel_source/monitor/cmdsvc/svc.c
new file mode 100644
index 0000000..d252a76
--- /dev/null
+++ b/tkernel_source/monitor/cmdsvc/svc.c
@@ -0,0 +1,174 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * svc.c
+ *
+ * service call
+ */
+
+#include "cmdsvc.h"
+#include <sys/rominfo.h>
+
+/*
+ * submodule extended SVC function
+ * fno function code
+ * p1-p3 parameter(s)
+ * er returns error code
+ * return value if the function is handled, returns TRUE.
+ * if not, returns FALSE
+ */
+typedef BOOL (*ESVCFUNC)( W fno, W p1, W p2, W p3, W *er );
+
+/*
+ * use weak attribute to call only the linked submodule.
+ * `weak' is a gcc-specific function and so other methods (using "#if" for example) need to be employed with other compilers.
+ *
+ */
+#ifdef __GNUC__
+#define WEAK __attribute__ ((weak))
+#else
+#define WEAK
+#endif
+
+/*
+ * submodule
+ */
+IMPORT BOOL memDiskSVC( W fno, W p1, W p2, W p3, W *er ) WEAK;
+IMPORT BOOL pciSVC( W fno, W p1, W p2, W p3, W *er ) WEAK;
+IMPORT BOOL usbSVC( W fno, W p1, W p2, W p3, W *er ) WEAK;
+IMPORT BOOL sysExtSVC( W fno, W p1, W p2, W p3, W *er ) WEAK;
+
+char version[]="ot-kernel";
+
+/*
+ * calling submodule extended SVC function
+ */
+LOCAL BOOL callSubModuleSVC( ESVCFUNC func, W fno, W p1, W p2, W p3, W *er )
+{
+ if ( func == NULL ) return FALSE;
+
+ return (*func)(fno, p1, p2, p3, er);
+}
+
+#define CALL_ESVC(func) callSubModuleSVC(func, fno, p1, p2, p3, &er)
+
+/*
+ * extended service call processing
+ */
+LOCAL W procExtSVC( W fno, W p1, W p2, W p3 )
+{
+ W er;
+
+ switch ( fno ) {
+ case TMEF_PORTBPS: /* debug port speed (bps) */
+ er = ConPortBps;
+ break;
+
+ case TMEF_DIPSW: /* DIPSW status */
+ er = getDipSw();
+ break;
+
+ case TMEF_WROM: /* Flash ROM write */
+ er = writeFrom(p1, p2, p3, 0);
+ break;
+
+ default:
+ CALL_ESVC(sysExtSVC) ||
+ CALL_ESVC(usbSVC) ||
+ CALL_ESVC(pciSVC) ||
+ CALL_ESVC(memDiskSVC) ||
+ (er = E_PAR);
+ }
+
+ return er;
+}
+
+/* ------------------------------------------------------------------------ */
+
+/*
+ * service call
+ */
+EXPORT W procSVC( W fno, W p1, W p2, W p3, W p4 )
+{
+ W er = E_OK;
+ W n;
+
+ ret = svcmap[fno](fno, p1, p2, p3, p4);
+
+ switch ( fno ) {
+ case TM_MONITOR: /* void tm_monitor( void ) */
+ procCommand(NULL, 0);
+ break;
+
+ case TM_GETCHAR: /* INT tm_getchar( INT wait ) */
+ er = getChar(p1);
+ break;
+
+ case TM_PUTCHAR: /* INT tm_putchar( INT c ) */
+ er = putChar(p1);
+ break;
+
+ case TM_GETLINE: /* INT tm_getline( UB *buff ) */
+ er = getString(wrkBuf);
+ if ( er < 0 ) break;
+ n = er + 1;
+ if ( writeMem(p1, wrkBuf, n, 1) != n ) er = E_MACV;
+ break;
+
+ case TM_PUTSTRING: /* INT tm_putstring( const UB *buff ) */
+ n = readMemStr(p1, wrkBuf, WRKBUF_SZ);
+ if ( n < 0 ) { er = E_MACV; break; }
+ er = putString(wrkBuf);
+ break;
+
+ case TM_COMMAND: /* INT tm_command( const UB *buff ) */
+ n = readMemStr(p1, lineBuf, L_LINE);
+ if ( n < 0 ) { er = E_MACV; break; }
+ procCommand(( n == 0 )? NULL: lineBuf, 1);
+ break;
+
+ case TM_READDISK:
+ case TM_WRITEDISK:
+ case TM_INFODISK:
+ /* INT tm_readdisk( const UB *dev, INT sec, INT nsec, void *addr )
+ * INT tm_writedisk( const UB *dev, INT sec, INT nsec, void *addr )
+ * INT tm_infodisk( const UB *dev, INT *blksz, INT *nblks )
+ */
+ n = readMemStr(p1, lineBuf, L_LINE);
+ if ( n < 0 ) { er = E_MACV; break; }
+
+ if ( fno == TM_INFODISK ) {
+ er = infoDisk(lineBuf, (UW*)p2, (UW*)p3);
+ } else {
+ n = ( fno == TM_READDISK )? 0: 1;
+ er = rwDisk(lineBuf, p2, p3, (void*)p4, n);
+ }
+ break;
+
+ case TM_EXIT: /* void tm_exit( INT mode ) */
+ sysExit(p1); /* do not return */
+ break;
+
+ case TM_EXTSVC:
+ /* INT tm_extsvc( INT fno, INT par1, INT par2, INT par3 ) */
+ er = procExtSVC(p1, p2, p3, p4);
+ break;
+
+ default:
+ er = E_PAR;
+ }
+
+ return er;
+}
diff --git a/tkernel_source/monitor/cmdsvc/wrkbuf.c b/tkernel_source/monitor/cmdsvc/wrkbuf.c
new file mode 100644
index 0000000..6742edd
--- /dev/null
+++ b/tkernel_source/monitor/cmdsvc/wrkbuf.c
@@ -0,0 +1,27 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * wrkbuf.c
+ *
+ * work buffer
+ *
+ * this is in an independent separate file so that we can specify the layout at link-time.
+ * this is also used to store FlashROM writing program.
+ *
+ */
+
+#include "cmdsvc.h"
+
+EXPORT UB wrkBuf[WRKBUF_SZ];
diff --git a/tkernel_source/monitor/driver/flash/build/tef_em1d/Makefile b/tkernel_source/monitor/driver/flash/build/tef_em1d/Makefile
deleted file mode 100644
index d0000b8..0000000
--- a/tkernel_source/monitor/driver/flash/build/tef_em1d/Makefile
+++ /dev/null
@@ -1,89 +0,0 @@
-#
-# ----------------------------------------------------------------------
-# T-Kernel 2.0 Software Package
-#
-# Copyright 2011 by Ken Sakamura.
-# This software is distributed under the latest version of T-License 2.x.
-# ----------------------------------------------------------------------
-#
-# Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
-# Modified by T-Engine Forum at 2012/11/07.
-# Modified by T-Engine Forum at 2013/02/20.
-# Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
-#
-# ----------------------------------------------------------------------
-#
-
-# T-Monitor : flash (em1d)
-
-MACHINE = em1d
-TETYPE = tef
-
-SRC_SYSDEP = setup-em1d.c
-SRC_WR_SYSDEP = reset-em1d.c cfi_16x1.c cfi.c
-
-# ----------------------------------------------------------------------------
-
-DEPS = Dependencies
-DEPENDENCIES_OUTPUT := $(DEPS)
-
-include $(BD)/etc/makerules
-
-TMONITOR_INSTALLDIR = $(BD)/monitor/bin/$(TETYPE)_$(MACHINE)
-
-HEADER = $(BD)/include $(BD)/monitor/include
-
-# ----------------------------------------------------------------------------
-
-TARGET = flash
-
-S = ../../src
-
-VPATH = $(S)
-HEADER += $(S)
-
-SRC = main.c
-SRC += $(SRC_SYSDEP)
-SRC_WR =
-SRC_WR += $(SRC_WR_SYSDEP)
-
-OBJ = $(addsuffix .o, $(basename $(SRC)))
-OBJ_WR = $(addsuffix .o, $(basename $(SRC_WR)))
-
-CFLAGS += $(CFLAGS_WARNING)
-
-# adjust for flashwr object
-REN_SECTION = --rename-section .text=flashwr.text \
- --rename-section .rodata=flashwr.rodata
-KEEP_SYMBOL = --keep-global-symbol=flashwr \
- --keep-global-symbol=FROM_SECSZ
-
-# ----------------------------------------------------------------------------
-
-.PHONY: all clean install
-
-ALL = $(TARGET).o
-
-all: $(ALL)
-
-$(TARGET).o: $(OBJ) flashwr.o
- $(LINK_R.o) $^ $(OUTPUT_OPTION)
-
-flashwr.o: $(OBJ_WR)
- $(LINK_R.o) $^ -lgcc $(OUTPUT_OPTION)
- $(OBJCOPY) $(REN_SECTION) $(KEEP_SYMBOL) $@
-
-clean:
- $(RM) $(OBJ) $(OBJ_WR) flashwr.o $(ALL) $(DEPS)
-
-install: $(addprefix $(TMONITOR_INSTALLDIR)/, $(ALL))
-
-$(TMONITOR_INSTALLDIR)/%: %
- $(BD)/etc/backup_copy -t -d !OLD $< $(TMONITOR_INSTALLDIR)
-
-ifdef DEPENDENCIES_OUTPUT
- $(DEPS): ; touch $(DEPS)
-else
- $(DEPS): $(SRC) ; $(MAKEDEPS) $@ $?
-endif
--include $(DEPS)
diff --git a/tkernel_source/monitor/driver/flash/cfi.c b/tkernel_source/monitor/driver/flash/cfi.c
new file mode 100644
index 0000000..342eefa
--- /dev/null
+++ b/tkernel_source/monitor/driver/flash/cfi.c
@@ -0,0 +1,64 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * cfi.c
+ *
+ * CFI(Intel) Flash ROM specification
+ */
+
+#include "flash.h"
+
+/*
+ Flash ROM specification:
+ Intel 28F256P30B 32MB (256Mbits)
+ 32 KB x 4
+ 128 KB x 255
+
+ command:
+ ba: Block Addr, xa: Any Addr, sr: Status Reg, xsr: extend Status Reg.
+
+ Reset(Read Array):
+ xa<-FF
+ Block Erase:
+ ba<-20, xa<-D0, sr<-xa & check
+ Write (via Buffer 16 words):
+ ba<-E8, xsr<-xa & check, ba<-15(count), da<-data, ..
+ xa<-D0, sr<-xa & check
+ Write:
+ xa<-40(10), da<-data, sr<-xa & check
+ Read sr:
+ xa<-70, sr<-xa, if any error, xa<-50 (clear sr)
+ sr: b7:0x80 1:Ready, 0:busy
+ b5:0x20 1:Error Erase
+ b4:0x10 1:Error Set Lock-bit
+ b3:0x08 1:Low Voltage Error
+ b1:0x02 1:Locked
+ xsr:b7:0x80 1:WriteBuffer Available
+ Clear Lock-bits:
+ xa<-60, xa<-D0, sr<-xa & check
+ ID read:
+ xa<-90, man-id<- ba:0, dev-id <- ba:2
+ man-id: 89 Intel
+ dev-id: 001C 28F256P30B
+*/
+
+/*
+ * CFI(Intel) Flash ROM specification
+ */
+EXPORT const JEDEC_SPEC JedecSpec[] = {
+ { 0x0089, 0x001c, 0x0000, 0x0000, 32, 0, 0x8888, 0x8000 }, /* 28F256P30B */
+};
+
+EXPORT const W N_JedecSpec = sizeof(JedecSpec) / sizeof(JEDEC_SPEC);
diff --git a/tkernel_source/monitor/driver/flash/cfi_16x1.c b/tkernel_source/monitor/driver/flash/cfi_16x1.c
new file mode 100644
index 0000000..a89cff3
--- /dev/null
+++ b/tkernel_source/monitor/driver/flash/cfi_16x1.c
@@ -0,0 +1,199 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * cfi_16x1.c
+ *
+ * Flash ROM write: CFI(Intel) specification 16bit x 1 configuration
+ */
+
+#include "flash.h"
+
+#ifndef SECSZ
+#define SECSZ 0x20000 /* sector size 128kB x 1 */
+#endif
+
+#ifndef BSECSZ
+#define BSECSZ 0x02000 /* boot sector size 8KB x 1 */
+#endif
+
+#define SECMSK (SECSZ - 1) /* sector mask */
+
+#define MAX_RETRY (3) /* maximum number of retries */
+#define WAIT_CNT 0x10000000 /* wait count (enough time) */
+
+#define WBSZ (16) /* write buffer size (H unit) */
+
+EXPORT const UW FROM_SECSZ = SECSZ; /* sector size */
+
+/*
+ * check Flash ROM
+ */
+LOCAL const JEDEC_SPEC *checkFlashROM(_UH *rom)
+{
+ const JEDEC_SPEC *spec;
+ UH man, dev;
+ W i;
+
+ /* read Signature */
+ rom[0] = 0x0090;
+ man = rom[0] & 0x00ff; /* ignore upper 8 bits */
+ dev = rom[1] & 0x00ff; /* ignore upper 8 bits */
+
+ /* obtain Flash ROM specification */
+ for (i = 0; i < N_JedecSpec; ++i) {
+ spec = &JedecSpec[i];
+ if (spec->man != man || spec->dev != dev) continue;
+
+ return spec;
+ }
+
+ return NULL; /* unsupported target */
+}
+
+/*
+ * write one sector
+ * rom should be the beginning of sector
+ * if data = NULL, only erasure is performed
+ */
+LOCAL ER writesec(_UH *rom, UH *data, const JEDEC_SPEC *spec)
+{
+ _UH *rp, *xp;
+ UH *dp, *ep;
+ UH d;
+ UW n, mask, ptn;
+ W i;
+
+ mask = (spec->size * (1024*1024) - 1) & ~SECMSK;
+ n = (UW)rom & mask;
+
+ /* sector configuration */
+ ptn = ( n == 0 )? spec->bsec: /* bottm sector */
+ ( n == mask )? spec->tsec: /* top sector */
+ 0x8000; /* other */
+
+ /* erase sector */
+ mask = 0x10000;
+ for ( rp = rom; (ptn & (mask - 1)) != 0; rp += BSECSZ/sizeof(UH) ) {
+ if ( (ptn & (mask >>= 1)) == 0 ) continue;
+
+ /* wait for Ready */
+ *rp = 0x0070;
+ for (i = WAIT_CNT; --i >= 0 && (*rp & 0x0080) == 0; );
+ if (i < 0) return E_IO;
+
+ /* release lock */
+ *rp = 0x0060;
+ *rp = 0x00D0;
+
+ /* wait for Ready */
+ *rp = 0x0070;
+ for (i = WAIT_CNT; --i >= 0 && (*rp & 0x0080) == 0; );
+ if (i < 0) return E_IO;
+
+ /* erase sector */
+ *rp = 0x0020;
+ *rp = 0x00D0;
+
+ /* wait for completion of erasure */
+ for (i = WAIT_CNT; --i >= 0 && ((d = *rp) & 0x0080) == 0; );
+ if (i < 0 || (d & 0x003A) != 0) {
+ *rp = 0x0050; /* clear error */
+ return E_IO;
+ }
+ }
+
+ if (data == NULL) return E_OK; /* erase only */
+
+ /* write (using a buffer) */
+ rp = rom;
+ ep = data + SECSZ / sizeof(UH);
+ for (dp = data; dp < ep; ) {
+ xp = rp;
+ for (i = WAIT_CNT; --i >= 0; ) {
+ *rp = 0x00E8;
+ if (*xp & 0x0080) break; /* XSR check */
+ }
+ if (i < 0) goto abort;
+
+ *rp = WBSZ - 1;
+ for (i = 0; i < WBSZ; i++) *rp++ = *dp++;
+ *xp = 0x00D0;
+
+ /* wait for completion of write */
+ /* *xp = 0x0070; */
+ for (i = WAIT_CNT; --i >= 0 && ((d = *xp) & 0x0080) == 0; );
+ if (i < 0 || (d & 0x001A) != 0) {
+ *xp = 0x0050; /* clear error */
+ goto abort;
+ }
+ }
+
+ abort:
+ /* write end */
+ *rom = 0x00FF;
+ if (dp < ep) return E_IO;
+
+ /* Verify write */
+ for (dp = data; dp < ep; ) {
+ if (*rom ++ != *dp++) return E_IO;
+ }
+
+ return E_OK;
+}
+
+/*
+ * FlashROM write
+ */
+EXPORT ER flashwr(UW addr, void *data, W nsec, BOOL reset)
+{
+ const JEDEC_SPEC *spec;
+ _UH *rom;
+ W sec, retry;
+ ER err;
+
+ /* FlashROM sector address */
+ rom = (_UH *)NOCACHE_ADDR(addr & ~SECMSK);
+
+ /* check FlashROM */
+ spec = checkFlashROM(rom);
+
+ /* reset FlashROM */
+ *rom = 0x00FF;
+
+ /* report error for unsupported FlashROM */
+ if (spec == NULL) return E_IO;
+
+ /* erase or write in sector unit */
+ for (sec = 0; sec < nsec; sec++) {
+ retry = MAX_RETRY;
+
+ do {
+ err = writesec(rom, data, spec);
+ if (err >= E_OK) break;
+
+ /* firstly, reset */
+ *rom = 0x00FF;
+ } while (--retry > 0);
+
+ if (err < E_OK) return err;
+
+ rom = (_UH *)((B *)rom + SECSZ);
+ data = (B *)data + SECSZ;
+ }
+
+ if (reset) flashwr_reset(); /* do not return */
+
+ return E_OK;
+}
diff --git a/tkernel_source/monitor/driver/flash/flash.h b/tkernel_source/monitor/driver/flash/flash.h
new file mode 100644
index 0000000..ca537a2
--- /dev/null
+++ b/tkernel_source/monitor/driver/flash/flash.h
@@ -0,0 +1,81 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by T-Engine Forum at 2013/03/04.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * flash.h
+ *
+ * Flash ROM write processing
+ */
+
+#include <tmonitor.h>
+
+/* ------------------------------------------------------------------------ */
+
+/*
+ * JEDEC Flash ROM specification
+ * bsec, and tsec show the sector configuration of boot block.
+ * Ordinary sectors are divided into 8KB units, and
+ * lower address is mapped to MSB side (this is the bitwise mapping ) The leading bit of a sector is 1, and
+ * if this is a continued part of a sector, then it is 0.
+ *
+ * range
+ * bit15 0x00000 - 0x01fff
+ * bit14 0x02000 - 0x03fff
+ * bit13 0x04000 - 0x05fff
+ * bit12 0x06000 - 0x07fff
+ * : : :
+ * bit3 0x18000 - 0x19fff
+ * bit2 0x1a000 - 0x1bfff
+ * bit1 0x1c000 - 0x1dfff
+ * bit0 0x1e000 - 0x1ffff
+ *
+ * example: if sector size if 64KB, and boot block is configured as follows,
+ * address size
+ * 0x0000 32KB
+ * 0x8000 8KB
+ * 0xa000 8KB
+ * 0xc000 16KB
+ * the configured value is 1000_1110_0000_0000 (binary) = 0x8e00
+ */
+typedef struct {
+ UH man; /* manufacturer ID */
+ UH dev; /* device ID */
+ UH ex1; /* extended device ID 1 */
+ UH ex2; /* extended device ID 2 2 */
+ UH size; /* capacity (MB) */
+ UH wrmode:1; /* write mode */
+ UH bsec; /* bottom (low address) boot sector configuration */
+ UH tsec; /* top (upper address) boot sector configuration */
+} JEDEC_SPEC;
+
+/* write mode */
+#define JD_WRSINGLE 0 /* single write */
+#define JD_WRMULTI 1 /* multiple write (command 0x20) */
+
+IMPORT const JEDEC_SPEC JedecSpec[];
+IMPORT const W N_JedecSpec;
+
+/* ------------------------------------------------------------------------ */
+
+IMPORT const UW FROM_SECSZ; /* Flash ROM sector size (byte)
+ in the case of FWM, it is block size */
+/*
+ * function definition
+ */
+IMPORT ER flashwr( UW addr, void *data, W nsec, BOOL reset );
+IMPORT void flashwr_reset( void );
+IMPORT ER flashwr_protect( UW addr, W nsec );
+IMPORT void flashwr_setup( BOOL reset );
+IMPORT void flashwr_done( void );
diff --git a/tkernel_source/monitor/driver/flash/main.c b/tkernel_source/monitor/driver/flash/main.c
new file mode 100644
index 0000000..b0c6b6f
--- /dev/null
+++ b/tkernel_source/monitor/driver/flash/main.c
@@ -0,0 +1,159 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * main.c
+ *
+ * Flash ROM write processing
+ */
+
+#include "flash.h"
+
+IMPORT B __flashwr_org[], __flashwr_start[], __flashwr_end[];
+
+/*
+ * Flash ROM sector erase / write
+ * addr Flash ROM write start address (must be on a sector boundary)
+ * data write data start address (RAM)
+ * nsec number of sectors to write
+ * msg 0 : no message display no verify write
+ * 1 : message display with verify write
+ * -1 : message display no verify write
+ * return value error code
+ */
+EXPORT ER writeFrom( UW addr, UW data, W nsec, W msg )
+{
+ ER (* volatile flashwr_p)( UW addr, void *data, W nsec, BOOL reset );
+ BOOL reset;
+ W sz;
+ UB c;
+ ER er;
+
+ /* parameter check */
+ if ( nsec <= 0 ) return E_PAR;
+ if ( (addr & (FROM_SECSZ-1)) != 0 ) return E_PAR;
+ sz = FROM_SECSZ * nsec;
+ if ( !inMemArea(addr, addr + sz, MSA_FROM) ) return E_PAR;
+ if ( !inMemArea(data, data + sz, MSA_OS|MSA_ERAM|MSA_WRK) )
+ return E_PAR;
+
+ /* check the write-protect status */
+ er = flashwr_protect(addr, nsec);
+ if ( er < E_OK ) return er;
+
+ /* Confirm if monitor itself is to be written */
+ reset = isOverlapMemArea(addr, addr + sz, MSA_MON);
+ if ( reset && msg != 0 ) {
+ DSP_S("Update Monitor Area, ");
+ if (msg > 0) {
+ DSP_S("OK (y/n)? ");
+ c = (UB)getChar(1);
+ putChar(c);
+ putChar('\n');
+ if (c != 'Y' && c != 'y') return E_OK;
+ } else if (msg < 0) {
+ DSP_S("Restart System after Writing.");
+ }
+ }
+
+ /* initial set-up before Flash ROM write */
+ flashwr_setup(reset);
+
+ if ( __flashwr_start != __flashwr_org ) {
+ /* transfer flashwr() to RAM area */
+ memcpy(__flashwr_start, __flashwr_org,
+ __flashwr_end - __flashwr_start);
+ }
+
+ /* Flash ROM sector erase / write
+ * flashwr() is executed in RAM area.
+ * if reset = TRUE, doesn't return.
+ * The offset is too large, and so we use indirect address.
+ */
+ flashwr_p = &flashwr;
+ er = (*flashwr_p)(addr, (UH*)data, nsec, reset);
+
+ /* restore after Flash ROM write */
+ flashwr_done();
+
+ return er;
+}
+
+/*
+ * set up Flash ROM loading processing
+ * mode 0 : set up for loading write data
+ * -1 : set up for writing already loaded data
+ *
+ * in the case of setting up loading (mode= 0)
+ * addr returns the following value.
+ * addr[0] the start address in RAM area for loading data
+ * addr[1] the end address in RAM area for loading data
+ * addr[1] - addr[0] + 1 = load area size
+ * in principle, load area size matches the size of FLASH ROM.
+ * But if RAM is small, there may be cases
+ * in which load area size is smaller than that of Flash ROM size.
+ * addr[2] the distance between the data load RAM area and Flash ROM area
+ * adjustment is made so that the addr[0] position is written to the beginning of Flash ROM.
+ * addr[2] = addr[0] - Flash ROM start address
+ *
+ * in the case of setting up for writing (mode = -1),
+ * we set the writing area based on the addr value when we called this function using mode = 0.
+ * addr[0] starting address of loaded data in RAM area (to be written)
+ * addr[1] ending address of loaded data in RAM area (to be written)
+ * addr[1] - addr[0] + 1 = size of written data
+ * addr[2] the value remains the same after it was set by mode = 0 (ignored)
+ * the modified values are returned in addr.
+ * addr[0] Flash ROM write start address
+ * addr[1] start address of write data in RAM
+ * address will be adjusted to the sector boundary of Flash ROM.
+ * addr[2] number of sectors to write
+ * Since writing is done in the unit of sectors, the writing will be done from the sector boundary,
+ * areas immediately before and after the designated area may be part of the write operation.
+ */
+EXPORT void setupFlashLoad( W mode, UW addr[3] )
+{
+ UW SECMSK = FROM_SECSZ - 1;
+ UW ofs, sa, romsize, ramtop, ramend;
+ const MEMSEG *rom, *ram;
+
+ /* Flash ROM capacity */
+ rom = MemArea(MSA_FROM, 1);
+ romsize = rom->end - rom->top;
+
+ /* RAM area for writing */
+ ram = MemArea(MSA_OS|MSA_WRK, 1);
+ ramtop = (ram->top + SECMSK) & ~SECMSK;
+ ramend = ram->end & ~SECMSK;
+
+ /* Use the end of RAM area for working area
+ if we have enough RAM, we set aside the area as large as the last sector */
+ sa = (ramend - FROM_SECSZ) - romsize;
+ if ( sa < ramtop ) sa = ramtop;
+ ofs = sa - (UW)rom->top; /* the distance between the ROM area and RAM work area */
+
+ if ( mode >= 0 ) {
+ /* set up loading */
+ addr[0] = rom->top + ofs; /* RAM address lower limit */
+ addr[1] = rom->end + ofs - 1; /* RAM address upper limit */
+ addr[2] = ofs; /* offset */
+ if ( addr[1] >= ramend ) addr[1] = ramend - 1;
+ } else {
+ /* set up writing */
+ sa = addr[0] & ~SECMSK; /* RAM start address */
+ addr[2] = ((addr[1] & ~SECMSK) - sa) / FROM_SECSZ + 1;
+ /* number of sectors */
+ addr[1] = sa; /* RAM start address */
+ addr[0] = sa - ofs; /* ROM start address */
+ }
+}
diff --git a/tkernel_source/monitor/driver/flash/reset-em1d.c b/tkernel_source/monitor/driver/flash/reset-em1d.c
new file mode 100644
index 0000000..c8618b9
--- /dev/null
+++ b/tkernel_source/monitor/driver/flash/reset-em1d.c
@@ -0,0 +1,43 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * reset.c
+ *
+ * Reset and reboot after Flash ROM write
+ */
+
+#include "flash.h"
+#include <tk/sysdef.h>
+
+IMPORT void _start( void ); /* start address after reset */
+
+/*
+ * reset and reboot
+ */
+EXPORT void flashwr_reset( void )
+{
+#define PAGETBL_BASE (_UW *)0x30000000
+
+ void (* volatile reset_p)( void ) = 0;
+
+ /* Remap the NOR FlashROM area to its original space, and jump */
+ *PAGETBL_BASE = 0x9402; /* Strongly-order, Kernel/RO */
+ DSB();
+ Asm("mcr p15, 0, %0, cr8, cr7, 0":: "r"(0)); /* I/D TLB invalidate */
+ Asm("mcr p15, 0, %0, cr7, cr5, 6":: "r"(0)); /* invalidate BTC */
+ DSB();
+ ISB();
+ (*reset_p)(); /* call reset entry (does not return) */
+}
diff --git a/tkernel_source/monitor/driver/flash/setup-em1d.c b/tkernel_source/monitor/driver/flash/setup-em1d.c
new file mode 100644
index 0000000..e95e9c8
--- /dev/null
+++ b/tkernel_source/monitor/driver/flash/setup-em1d.c
@@ -0,0 +1,71 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * setup.c
+ *
+ * prepare for Flash ROM write
+ */
+
+#include "flash.h"
+
+EXPORT void ChangeMemAttr( UW top, UW end, UW attr );
+
+/* Update Flash ROM page table so that it can be written to. */
+LOCAL void flashwr_pagetable(BOOL writable)
+{
+ MEMSEG *mp;
+ UW attr;
+
+ mp = MemArea(MSA_FROM, 1);
+ attr = (writable) ? (PGA_RW | PGA_D | PGA_S) : (mp->pa & 0x000fffff);
+ ChangeMemAttr(mp->top, mp->end, attr);
+
+ return;
+}
+
+/*
+ * check Flash ROM write-protect status
+ * return value E_OK writable (OK)
+ * E_PROTECT write-protected
+ */
+EXPORT ER flashwr_protect( UW addr, W nsec )
+{
+ return E_OK;
+}
+
+/*
+ * set up Flash ROM write
+ */
+EXPORT void flashwr_setup( BOOL reset )
+{
+ /* invalidate cache
+ keep MMU enabled so that we can use WKRAM */
+ DisableCache();
+
+ /* page table is modified so that ROM area can be written to. */
+ flashwr_pagetable(TRUE);
+}
+
+/*
+ * post processing after Flash ROM write completed
+ */
+EXPORT void flashwr_done( void )
+{
+ /* restore the page table setting to the original. */
+ flashwr_pagetable(FALSE);
+
+ /* validate cache */
+ EnableCache();
+}
diff --git a/tkernel_source/monitor/driver/flash/src/cfi.c b/tkernel_source/monitor/driver/flash/src/cfi.c
deleted file mode 100644
index 342eefa..0000000
--- a/tkernel_source/monitor/driver/flash/src/cfi.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * cfi.c
- *
- * CFI(Intel) Flash ROM specification
- */
-
-#include "flash.h"
-
-/*
- Flash ROM specification:
- Intel 28F256P30B 32MB (256Mbits)
- 32 KB x 4
- 128 KB x 255
-
- command:
- ba: Block Addr, xa: Any Addr, sr: Status Reg, xsr: extend Status Reg.
-
- Reset(Read Array):
- xa<-FF
- Block Erase:
- ba<-20, xa<-D0, sr<-xa & check
- Write (via Buffer 16 words):
- ba<-E8, xsr<-xa & check, ba<-15(count), da<-data, ..
- xa<-D0, sr<-xa & check
- Write:
- xa<-40(10), da<-data, sr<-xa & check
- Read sr:
- xa<-70, sr<-xa, if any error, xa<-50 (clear sr)
- sr: b7:0x80 1:Ready, 0:busy
- b5:0x20 1:Error Erase
- b4:0x10 1:Error Set Lock-bit
- b3:0x08 1:Low Voltage Error
- b1:0x02 1:Locked
- xsr:b7:0x80 1:WriteBuffer Available
- Clear Lock-bits:
- xa<-60, xa<-D0, sr<-xa & check
- ID read:
- xa<-90, man-id<- ba:0, dev-id <- ba:2
- man-id: 89 Intel
- dev-id: 001C 28F256P30B
-*/
-
-/*
- * CFI(Intel) Flash ROM specification
- */
-EXPORT const JEDEC_SPEC JedecSpec[] = {
- { 0x0089, 0x001c, 0x0000, 0x0000, 32, 0, 0x8888, 0x8000 }, /* 28F256P30B */
-};
-
-EXPORT const W N_JedecSpec = sizeof(JedecSpec) / sizeof(JEDEC_SPEC);
diff --git a/tkernel_source/monitor/driver/flash/src/cfi_16x1.c b/tkernel_source/monitor/driver/flash/src/cfi_16x1.c
deleted file mode 100644
index a89cff3..0000000
--- a/tkernel_source/monitor/driver/flash/src/cfi_16x1.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * cfi_16x1.c
- *
- * Flash ROM write: CFI(Intel) specification 16bit x 1 configuration
- */
-
-#include "flash.h"
-
-#ifndef SECSZ
-#define SECSZ 0x20000 /* sector size 128kB x 1 */
-#endif
-
-#ifndef BSECSZ
-#define BSECSZ 0x02000 /* boot sector size 8KB x 1 */
-#endif
-
-#define SECMSK (SECSZ - 1) /* sector mask */
-
-#define MAX_RETRY (3) /* maximum number of retries */
-#define WAIT_CNT 0x10000000 /* wait count (enough time) */
-
-#define WBSZ (16) /* write buffer size (H unit) */
-
-EXPORT const UW FROM_SECSZ = SECSZ; /* sector size */
-
-/*
- * check Flash ROM
- */
-LOCAL const JEDEC_SPEC *checkFlashROM(_UH *rom)
-{
- const JEDEC_SPEC *spec;
- UH man, dev;
- W i;
-
- /* read Signature */
- rom[0] = 0x0090;
- man = rom[0] & 0x00ff; /* ignore upper 8 bits */
- dev = rom[1] & 0x00ff; /* ignore upper 8 bits */
-
- /* obtain Flash ROM specification */
- for (i = 0; i < N_JedecSpec; ++i) {
- spec = &JedecSpec[i];
- if (spec->man != man || spec->dev != dev) continue;
-
- return spec;
- }
-
- return NULL; /* unsupported target */
-}
-
-/*
- * write one sector
- * rom should be the beginning of sector
- * if data = NULL, only erasure is performed
- */
-LOCAL ER writesec(_UH *rom, UH *data, const JEDEC_SPEC *spec)
-{
- _UH *rp, *xp;
- UH *dp, *ep;
- UH d;
- UW n, mask, ptn;
- W i;
-
- mask = (spec->size * (1024*1024) - 1) & ~SECMSK;
- n = (UW)rom & mask;
-
- /* sector configuration */
- ptn = ( n == 0 )? spec->bsec: /* bottm sector */
- ( n == mask )? spec->tsec: /* top sector */
- 0x8000; /* other */
-
- /* erase sector */
- mask = 0x10000;
- for ( rp = rom; (ptn & (mask - 1)) != 0; rp += BSECSZ/sizeof(UH) ) {
- if ( (ptn & (mask >>= 1)) == 0 ) continue;
-
- /* wait for Ready */
- *rp = 0x0070;
- for (i = WAIT_CNT; --i >= 0 && (*rp & 0x0080) == 0; );
- if (i < 0) return E_IO;
-
- /* release lock */
- *rp = 0x0060;
- *rp = 0x00D0;
-
- /* wait for Ready */
- *rp = 0x0070;
- for (i = WAIT_CNT; --i >= 0 && (*rp & 0x0080) == 0; );
- if (i < 0) return E_IO;
-
- /* erase sector */
- *rp = 0x0020;
- *rp = 0x00D0;
-
- /* wait for completion of erasure */
- for (i = WAIT_CNT; --i >= 0 && ((d = *rp) & 0x0080) == 0; );
- if (i < 0 || (d & 0x003A) != 0) {
- *rp = 0x0050; /* clear error */
- return E_IO;
- }
- }
-
- if (data == NULL) return E_OK; /* erase only */
-
- /* write (using a buffer) */
- rp = rom;
- ep = data + SECSZ / sizeof(UH);
- for (dp = data; dp < ep; ) {
- xp = rp;
- for (i = WAIT_CNT; --i >= 0; ) {
- *rp = 0x00E8;
- if (*xp & 0x0080) break; /* XSR check */
- }
- if (i < 0) goto abort;
-
- *rp = WBSZ - 1;
- for (i = 0; i < WBSZ; i++) *rp++ = *dp++;
- *xp = 0x00D0;
-
- /* wait for completion of write */
- /* *xp = 0x0070; */
- for (i = WAIT_CNT; --i >= 0 && ((d = *xp) & 0x0080) == 0; );
- if (i < 0 || (d & 0x001A) != 0) {
- *xp = 0x0050; /* clear error */
- goto abort;
- }
- }
-
- abort:
- /* write end */
- *rom = 0x00FF;
- if (dp < ep) return E_IO;
-
- /* Verify write */
- for (dp = data; dp < ep; ) {
- if (*rom ++ != *dp++) return E_IO;
- }
-
- return E_OK;
-}
-
-/*
- * FlashROM write
- */
-EXPORT ER flashwr(UW addr, void *data, W nsec, BOOL reset)
-{
- const JEDEC_SPEC *spec;
- _UH *rom;
- W sec, retry;
- ER err;
-
- /* FlashROM sector address */
- rom = (_UH *)NOCACHE_ADDR(addr & ~SECMSK);
-
- /* check FlashROM */
- spec = checkFlashROM(rom);
-
- /* reset FlashROM */
- *rom = 0x00FF;
-
- /* report error for unsupported FlashROM */
- if (spec == NULL) return E_IO;
-
- /* erase or write in sector unit */
- for (sec = 0; sec < nsec; sec++) {
- retry = MAX_RETRY;
-
- do {
- err = writesec(rom, data, spec);
- if (err >= E_OK) break;
-
- /* firstly, reset */
- *rom = 0x00FF;
- } while (--retry > 0);
-
- if (err < E_OK) return err;
-
- rom = (_UH *)((B *)rom + SECSZ);
- data = (B *)data + SECSZ;
- }
-
- if (reset) flashwr_reset(); /* do not return */
-
- return E_OK;
-}
diff --git a/tkernel_source/monitor/driver/flash/src/flash.h b/tkernel_source/monitor/driver/flash/src/flash.h
deleted file mode 100644
index ca537a2..0000000
--- a/tkernel_source/monitor/driver/flash/src/flash.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by T-Engine Forum at 2013/03/04.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * flash.h
- *
- * Flash ROM write processing
- */
-
-#include <tmonitor.h>
-
-/* ------------------------------------------------------------------------ */
-
-/*
- * JEDEC Flash ROM specification
- * bsec, and tsec show the sector configuration of boot block.
- * Ordinary sectors are divided into 8KB units, and
- * lower address is mapped to MSB side (this is the bitwise mapping ) The leading bit of a sector is 1, and
- * if this is a continued part of a sector, then it is 0.
- *
- * range
- * bit15 0x00000 - 0x01fff
- * bit14 0x02000 - 0x03fff
- * bit13 0x04000 - 0x05fff
- * bit12 0x06000 - 0x07fff
- * : : :
- * bit3 0x18000 - 0x19fff
- * bit2 0x1a000 - 0x1bfff
- * bit1 0x1c000 - 0x1dfff
- * bit0 0x1e000 - 0x1ffff
- *
- * example: if sector size if 64KB, and boot block is configured as follows,
- * address size
- * 0x0000 32KB
- * 0x8000 8KB
- * 0xa000 8KB
- * 0xc000 16KB
- * the configured value is 1000_1110_0000_0000 (binary) = 0x8e00
- */
-typedef struct {
- UH man; /* manufacturer ID */
- UH dev; /* device ID */
- UH ex1; /* extended device ID 1 */
- UH ex2; /* extended device ID 2 2 */
- UH size; /* capacity (MB) */
- UH wrmode:1; /* write mode */
- UH bsec; /* bottom (low address) boot sector configuration */
- UH tsec; /* top (upper address) boot sector configuration */
-} JEDEC_SPEC;
-
-/* write mode */
-#define JD_WRSINGLE 0 /* single write */
-#define JD_WRMULTI 1 /* multiple write (command 0x20) */
-
-IMPORT const JEDEC_SPEC JedecSpec[];
-IMPORT const W N_JedecSpec;
-
-/* ------------------------------------------------------------------------ */
-
-IMPORT const UW FROM_SECSZ; /* Flash ROM sector size (byte)
- in the case of FWM, it is block size */
-/*
- * function definition
- */
-IMPORT ER flashwr( UW addr, void *data, W nsec, BOOL reset );
-IMPORT void flashwr_reset( void );
-IMPORT ER flashwr_protect( UW addr, W nsec );
-IMPORT void flashwr_setup( BOOL reset );
-IMPORT void flashwr_done( void );
diff --git a/tkernel_source/monitor/driver/flash/src/main.c b/tkernel_source/monitor/driver/flash/src/main.c
deleted file mode 100644
index b0c6b6f..0000000
--- a/tkernel_source/monitor/driver/flash/src/main.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * main.c
- *
- * Flash ROM write processing
- */
-
-#include "flash.h"
-
-IMPORT B __flashwr_org[], __flashwr_start[], __flashwr_end[];
-
-/*
- * Flash ROM sector erase / write
- * addr Flash ROM write start address (must be on a sector boundary)
- * data write data start address (RAM)
- * nsec number of sectors to write
- * msg 0 : no message display no verify write
- * 1 : message display with verify write
- * -1 : message display no verify write
- * return value error code
- */
-EXPORT ER writeFrom( UW addr, UW data, W nsec, W msg )
-{
- ER (* volatile flashwr_p)( UW addr, void *data, W nsec, BOOL reset );
- BOOL reset;
- W sz;
- UB c;
- ER er;
-
- /* parameter check */
- if ( nsec <= 0 ) return E_PAR;
- if ( (addr & (FROM_SECSZ-1)) != 0 ) return E_PAR;
- sz = FROM_SECSZ * nsec;
- if ( !inMemArea(addr, addr + sz, MSA_FROM) ) return E_PAR;
- if ( !inMemArea(data, data + sz, MSA_OS|MSA_ERAM|MSA_WRK) )
- return E_PAR;
-
- /* check the write-protect status */
- er = flashwr_protect(addr, nsec);
- if ( er < E_OK ) return er;
-
- /* Confirm if monitor itself is to be written */
- reset = isOverlapMemArea(addr, addr + sz, MSA_MON);
- if ( reset && msg != 0 ) {
- DSP_S("Update Monitor Area, ");
- if (msg > 0) {
- DSP_S("OK (y/n)? ");
- c = (UB)getChar(1);
- putChar(c);
- putChar('\n');
- if (c != 'Y' && c != 'y') return E_OK;
- } else if (msg < 0) {
- DSP_S("Restart System after Writing.");
- }
- }
-
- /* initial set-up before Flash ROM write */
- flashwr_setup(reset);
-
- if ( __flashwr_start != __flashwr_org ) {
- /* transfer flashwr() to RAM area */
- memcpy(__flashwr_start, __flashwr_org,
- __flashwr_end - __flashwr_start);
- }
-
- /* Flash ROM sector erase / write
- * flashwr() is executed in RAM area.
- * if reset = TRUE, doesn't return.
- * The offset is too large, and so we use indirect address.
- */
- flashwr_p = &flashwr;
- er = (*flashwr_p)(addr, (UH*)data, nsec, reset);
-
- /* restore after Flash ROM write */
- flashwr_done();
-
- return er;
-}
-
-/*
- * set up Flash ROM loading processing
- * mode 0 : set up for loading write data
- * -1 : set up for writing already loaded data
- *
- * in the case of setting up loading (mode= 0)
- * addr returns the following value.
- * addr[0] the start address in RAM area for loading data
- * addr[1] the end address in RAM area for loading data
- * addr[1] - addr[0] + 1 = load area size
- * in principle, load area size matches the size of FLASH ROM.
- * But if RAM is small, there may be cases
- * in which load area size is smaller than that of Flash ROM size.
- * addr[2] the distance between the data load RAM area and Flash ROM area
- * adjustment is made so that the addr[0] position is written to the beginning of Flash ROM.
- * addr[2] = addr[0] - Flash ROM start address
- *
- * in the case of setting up for writing (mode = -1),
- * we set the writing area based on the addr value when we called this function using mode = 0.
- * addr[0] starting address of loaded data in RAM area (to be written)
- * addr[1] ending address of loaded data in RAM area (to be written)
- * addr[1] - addr[0] + 1 = size of written data
- * addr[2] the value remains the same after it was set by mode = 0 (ignored)
- * the modified values are returned in addr.
- * addr[0] Flash ROM write start address
- * addr[1] start address of write data in RAM
- * address will be adjusted to the sector boundary of Flash ROM.
- * addr[2] number of sectors to write
- * Since writing is done in the unit of sectors, the writing will be done from the sector boundary,
- * areas immediately before and after the designated area may be part of the write operation.
- */
-EXPORT void setupFlashLoad( W mode, UW addr[3] )
-{
- UW SECMSK = FROM_SECSZ - 1;
- UW ofs, sa, romsize, ramtop, ramend;
- const MEMSEG *rom, *ram;
-
- /* Flash ROM capacity */
- rom = MemArea(MSA_FROM, 1);
- romsize = rom->end - rom->top;
-
- /* RAM area for writing */
- ram = MemArea(MSA_OS|MSA_WRK, 1);
- ramtop = (ram->top + SECMSK) & ~SECMSK;
- ramend = ram->end & ~SECMSK;
-
- /* Use the end of RAM area for working area
- if we have enough RAM, we set aside the area as large as the last sector */
- sa = (ramend - FROM_SECSZ) - romsize;
- if ( sa < ramtop ) sa = ramtop;
- ofs = sa - (UW)rom->top; /* the distance between the ROM area and RAM work area */
-
- if ( mode >= 0 ) {
- /* set up loading */
- addr[0] = rom->top + ofs; /* RAM address lower limit */
- addr[1] = rom->end + ofs - 1; /* RAM address upper limit */
- addr[2] = ofs; /* offset */
- if ( addr[1] >= ramend ) addr[1] = ramend - 1;
- } else {
- /* set up writing */
- sa = addr[0] & ~SECMSK; /* RAM start address */
- addr[2] = ((addr[1] & ~SECMSK) - sa) / FROM_SECSZ + 1;
- /* number of sectors */
- addr[1] = sa; /* RAM start address */
- addr[0] = sa - ofs; /* ROM start address */
- }
-}
diff --git a/tkernel_source/monitor/driver/flash/src/reset-em1d.c b/tkernel_source/monitor/driver/flash/src/reset-em1d.c
deleted file mode 100644
index c8618b9..0000000
--- a/tkernel_source/monitor/driver/flash/src/reset-em1d.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * reset.c
- *
- * Reset and reboot after Flash ROM write
- */
-
-#include "flash.h"
-#include <tk/sysdef.h>
-
-IMPORT void _start( void ); /* start address after reset */
-
-/*
- * reset and reboot
- */
-EXPORT void flashwr_reset( void )
-{
-#define PAGETBL_BASE (_UW *)0x30000000
-
- void (* volatile reset_p)( void ) = 0;
-
- /* Remap the NOR FlashROM area to its original space, and jump */
- *PAGETBL_BASE = 0x9402; /* Strongly-order, Kernel/RO */
- DSB();
- Asm("mcr p15, 0, %0, cr8, cr7, 0":: "r"(0)); /* I/D TLB invalidate */
- Asm("mcr p15, 0, %0, cr7, cr5, 6":: "r"(0)); /* invalidate BTC */
- DSB();
- ISB();
- (*reset_p)(); /* call reset entry (does not return) */
-}
diff --git a/tkernel_source/monitor/driver/flash/src/setup-em1d.c b/tkernel_source/monitor/driver/flash/src/setup-em1d.c
deleted file mode 100644
index e95e9c8..0000000
--- a/tkernel_source/monitor/driver/flash/src/setup-em1d.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * setup.c
- *
- * prepare for Flash ROM write
- */
-
-#include "flash.h"
-
-EXPORT void ChangeMemAttr( UW top, UW end, UW attr );
-
-/* Update Flash ROM page table so that it can be written to. */
-LOCAL void flashwr_pagetable(BOOL writable)
-{
- MEMSEG *mp;
- UW attr;
-
- mp = MemArea(MSA_FROM, 1);
- attr = (writable) ? (PGA_RW | PGA_D | PGA_S) : (mp->pa & 0x000fffff);
- ChangeMemAttr(mp->top, mp->end, attr);
-
- return;
-}
-
-/*
- * check Flash ROM write-protect status
- * return value E_OK writable (OK)
- * E_PROTECT write-protected
- */
-EXPORT ER flashwr_protect( UW addr, W nsec )
-{
- return E_OK;
-}
-
-/*
- * set up Flash ROM write
- */
-EXPORT void flashwr_setup( BOOL reset )
-{
- /* invalidate cache
- keep MMU enabled so that we can use WKRAM */
- DisableCache();
-
- /* page table is modified so that ROM area can be written to. */
- flashwr_pagetable(TRUE);
-}
-
-/*
- * post processing after Flash ROM write completed
- */
-EXPORT void flashwr_done( void )
-{
- /* restore the page table setting to the original. */
- flashwr_pagetable(FALSE);
-
- /* validate cache */
- EnableCache();
-}
diff --git a/tkernel_source/monitor/driver/memdisk/build/tef_em1d/Makefile b/tkernel_source/monitor/driver/memdisk/build/tef_em1d/Makefile
deleted file mode 100644
index 524e982..0000000
--- a/tkernel_source/monitor/driver/memdisk/build/tef_em1d/Makefile
+++ /dev/null
@@ -1,75 +0,0 @@
-#
-# ----------------------------------------------------------------------
-# T-Kernel 2.0 Software Package
-#
-# Copyright 2011 by Ken Sakamura.
-# This software is distributed under the latest version of T-License 2.x.
-# ----------------------------------------------------------------------
-#
-# Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
-# Modified by T-Engine Forum at 2012/11/07.
-# Modified by T-Engine Forum at 2013/02/20.
-# Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
-#
-# ----------------------------------------------------------------------
-#
-
-# T-Monitor : memdisk (em1d)
-
-MACHINE = em1d
-TETYPE = tef
-
-SRC_SYSDEP =
-
-# ----------------------------------------------------------------------------
-
-DEPS = Dependencies
-DEPENDENCIES_OUTPUT := $(DEPS)
-
-include $(BD)/etc/makerules
-
-TMONITOR_INSTALLDIR = $(BD)/monitor/bin/$(TETYPE)_$(MACHINE)
-
-HEADER = $(BD)/include $(BD)/monitor/include
-
-# ----------------------------------------------------------------------------
-
-TARGET = memdisk
-
-S = ../../src
-
-VPATH = $(S)
-HEADER += $(S)
-
-SRC = memdsk.c
-SRC += $(SRC_SYSDEP)
-
-OBJ = $(addsuffix .o, $(basename $(SRC)))
-
-CFLAGS += $(CFLAGS_WARNING)
-
-# ----------------------------------------------------------------------------
-
-.PHONY: all clean install
-
-ALL = $(TARGET).o
-
-all: $(ALL)
-
-$(TARGET).o: $(OBJ)
- $(LINK_R.o) $^ $(OUTPUT_OPTION)
-
-clean:
- $(RM) $(OBJ) $(ALL) $(DEPS)
-
-install: $(addprefix $(TMONITOR_INSTALLDIR)/, $(ALL))
-
-$(TMONITOR_INSTALLDIR)/%: %
- $(BD)/etc/backup_copy -t -d !OLD $< $(TMONITOR_INSTALLDIR)
-
-ifdef DEPENDENCIES_OUTPUT
- $(DEPS): ; touch $(DEPS)
-else
- $(DEPS): $(SRC) ; $(MAKEDEPS) $@ $?
-endif
--include $(DEPS)
diff --git a/tkernel_source/monitor/driver/memdisk/memdsk.c b/tkernel_source/monitor/driver/memdisk/memdsk.c
new file mode 100644
index 0000000..91746d1
--- /dev/null
+++ b/tkernel_source/monitor/driver/memdisk/memdsk.c
@@ -0,0 +1,163 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * memdsk.c
+ *
+ * memory disk
+ */
+
+#include <tmonitor.h>
+#include <tm/tmonitor.h>
+#include <sys/rominfo.h>
+
+/*
+ * memory disk information
+ * Use the ROM disk information in ROM info as the starting point.
+ */
+typedef struct {
+ UW rd_type; /* disk type */
+ UW rd_blksz; /* disk block size */
+ UW rd_saddr; /* disk start address */
+ UW rd_eaddr; /* disk end address */
+} MDINFO;
+
+/*
+ * disk types
+ */
+#define ROMDISK 1
+
+/* ------------------------------------------------------------------------ */
+
+/*
+ * submodule extended SVC function
+ * fno function code
+ * p1-p3 parameter(s)
+ * er_p returns error code
+ * return value if the function is handled, returns TRUE.
+ * if not, returns FALSE
+ */
+EXPORT BOOL memDiskSVC( W fno, W p1, W p2, W p3, W *er_p )
+{
+ MDINFO *mdi;
+ UW type;
+ W er, n, v;
+
+ switch ( fno ) {
+ case TMEF_RDAINFO: /* ROM disk information */
+ mdi = (MDINFO*)&ROMInfo->rd_type;
+ type = ROMDISK;
+ goto info;
+
+ info:
+ if ( mdi->rd_blksz > 0 && mdi->rd_type == type ) {
+ v = (UW)mdi;
+ n = writeMem(p1, &v, sizeof(W), sizeof(W));
+ er = ( n == sizeof(W) )? E_OK: E_MACV;
+ } else {
+ er = E_NOEXS;
+ }
+ break;
+
+ default:
+ return FALSE; /* unsupported */
+ }
+
+ *er_p = er;
+ return TRUE;
+}
+
+/* ------------------------------------------------------------------------ */
+
+/*
+ * I/O functions
+ * blk start block number
+ * this is not a block number within a partition, but
+ * it is a disk-wide block number unique inside the whole disk.
+ * nblk number of blocks
+ * buf buffer (* )
+ * wrt FALSE : read
+ * TRUE : write
+ * return value error code
+ * argument marked with (* ) may be an address specified from external sources.
+ */
+LOCAL ER rwdisk( DISKCB *dcb, W blk, W nblk, void *buf, BOOL wrt )
+{
+ MDINFO *mdi = (MDINFO*)dcb->info;
+ W sz, asz;
+ void *adr;
+
+ if ( dcb->blksz <= 0 ) return E_NOEXS; /* not yet initialized */
+
+ adr = (void*)(mdi->rd_saddr + blk * dcb->blksz);
+ sz = nblk * dcb->blksz;
+
+ if ( wrt ) {
+ /* write */
+ if ( mdi->rd_type == ROMDISK ) return E_RONLY;
+ asz = readMem((UW)buf, adr, sz, 1);
+ } else {
+ /* read */
+ asz = writeMem((UW)buf, adr, sz, 1);
+ }
+ if ( asz < sz ) return E_IO;
+
+ return E_OK;
+}
+
+/*
+ * initialization processing
+ * disk drive that is supported by the initialization by CFGDISK
+ * disk drive is initialized and DISKCB is set up.
+ * DISKCB is given in 0-cleared state initially. Subsequently,
+ * DISKCB returned in the previous call is passed.
+ * I/O function receives this DISKCB.
+ *
+ * In principle, this function is called every time an I/O processing is performed.
+ * Hence, there is no need to perform hardware initialization on the second call and afterward.
+ * but whether the hardware status remains as it was the last time the initialization took place is not guaranteed,
+ * so,
+ * it is desirable to initialize hardware from time to as necessary.
+ * If we perform re-initialization, DISKCB is to be re-initialized.
+ */
+EXPORT ER initMemDisk( DISKCB *dcb, const CFGDISK *cfg )
+{
+ MDINFO *mdi;
+ UW type;
+
+ if ( dcb->blksz > 0 ) return E_OK; /* already initialized */
+
+ /* select the target disk */
+ switch ( cfg->info ) {
+ case 0: /* ROM disk */
+ mdi = (MDINFO*)&ROMInfo->rd_type;
+ type = ROMDISK;
+ break;
+
+ default:
+ return E_PAR;
+ }
+
+ if ( mdi->rd_blksz <= 0 || mdi->rd_type != type ) return E_NOEXS;
+
+ /* set up disk drive control block (DISKCB) */
+ memset(dcb, 0, sizeof(DISKCB));
+ dcb->info = (UW)mdi;
+ dcb->blksz = mdi->rd_blksz;
+ dcb->part[0].sblk = 0;
+ dcb->part[0].nblk = (mdi->rd_eaddr - mdi->rd_saddr) / mdi->rd_blksz;
+ dcb->rwdisk = rwdisk;
+
+ return E_OK;
+}
diff --git a/tkernel_source/monitor/driver/memdisk/src/memdsk.c b/tkernel_source/monitor/driver/memdisk/src/memdsk.c
deleted file mode 100644
index 91746d1..0000000
--- a/tkernel_source/monitor/driver/memdisk/src/memdsk.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * memdsk.c
- *
- * memory disk
- */
-
-#include <tmonitor.h>
-#include <tm/tmonitor.h>
-#include <sys/rominfo.h>
-
-/*
- * memory disk information
- * Use the ROM disk information in ROM info as the starting point.
- */
-typedef struct {
- UW rd_type; /* disk type */
- UW rd_blksz; /* disk block size */
- UW rd_saddr; /* disk start address */
- UW rd_eaddr; /* disk end address */
-} MDINFO;
-
-/*
- * disk types
- */
-#define ROMDISK 1
-
-/* ------------------------------------------------------------------------ */
-
-/*
- * submodule extended SVC function
- * fno function code
- * p1-p3 parameter(s)
- * er_p returns error code
- * return value if the function is handled, returns TRUE.
- * if not, returns FALSE
- */
-EXPORT BOOL memDiskSVC( W fno, W p1, W p2, W p3, W *er_p )
-{
- MDINFO *mdi;
- UW type;
- W er, n, v;
-
- switch ( fno ) {
- case TMEF_RDAINFO: /* ROM disk information */
- mdi = (MDINFO*)&ROMInfo->rd_type;
- type = ROMDISK;
- goto info;
-
- info:
- if ( mdi->rd_blksz > 0 && mdi->rd_type == type ) {
- v = (UW)mdi;
- n = writeMem(p1, &v, sizeof(W), sizeof(W));
- er = ( n == sizeof(W) )? E_OK: E_MACV;
- } else {
- er = E_NOEXS;
- }
- break;
-
- default:
- return FALSE; /* unsupported */
- }
-
- *er_p = er;
- return TRUE;
-}
-
-/* ------------------------------------------------------------------------ */
-
-/*
- * I/O functions
- * blk start block number
- * this is not a block number within a partition, but
- * it is a disk-wide block number unique inside the whole disk.
- * nblk number of blocks
- * buf buffer (* )
- * wrt FALSE : read
- * TRUE : write
- * return value error code
- * argument marked with (* ) may be an address specified from external sources.
- */
-LOCAL ER rwdisk( DISKCB *dcb, W blk, W nblk, void *buf, BOOL wrt )
-{
- MDINFO *mdi = (MDINFO*)dcb->info;
- W sz, asz;
- void *adr;
-
- if ( dcb->blksz <= 0 ) return E_NOEXS; /* not yet initialized */
-
- adr = (void*)(mdi->rd_saddr + blk * dcb->blksz);
- sz = nblk * dcb->blksz;
-
- if ( wrt ) {
- /* write */
- if ( mdi->rd_type == ROMDISK ) return E_RONLY;
- asz = readMem((UW)buf, adr, sz, 1);
- } else {
- /* read */
- asz = writeMem((UW)buf, adr, sz, 1);
- }
- if ( asz < sz ) return E_IO;
-
- return E_OK;
-}
-
-/*
- * initialization processing
- * disk drive that is supported by the initialization by CFGDISK
- * disk drive is initialized and DISKCB is set up.
- * DISKCB is given in 0-cleared state initially. Subsequently,
- * DISKCB returned in the previous call is passed.
- * I/O function receives this DISKCB.
- *
- * In principle, this function is called every time an I/O processing is performed.
- * Hence, there is no need to perform hardware initialization on the second call and afterward.
- * but whether the hardware status remains as it was the last time the initialization took place is not guaranteed,
- * so,
- * it is desirable to initialize hardware from time to as necessary.
- * If we perform re-initialization, DISKCB is to be re-initialized.
- */
-EXPORT ER initMemDisk( DISKCB *dcb, const CFGDISK *cfg )
-{
- MDINFO *mdi;
- UW type;
-
- if ( dcb->blksz > 0 ) return E_OK; /* already initialized */
-
- /* select the target disk */
- switch ( cfg->info ) {
- case 0: /* ROM disk */
- mdi = (MDINFO*)&ROMInfo->rd_type;
- type = ROMDISK;
- break;
-
- default:
- return E_PAR;
- }
-
- if ( mdi->rd_blksz <= 0 || mdi->rd_type != type ) return E_NOEXS;
-
- /* set up disk drive control block (DISKCB) */
- memset(dcb, 0, sizeof(DISKCB));
- dcb->info = (UW)mdi;
- dcb->blksz = mdi->rd_blksz;
- dcb->part[0].sblk = 0;
- dcb->part[0].nblk = (mdi->rd_eaddr - mdi->rd_saddr) / mdi->rd_blksz;
- dcb->rwdisk = rwdisk;
-
- return E_OK;
-}
diff --git a/tkernel_source/monitor/driver/sio/build/tef_em1d/Makefile b/tkernel_source/monitor/driver/sio/build/tef_em1d/Makefile
deleted file mode 100644
index 42b48c6..0000000
--- a/tkernel_source/monitor/driver/sio/build/tef_em1d/Makefile
+++ /dev/null
@@ -1,75 +0,0 @@
-#
-# ----------------------------------------------------------------------
-# T-Kernel 2.0 Software Package
-#
-# Copyright 2011 by Ken Sakamura.
-# This software is distributed under the latest version of T-License 2.x.
-# ----------------------------------------------------------------------
-#
-# Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
-# Modified by T-Engine Forum at 2012/11/07.
-# Modified by T-Engine Forum at 2013/02/20.
-# Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
-#
-# ----------------------------------------------------------------------
-#
-
-# T-Monitor : sio (em1d)
-
-MACHINE = em1d
-TETYPE = tef
-
-SRC_SYSDEP = ns16550.c
-
-# ----------------------------------------------------------------------------
-
-DEPS = Dependencies
-DEPENDENCIES_OUTPUT := $(DEPS)
-
-include $(BD)/etc/makerules
-
-TMONITOR_INSTALLDIR = $(BD)/monitor/bin/$(TETYPE)_$(MACHINE)
-
-HEADER = $(BD)/include $(BD)/monitor/include
-
-# ----------------------------------------------------------------------------
-
-TARGET = sio
-
-S = ../../src
-
-VPATH = $(S)
-HEADER += $(S)
-
-SRC =
-SRC += $(SRC_SYSDEP)
-
-OBJ = $(addsuffix .o, $(basename $(SRC)))
-
-CFLAGS += $(CFLAGS_WARNING)
-
-# ----------------------------------------------------------------------------
-
-.PHONY: all clean install
-
-ALL = $(TARGET).o
-
-all: $(ALL)
-
-$(TARGET).o: $(OBJ)
- $(LINK_R.o) $^ $(OUTPUT_OPTION)
-
-clean:
- $(RM) $(OBJ) $(ALL) $(DEPS)
-
-install: $(addprefix $(TMONITOR_INSTALLDIR)/, $(ALL))
-
-$(TMONITOR_INSTALLDIR)/%: %
- $(BD)/etc/backup_copy -t -d !OLD $< $(TMONITOR_INSTALLDIR)
-
-ifdef DEPENDENCIES_OUTPUT
- $(DEPS): ; touch $(DEPS)
-else
- $(DEPS): $(SRC) ; $(MAKEDEPS) $@ $?
-endif
--include $(DEPS)
diff --git a/tkernel_source/monitor/driver/sio/ns16550.c b/tkernel_source/monitor/driver/sio/ns16550.c
new file mode 100644
index 0000000..12c16b0
--- /dev/null
+++ b/tkernel_source/monitor/driver/sio/ns16550.c
@@ -0,0 +1,294 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by T-Engine Forum at 2013/02/28.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * ns16550.c
+ *
+ * serial port I/O
+ */
+
+#include <tmonitor.h>
+
+/*
+ * serial port hardware configuration definition
+ */
+typedef struct {
+ UW iob; /* I/O base address */
+} DEFSIO;
+
+#if 0
+# define IOSTEP /* I/O address separation */
+# define CLOCK /* input clock (Hz) */
+
+/* ----------------------------------------------------------------------- */
+#elif _TEF_EM1D_
+# include <arm/em1d512.h>
+ LOCAL const DEFSIO DefSIO[3] = {
+ { UARTnBase(UART0) },
+ { UARTnBase(UART1) },
+ { UARTnBase(UART2) },
+ };
+# define IOSTEP 4
+# define CLOCK 229376000
+
+/* Unlike ordinary 16550, all registers exist and are independently accessed.
+ * (No overlaid meaning/behavior per read or write, or switching of register sets is necessary.
+ * also, 16-bits read/write to data register while FIFO is enabled causes two character input/output.) */
+
+#define UART(n) ( IOB + (n) * IOSTEP )
+#define regDATA UART(0) /* data register (RW) */
+#define regINTE UART(1) /* interrupt enable register (RW) */
+#define regINTS UART(2) /* interrupt selection register(R ) */
+#define regFCTL UART(3) /* FIFO control register (RW) */
+#define regLCTL UART(4) /* line control register (RW) */
+#define regMCTL UART(5) /* model control register (RW) */
+#define regLSTS UART(6) /* line status register (R ) */
+#define regMSTS UART(7) /* modem status register (R ) */
+#define regSCRA UART(8) /* scratch data register (RW) */
+#define regDIVL UART(9) /* divisor lower bits (RW) */
+#define regDIVH UART(10) /* divisor upper bits (RW) */
+/* ----------------------------------------------------------------------- */
+#endif
+
+#define N_DEFSIO ( sizeof(DefSIO) / sizeof(DEFSIO) )
+
+/* ------------------------------------------------------------------------ */
+
+#define IOB ( scb->info ) /* I/O base address */
+
+#if !defined(IN)
+#define IN(x) in_b(x)
+#define OUT(x, y) out_b((x), (y))
+#endif
+
+/*
+ * definition of 16550
+ * Every access is byte access.
+ */
+#if !defined(UART)
+#define UART(n) ( IOB + (n) * IOSTEP )
+#define regDATA UART(0) /* data register (RW) */
+#define regINTE UART(1) /* interrupt enable register (RW) */
+#define regINTS UART(2) /* interrupt selection register(R ) */
+#define regFCTL UART(2) /* FIFO control register ( W) */
+#define regLCTL UART(3) /* line control register (RW) */
+#define regMCTL UART(4) /* modem control register (RW) */
+#define regLSTS UART(5) /* line status register (R ) */
+#define regMSTS UART(6) /* modem status register (R ) */
+#define regSCRA UART(7) /* scratch data register (RW) */
+#define regDIVL UART(0) /* divisor lower bits (RW) */
+#define regDIVH UART(1) /* divisor upper bits (RW) */
+#endif
+
+/* transmission speed -> divided counter value. */
+#define LC_LINE_SPEED(bps) (CLOCK / 16 / (bps))
+
+/* line control register */
+#define LC_DLAB 0x80 /* (divided) counter access */
+#define LC_SBRK 0x40 /* send BREAK */
+#define LC_SNDP 0x20 /* with parity */
+#define LC_EVNP 0x10 /* even parity */
+#define LC_ENAP 0x08 /* enable parity */
+#define LC_STOP 0x04 /* stop bit */
+#define LC_BLEN 0x03 /* number of bits in data */
+
+/* default : 8 bits data, one bit stop, and no parity. */
+#define dtLC (0x03)
+
+/* line status register */
+#define LS_TSRE 0x40 /* transmission shift register empty */
+#define LS_THRE 0x20 /* transmission hold register empty */
+#define LS_BINT 0x10 /* BREAK received */
+#define LS_FERR 0x08 /* framing error */
+#define LS_PERR 0x04 /* parity error */
+#define LS_OERR 0x02 /* overrun error */
+#define LS_DRDY 0x01 /* received data ready */
+
+#define LS_RxERR (LS_BINT|LS_FERR|LS_PERR|LS_OERR)
+
+/* modem control register */
+#define MC_OUT2 0x08 /* auxiliary output #2 (enable interrupt) */
+#define MC_OUT1 0x04 /* auxiliary output #1 */
+#define MC_RTS 0x02 /* Request To Send */
+#define MC_DTR 0x01 /* Data Terminal Ready */
+
+/* default : disable interrupt */
+#define dtMC (MC_RTS | MC_DTR)
+
+/* modem status register */
+#define MS_CD 0x80 /* Data Carrier Detect */
+#define MS_RI 0x40 /* Ring Indicate */
+#define MS_DR 0x20 /* Data Set Ready */
+#define MS_CS 0x10 /* Clear To Send */
+#define MS_D_CD 0x08 /* change of CD detected */
+#define MS_D_RI 0x04 /* change of RI detected */
+#define MS_D_DR 0x02 /* change of DR detected */
+#define MS_D_CS 0x01 /* change of CS detected */
+
+/* interrupt enable register */
+#define IM_MSTS 0x08 /* modem state interrupt */
+#define IM_LSTS 0x04 /* receive line state interrupt */
+#define IM_SND 0x02 /* send ready interrupt */
+#define IM_RCV 0x01 /* input data ready interrupt */
+
+/* default : all interrupts are disabled */
+#define dtIM (0x00)
+
+/* interrupt selection register */
+#define IS_PEND 0x01 /* interrupt is pending */
+#define IS_ID 0x0e /* interrupt ID */
+#define IS_CTMO 0x0c /* ID=6 timeout interrupt */
+#define IS_LSTS 0x06 /* ID=3 receive line state interrupt. */
+#define IS_RCV 0x04 /* ID=2 input data ready interupt */
+#define IS_SND 0x02 /* ID=1 send ready interrupt */
+#define IS_MSTS 0x00 /* ID=0 modem state interrupt */
+#define IS_FIFO 0xc0 /* FIFO is in use */
+
+/* FIFO control register */
+#define FC_TL01 0x00 /* receive interrupt threshold ( 1 byte ) */
+#define FC_TL04 0x40 /* receive threshold 4 byte */
+#define FC_TL08 0x80 /* receive interrupt thereshold 8 byte */
+#define FC_TL14 0xc0 /* receive interrupt threshold 14 byte */
+#define FC_TXCLR 0x04 /* clear trasnmission FIFO */
+#define FC_RXCLR 0x02 /* receive FIFO clear. */
+#if _TEF_EM1D_
+#define FC_FIFO 0x21 /* enable 64 bytes FIFO */
+#define FIFO_SIZE 64 /* FIFO size */
+#define dtFC (FC_FIFO | FC_TL14) /* default */
+#else
+#define FC_FIFO 0x01 /* enable FIFO */
+#define FIFO_SIZE 16 /* FIFO size */
+#define dtFC (FC_FIFO | FC_TL08) /* default */
+#endif
+
+/* default : enable FIFO, 8 byte threshold */
+#define dtFC_CLR (FC_FIFO | FC_TXCLR | FC_RXCLR) /* clear */
+
+/* ------------------------------------------------------------------------ */
+
+/*
+ * Power on RS-232C driver IC
+ */
+#define RSDRV_PWON(siocb) /* no operation */
+
+/*
+ * serial port I/O
+ */
+LOCAL void putSIO_16550( SIOCB *scb, UB c )
+{
+ RSDRV_PWON(scb);
+
+ /* wait until transmission is ready. */
+ while ((IN(regLSTS) & LS_THRE) == 0);
+
+ /* write transmission data */
+ OUT(regDATA, c);
+
+ /* wait until the completion of transmission */
+ while ((IN(regLSTS) & LS_THRE) == 0);
+}
+
+/*
+ * serial port input
+ * tmo timeout (milliseconds)
+ * You can not wait forever.
+ * return value >= 0 : character code
+ * -1 : timeout
+ * input data using buffer.
+ * receive error is ignored.
+ */
+LOCAL W getSIO_16550(SIOCB *scb, W tmo )
+{
+ W sts, c = 0;
+
+ RSDRV_PWON();
+
+ tmo *= 1000/20; /* convert tmo to 20 usec units */
+
+ /* receive as much data as possible in the receive buffer */
+ while (scb->iptr - scb->optr < SIO_RCVBUFSZ) {
+
+ /* is there data in FIFO? */
+ if ( !((sts = IN(regLSTS)) & (LS_DRDY | LS_RxERR))) {
+ if (scb->iptr != scb->optr) break; /* already received */
+ if (tmo-- <= 0) break; /* timeout */
+ waitUsec(20);
+ continue;
+ }
+
+ /* receive data input */
+ if (sts & LS_DRDY) c = IN(regDATA);
+
+ /* error check */
+ if (sts & LS_RxERR) continue;
+
+ /* set data to rcvbuf */
+ scb->rcvbuf[scb->iptr++ & SIO_PTRMSK] = c;
+ }
+
+ /* return the data in rcvbuf */
+ return (scb->iptr == scb->optr)?
+ -1 : scb->rcvbuf[scb->optr++ & SIO_PTRMSK];
+}
+
+/* ------------------------------------------------------------------------ */
+
+/*
+ * initialize serial port
+ * serial port that is supported by the initialization of CFGSIO
+ * speed communication speed (bps)
+ * initialize the serial port according to the specified parameters and set SIOCB
+ * SIOCB is given in 0-cleared state initially.
+ * Subsequent I/O operations uses the SIOCB.
+ *
+ * Only for PC/AT version
+ * if speed = 0, we use the value in biosp->siomode.
+ * But we use only the transmission speed and other settings are ignored.
+ * Efforts were made to be compatible B-right/V, but because of the ignorance of no-speed settings such as data length and stop bit length,
+ * we have reduced functionality.
+ */
+EXPORT ER initSIO_ns16550(SIOCB *scb, const CFGSIO *csio, W speed)
+{
+ UH div;
+
+ if ( (UW)csio->info >= N_DEFSIO ) return E_PAR;
+
+ /* select the target port */
+ scb->info = DefSIO[csio->info].iob;
+
+ /* communicatin speed default value */
+ div = LC_LINE_SPEED(speed);
+
+ /* initialize serial controller */
+ IN(regLSTS); /* clear IS_LSTS */
+ IN(regINTS); /* clear IS_SND */
+ IN(regMSTS); /* clear IS_MSTS */
+
+ OUT(regLCTL, LC_DLAB);
+ OUT(regDIVL, 0xff); /* to keep the following from happening, Div = 0 */
+ OUT(regDIVH, div >> 8); /* communication speed */
+ OUT(regDIVL, div & 0xff);
+ OUT(regLCTL, dtLC); /* line mode */
+ OUT(regFCTL, dtFC_CLR); /* clear FIFO */
+ OUT(regFCTL, dtFC); /* FIFO mode */
+ OUT(regMCTL, dtMC); /* modem mode */
+ OUT(regINTE, dtIM); /* interrupt mask */
+
+ /* I/O function default */
+ scb->put = putSIO_16550;
+ scb->get = getSIO_16550;
+
+ return E_OK;
+}
diff --git a/tkernel_source/monitor/driver/sio/src/ns16550.c b/tkernel_source/monitor/driver/sio/src/ns16550.c
deleted file mode 100644
index 12c16b0..0000000
--- a/tkernel_source/monitor/driver/sio/src/ns16550.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by T-Engine Forum at 2013/02/28.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * ns16550.c
- *
- * serial port I/O
- */
-
-#include <tmonitor.h>
-
-/*
- * serial port hardware configuration definition
- */
-typedef struct {
- UW iob; /* I/O base address */
-} DEFSIO;
-
-#if 0
-# define IOSTEP /* I/O address separation */
-# define CLOCK /* input clock (Hz) */
-
-/* ----------------------------------------------------------------------- */
-#elif _TEF_EM1D_
-# include <arm/em1d512.h>
- LOCAL const DEFSIO DefSIO[3] = {
- { UARTnBase(UART0) },
- { UARTnBase(UART1) },
- { UARTnBase(UART2) },
- };
-# define IOSTEP 4
-# define CLOCK 229376000
-
-/* Unlike ordinary 16550, all registers exist and are independently accessed.
- * (No overlaid meaning/behavior per read or write, or switching of register sets is necessary.
- * also, 16-bits read/write to data register while FIFO is enabled causes two character input/output.) */
-
-#define UART(n) ( IOB + (n) * IOSTEP )
-#define regDATA UART(0) /* data register (RW) */
-#define regINTE UART(1) /* interrupt enable register (RW) */
-#define regINTS UART(2) /* interrupt selection register(R ) */
-#define regFCTL UART(3) /* FIFO control register (RW) */
-#define regLCTL UART(4) /* line control register (RW) */
-#define regMCTL UART(5) /* model control register (RW) */
-#define regLSTS UART(6) /* line status register (R ) */
-#define regMSTS UART(7) /* modem status register (R ) */
-#define regSCRA UART(8) /* scratch data register (RW) */
-#define regDIVL UART(9) /* divisor lower bits (RW) */
-#define regDIVH UART(10) /* divisor upper bits (RW) */
-/* ----------------------------------------------------------------------- */
-#endif
-
-#define N_DEFSIO ( sizeof(DefSIO) / sizeof(DEFSIO) )
-
-/* ------------------------------------------------------------------------ */
-
-#define IOB ( scb->info ) /* I/O base address */
-
-#if !defined(IN)
-#define IN(x) in_b(x)
-#define OUT(x, y) out_b((x), (y))
-#endif
-
-/*
- * definition of 16550
- * Every access is byte access.
- */
-#if !defined(UART)
-#define UART(n) ( IOB + (n) * IOSTEP )
-#define regDATA UART(0) /* data register (RW) */
-#define regINTE UART(1) /* interrupt enable register (RW) */
-#define regINTS UART(2) /* interrupt selection register(R ) */
-#define regFCTL UART(2) /* FIFO control register ( W) */
-#define regLCTL UART(3) /* line control register (RW) */
-#define regMCTL UART(4) /* modem control register (RW) */
-#define regLSTS UART(5) /* line status register (R ) */
-#define regMSTS UART(6) /* modem status register (R ) */
-#define regSCRA UART(7) /* scratch data register (RW) */
-#define regDIVL UART(0) /* divisor lower bits (RW) */
-#define regDIVH UART(1) /* divisor upper bits (RW) */
-#endif
-
-/* transmission speed -> divided counter value. */
-#define LC_LINE_SPEED(bps) (CLOCK / 16 / (bps))
-
-/* line control register */
-#define LC_DLAB 0x80 /* (divided) counter access */
-#define LC_SBRK 0x40 /* send BREAK */
-#define LC_SNDP 0x20 /* with parity */
-#define LC_EVNP 0x10 /* even parity */
-#define LC_ENAP 0x08 /* enable parity */
-#define LC_STOP 0x04 /* stop bit */
-#define LC_BLEN 0x03 /* number of bits in data */
-
-/* default : 8 bits data, one bit stop, and no parity. */
-#define dtLC (0x03)
-
-/* line status register */
-#define LS_TSRE 0x40 /* transmission shift register empty */
-#define LS_THRE 0x20 /* transmission hold register empty */
-#define LS_BINT 0x10 /* BREAK received */
-#define LS_FERR 0x08 /* framing error */
-#define LS_PERR 0x04 /* parity error */
-#define LS_OERR 0x02 /* overrun error */
-#define LS_DRDY 0x01 /* received data ready */
-
-#define LS_RxERR (LS_BINT|LS_FERR|LS_PERR|LS_OERR)
-
-/* modem control register */
-#define MC_OUT2 0x08 /* auxiliary output #2 (enable interrupt) */
-#define MC_OUT1 0x04 /* auxiliary output #1 */
-#define MC_RTS 0x02 /* Request To Send */
-#define MC_DTR 0x01 /* Data Terminal Ready */
-
-/* default : disable interrupt */
-#define dtMC (MC_RTS | MC_DTR)
-
-/* modem status register */
-#define MS_CD 0x80 /* Data Carrier Detect */
-#define MS_RI 0x40 /* Ring Indicate */
-#define MS_DR 0x20 /* Data Set Ready */
-#define MS_CS 0x10 /* Clear To Send */
-#define MS_D_CD 0x08 /* change of CD detected */
-#define MS_D_RI 0x04 /* change of RI detected */
-#define MS_D_DR 0x02 /* change of DR detected */
-#define MS_D_CS 0x01 /* change of CS detected */
-
-/* interrupt enable register */
-#define IM_MSTS 0x08 /* modem state interrupt */
-#define IM_LSTS 0x04 /* receive line state interrupt */
-#define IM_SND 0x02 /* send ready interrupt */
-#define IM_RCV 0x01 /* input data ready interrupt */
-
-/* default : all interrupts are disabled */
-#define dtIM (0x00)
-
-/* interrupt selection register */
-#define IS_PEND 0x01 /* interrupt is pending */
-#define IS_ID 0x0e /* interrupt ID */
-#define IS_CTMO 0x0c /* ID=6 timeout interrupt */
-#define IS_LSTS 0x06 /* ID=3 receive line state interrupt. */
-#define IS_RCV 0x04 /* ID=2 input data ready interupt */
-#define IS_SND 0x02 /* ID=1 send ready interrupt */
-#define IS_MSTS 0x00 /* ID=0 modem state interrupt */
-#define IS_FIFO 0xc0 /* FIFO is in use */
-
-/* FIFO control register */
-#define FC_TL01 0x00 /* receive interrupt threshold ( 1 byte ) */
-#define FC_TL04 0x40 /* receive threshold 4 byte */
-#define FC_TL08 0x80 /* receive interrupt thereshold 8 byte */
-#define FC_TL14 0xc0 /* receive interrupt threshold 14 byte */
-#define FC_TXCLR 0x04 /* clear trasnmission FIFO */
-#define FC_RXCLR 0x02 /* receive FIFO clear. */
-#if _TEF_EM1D_
-#define FC_FIFO 0x21 /* enable 64 bytes FIFO */
-#define FIFO_SIZE 64 /* FIFO size */
-#define dtFC (FC_FIFO | FC_TL14) /* default */
-#else
-#define FC_FIFO 0x01 /* enable FIFO */
-#define FIFO_SIZE 16 /* FIFO size */
-#define dtFC (FC_FIFO | FC_TL08) /* default */
-#endif
-
-/* default : enable FIFO, 8 byte threshold */
-#define dtFC_CLR (FC_FIFO | FC_TXCLR | FC_RXCLR) /* clear */
-
-/* ------------------------------------------------------------------------ */
-
-/*
- * Power on RS-232C driver IC
- */
-#define RSDRV_PWON(siocb) /* no operation */
-
-/*
- * serial port I/O
- */
-LOCAL void putSIO_16550( SIOCB *scb, UB c )
-{
- RSDRV_PWON(scb);
-
- /* wait until transmission is ready. */
- while ((IN(regLSTS) & LS_THRE) == 0);
-
- /* write transmission data */
- OUT(regDATA, c);
-
- /* wait until the completion of transmission */
- while ((IN(regLSTS) & LS_THRE) == 0);
-}
-
-/*
- * serial port input
- * tmo timeout (milliseconds)
- * You can not wait forever.
- * return value >= 0 : character code
- * -1 : timeout
- * input data using buffer.
- * receive error is ignored.
- */
-LOCAL W getSIO_16550(SIOCB *scb, W tmo )
-{
- W sts, c = 0;
-
- RSDRV_PWON();
-
- tmo *= 1000/20; /* convert tmo to 20 usec units */
-
- /* receive as much data as possible in the receive buffer */
- while (scb->iptr - scb->optr < SIO_RCVBUFSZ) {
-
- /* is there data in FIFO? */
- if ( !((sts = IN(regLSTS)) & (LS_DRDY | LS_RxERR))) {
- if (scb->iptr != scb->optr) break; /* already received */
- if (tmo-- <= 0) break; /* timeout */
- waitUsec(20);
- continue;
- }
-
- /* receive data input */
- if (sts & LS_DRDY) c = IN(regDATA);
-
- /* error check */
- if (sts & LS_RxERR) continue;
-
- /* set data to rcvbuf */
- scb->rcvbuf[scb->iptr++ & SIO_PTRMSK] = c;
- }
-
- /* return the data in rcvbuf */
- return (scb->iptr == scb->optr)?
- -1 : scb->rcvbuf[scb->optr++ & SIO_PTRMSK];
-}
-
-/* ------------------------------------------------------------------------ */
-
-/*
- * initialize serial port
- * serial port that is supported by the initialization of CFGSIO
- * speed communication speed (bps)
- * initialize the serial port according to the specified parameters and set SIOCB
- * SIOCB is given in 0-cleared state initially.
- * Subsequent I/O operations uses the SIOCB.
- *
- * Only for PC/AT version
- * if speed = 0, we use the value in biosp->siomode.
- * But we use only the transmission speed and other settings are ignored.
- * Efforts were made to be compatible B-right/V, but because of the ignorance of no-speed settings such as data length and stop bit length,
- * we have reduced functionality.
- */
-EXPORT ER initSIO_ns16550(SIOCB *scb, const CFGSIO *csio, W speed)
-{
- UH div;
-
- if ( (UW)csio->info >= N_DEFSIO ) return E_PAR;
-
- /* select the target port */
- scb->info = DefSIO[csio->info].iob;
-
- /* communicatin speed default value */
- div = LC_LINE_SPEED(speed);
-
- /* initialize serial controller */
- IN(regLSTS); /* clear IS_LSTS */
- IN(regINTS); /* clear IS_SND */
- IN(regMSTS); /* clear IS_MSTS */
-
- OUT(regLCTL, LC_DLAB);
- OUT(regDIVL, 0xff); /* to keep the following from happening, Div = 0 */
- OUT(regDIVH, div >> 8); /* communication speed */
- OUT(regDIVL, div & 0xff);
- OUT(regLCTL, dtLC); /* line mode */
- OUT(regFCTL, dtFC_CLR); /* clear FIFO */
- OUT(regFCTL, dtFC); /* FIFO mode */
- OUT(regMCTL, dtMC); /* modem mode */
- OUT(regINTE, dtIM); /* interrupt mask */
-
- /* I/O function default */
- scb->put = putSIO_16550;
- scb->get = getSIO_16550;
-
- return E_OK;
-}
diff --git a/tkernel_source/monitor/hwdepend/arm/cpu/break.c b/tkernel_source/monitor/hwdepend/arm/cpu/break.c
new file mode 100644
index 0000000..fc1bed7
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/cpu/break.c
@@ -0,0 +1,560 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * break.c
+ *
+ * break/trace processing (after ARMv6)
+ */
+
+#include "../cmdsvc.h"
+#include <sys/sysinfo.h>
+
+/* SW breakpoint code (BKPT instruction) */
+#define BREAK_ARM 0xE1200070
+#define BREAK_THUMB 0xBE000000
+
+/*
+ breakpoint data
+*/
+typedef struct {
+ UW addr; /* break address */
+ UW code; /* saved data */
+ UW atr; /* break attribute */
+ H sz; /* code size (2 or 4) */
+ UB cmd[L_BPCMD]; /* executed command */
+} BRKPT;
+
+#define MAX_SBP (8) /* maximum number of SW breakpoint */
+#define MAX_IBP (0)
+#define MAX_OBP (0)
+#define MAX_BRKPT (MAX_SBP + MAX_IBP + MAX_OBP)
+
+LOCAL BRKPT brkPt[MAX_BRKPT + 1]; /* breakpoint data */
+ /* the last is temorary break */
+
+/*
+ step point data
+ * used for trace and temporary step processing
+*/
+typedef struct {
+ UW addr; /* step address */
+ UW code; /* step save data */
+ UW pc; /* address of replaced instruction */
+ UW inst; /* replaced instruction */
+ UW regval; /* replaced register value */
+ H reg; /* replaced register number */
+ H sz; /* code size ( 2 / 4) */
+} STEPPT;
+
+LOCAL STEPPT stepPt; /* step point data */
+
+/*
+ break attribute
+*/
+#define BA_S 0x1000 /* software break */
+#define BA_I 0x2000 /* instruction break */
+#define BA_O 0x4000 /* operand break */
+#define BA_SET 0x8000 /* software break released flag */
+#define BA_PRE 0x0100 /* break before execution */
+#define BA_R 0x0200 /* break on read */
+#define BA_W 0x0400 /* break on write */
+#define BA_RW 0x0600 /* break on read/write */
+#define BA_TMP 0x0800 /* temporary break */
+
+#define MAX_BPATR 1
+
+LOCAL const struct {
+ UB name[4]; /* attribute name */
+ UW atr; /* attribute code */
+} brkAtr[MAX_BPATR] = {
+ {"S ", 0x00000000 | BA_S | BA_PRE}, /* software break */
+};
+
+/*
+ trace data
+*/
+LOCAL W traceMode; /* trace mode */
+LOCAL W traceStep; /* number of trace steps */
+LOCAL W stepFlg; /* temporary step execution flag */
+LOCAL union {
+ UB b[8];
+ UW w[2]; /* to align on word boundary */
+ } sbpCode; /* SW break instructions (two) */
+
+/*
+ CP14 register manipulation
+*/
+/* no debug comprocessor */
+LOCAL void setDSCR(UW val) {return;}
+LOCAL UW getDSCR(void) {return 0;}
+LOCAL UW getWFAR(void) {return 0;}
+LOCAL void setBVR(W num, UW val) {return;}
+LOCAL void setBCR(W num, UW val) {return;}
+LOCAL UW getBCR(W num) {return 0;}
+LOCAL void setWVR(W num, UW val) {return;}
+LOCAL void setWCR(W num, UW val) {return;}
+LOCAL UW getWCR(W num) {return 0;}
+
+/*
+ check CP14 monitor debug mode
+*/
+LOCAL UW CheckCP14(void)
+{
+ return getDSCR() & 0x00008000;
+}
+/*
+ set CP14 monitor debug mode
+*/
+LOCAL UW EnableCP14(void)
+{
+ UW dscr;
+
+ dscr = getDSCR();
+ dscr |= 0x00008000; /* monitor debug mode on */
+ dscr &= ~0x00004000; /* hold debug mode off */
+ setDSCR(dscr);
+
+ /* return the success/failure of setting */
+ return CheckCP14();
+}
+/*
+ reset CP14 monitor debug mode
+*/
+LOCAL void DisableCP14(void)
+{
+ setDSCR(getDSCR() & ~0x00008000);
+ return;
+}
+/*
+ extract break attribute
+*/
+EXPORT W getBreakAtr(UB *name)
+{
+ W i;
+
+ if (name[4] == ' ') {
+ for (i = 0; i < MAX_BPATR; i++) {
+ if (memcmp(brkAtr[i].name, name, sizeof(UW)) == 0)
+ return brkAtr[i].atr;
+ }
+ }
+ return E_BPATR;
+}
+/*
+ extract break attribute string (fixed length: 4 characters)
+*/
+LOCAL UB *strBreakAtr(W atr)
+{
+ W i;
+static UB str[5];
+
+ atr &= ~BA_SET;
+
+ for (i = 0; i < MAX_BPATR; i++) {
+ if (brkAtr[i].atr == atr) {
+ memcpy(str, brkAtr[i].name, 4);
+ for (i = 4; str[--i] == ' '; );
+ str[i + 1] = '\0';
+ return str;
+ }
+ }
+ return NULL;
+}
+/*
+ set breakpoint
+*/
+EXPORT ER setBreak(UW addr, W atr, UB *cmd, W cmdlen)
+{
+ W ibcnt, obcnt, sbcnt, sz;
+ UW code;
+ BRKPT *bp, *p;
+
+ if (atr == 0) atr = BA_S | BA_PRE; /* default attribute */
+
+ /* unaligned address (non-W alignment) is regarded as Thumb instruction */
+ sz = (addr & 0x03) ? 2 : 4;
+ addr &= ~(sz - 1);
+
+ if (atr & BA_TMP) { /* temporary break is used at fixed location */
+ bp = &brkPt[MAX_BRKPT];
+ } else {
+ /* find an empty slot in the table */
+ ibcnt = obcnt = sbcnt = 0;
+ for (bp = NULL, p = brkPt; p < &brkPt[MAX_BRKPT]; p++) {
+ if (p->addr == 0) {if (bp == NULL) bp = p;} /* empty */
+ else if (p->addr == addr) bp = p; /* update */
+ else if (p->atr & BA_O) obcnt++; /* WP */
+ else if (p->atr & BA_I) ibcnt++; /* HW BP */
+ else sbcnt++; /* SW BP */
+ }
+ /* check for the maximum value */
+ if (atr & BA_O) {
+ if (obcnt >= MAX_OBP) return E_HBPOVR;
+ } else if (atr & BA_I) {
+ if (ibcnt >= MAX_IBP) return E_HBPOVR;
+ } else {
+ if (sbcnt >= MAX_SBP) return E_SBPOVR;
+ }
+ }
+
+ if (atr & BA_S) {
+ /* validate PC */
+ /* if (invalidPC(addr)) return E_BPBAD; */
+
+ /*check for read and and write access rights */
+ if (readMem(addr, &code, sz, 2) != sz) return E_BPBAD;
+ if (writeMem(addr, &sbpCode.b[sz], sz, 2) != sz) return E_BPROM;
+ writeMem(addr, &code, sz, 2);
+ } else {
+ code = 0;
+ }
+
+ /*set breakpoint */
+ bp->addr = addr;
+ bp->atr = atr | BA_SET;
+ bp->sz = sz;
+ bp->code = code;
+ memset(bp->cmd, 0, L_BPCMD);
+ if (cmdlen > 0) memcpy(bp->cmd, cmd, cmdlen);
+ return E_OK;
+}
+/*
+ clear breakpoint
+*/
+EXPORT ER clearBreak(UW addr)
+{
+ BRKPT *p;
+
+ if (addr == 0) { /* clear all breakpoints */
+ memset(&brkPt[0], 0, sizeof(brkPt));
+ return E_OK;
+ }
+ for (p = brkPt; p < &brkPt[MAX_BRKPT]; p++) {
+ if (p->addr && p->addr == (addr & ~(p->sz - 1))) {
+ memset(p, 0, sizeof(BRKPT));
+ return E_OK;
+ }
+ }
+ return E_BPUDF;
+}
+/*
+ list all breakpoints
+*/
+EXPORT void dspBreak(void)
+{
+ BRKPT *p;
+
+ for (p = brkPt; p < &brkPt[MAX_BRKPT]; p++) {
+ if (p->addr == 0) continue;
+ /* THUMB(sz == 2) is displayed using odd address */
+ DSP_F3(08X,(p->addr + ((p->sz & 2) >> 1)), CH,' ',
+ S,strBreakAtr(p->atr));
+ if (p->cmd[0] != '\0') {
+ DSP_F3(S," \"", S,p->cmd, CH,'"');
+ }
+ DSP_LF;
+ }
+}
+/*
+ initialize breakpoint
+*/
+EXPORT void initBreak(void)
+{
+ /* clear all breakpoints */
+ memset(&brkPt[0], 0, sizeof(brkPt));
+
+ /* clear all step points */
+ memset(&stepPt, 0, sizeof(stepPt));
+
+ /* initialize others, */
+ traceMode = traceStep = stepFlg = 0;
+
+ /* SW break instruction (undefined instruction) */
+ sbpCode.w[0] = BREAK_THUMB;
+ sbpCode.w[1] = BREAK_ARM;
+}
+/*
+ release breakpoint temporarily (monitor entry)
+*/
+EXPORT W resetBreak(UW vec)
+{
+ W i, n, bpflg;
+ UW code, pc;
+ BRKPT *p;
+
+ pc = getCurPCX(); /* break address has been adjusted */
+ bpflg = 0;
+
+ /* release if monitor debug mode is used */
+ if (CheckCP14()) {
+ /* release hardware breakpoint */
+ for (i = 0; i < MAX_IBP; i++) {
+ setBCR(i, getBCR(i) & ~1);
+ }
+
+ /* release watchpoint */
+ for (i = 0; i < MAX_OBP; i++) {
+ setWCR(i, getWCR(i) & ~1);
+ }
+
+ /* monitor debug mode is set to off later */
+ }
+
+ /* release steppoints */
+ if (stepPt.addr != 0) {
+ n = stepPt.sz;
+ readMem(stepPt.addr, &code, n, 2);
+ if (memcmp(&code, &sbpCode.b[n], n) == 0) {
+ if (pc == stepPt.addr) bpflg = 0x100;
+ writeMem(stepPt.addr, &stepPt.code, n, 2);
+ if (stepPt.pc > 0) {
+ /* restore the changed instruction (ARM instruction only) */
+ writeMem(stepPt.pc, &stepPt.inst, 4, 2);
+ /* restore the changed register */
+ pc = getRegister(stepPt.reg);
+ setRegister(stepPt.reg, stepPt.regval);
+ }
+ /* set the NEXT real PC */
+ if (bpflg != 0) setCurPCX(pc);
+ }
+ }
+
+ /* in the case of trace/step execution, SW breakpoints have been released */
+ if (! (traceMode || stepFlg)) {
+
+ /* temporaly release SW/HW breakpoints (including the temporary breakpoints) */
+ for (p = brkPt; p <= &brkPt[MAX_BRKPT]; p++) {
+ if (p->addr == 0) continue;
+
+ if (p->atr & BA_O) {
+ if (vec == EIT_DDEBUG)
+ bpflg = (p - brkPt) | 0x10;
+ } else if (p->atr & BA_I) {
+ if (pc == p->addr)
+ bpflg = (p - brkPt) | 0x10;
+ } else {
+ readMem(p->addr, &code, n = p->sz, 2);
+ if (memcmp(&code, &sbpCode.b[n], n) == 0) {
+ if (pc == p->addr)
+ bpflg = (p - brkPt) | 0x10;
+ writeMem(p->addr, &p->code, n, 2);
+ p->atr |= BA_SET;
+ } else {
+ p->atr &= ~BA_SET;
+ }
+ /* clear temporary breakpoint */
+ if (p->atr & BA_TMP)
+ memset(p, 0, sizeof(BRKPT));
+ }
+ }
+ }
+ return bpflg; /* is PC breakpoint? */
+}
+/*
+ setting step
+*/
+LOCAL void setStep(UW pc, W mode)
+{
+ W n;
+ UW cpsr, inst;
+
+ /* ARM or THUMB */
+ cpsr = getCurCPSR();
+
+ /* decode instruction and obtain the next branch target */
+ n = getStepAddr(pc, cpsr, (mode == 2) ? 1 : 0, &stepPt.addr, &inst);
+
+ if (n >= 0x10) { /* instruction modification */
+ /* modify instruction (ARM instruction only) */
+ readMem(stepPt.pc = pc, &stepPt.inst, 4, 2);
+ writeMem(pc, &inst, 4, 2);
+ /* restore the changed register */
+ stepPt.reg = (n >> 4) & 0x0F;
+ stepPt.regval = getRegister(stepPt.reg);
+ /* Set PC witht the content of the replace register */
+ setRegister(stepPt.reg, pc + ((cpsr & PSR_T) ? 4 : 8));
+ }
+ /*set break command */
+ stepPt.sz = (n &= 0x0F);
+ readMem(stepPt.addr, &stepPt.code, n, 2);
+ writeMem(stepPt.addr, &sbpCode.b[n], n, 2);
+}
+/*
+ set breakpoint (monitor exit)
+*/
+EXPORT void setupBreak(void)
+{
+ W ibcnt, obcnt;
+ UW bcr, wcr, pc;
+ BRKPT *p;
+
+ pc = getCurPCX();
+
+ /* clear steppoint */
+ memset(&stepPt, 0, sizeof(stepPt));
+
+ if (traceMode) { /* trace is executed */
+
+ setStep(pc, traceMode); /* set up step */
+
+ } else { /* normal execution */
+
+ /* if an unexecuted break matches the PC value */
+ /* temporarily set up step execution, and execute one instruction only */
+ if (stepFlg == 0) {
+ for (p = brkPt; p <= &brkPt[MAX_BRKPT]; p++) {
+ if (p->addr == pc && (p->atr & BA_PRE)) {
+ setStep(pc, 0); /* set up temporary step execution */
+ stepFlg = 1;
+ return;
+ }
+ }
+ }
+
+ ibcnt = obcnt = 0;
+
+ /*set breakpoint */
+ /* - unless we turn on monitor debug mode, WCR/WVR/BCR/BVR */
+ /* cannot be accessed */
+ /* - depending on hardware, monitor debug mode cannot be */
+ /* set to on */
+ /* So try setting monitor debug mode on, and only if it is successful, */
+ /* we try to set WCR/WVR/BCR/BVR */
+ for (p = brkPt; p <= &brkPt[MAX_BRKPT]; p++) {
+ if (p->addr == 0) continue;
+
+ if (p->atr & BA_O) {
+ if (!EnableCP14()) continue;
+ wcr = getWCR(obcnt);
+ wcr &= ~0x001FC1FF;
+ wcr |= ((p->atr & (BA_RW)) >> 9) << 3;
+ switch (p->atr >> 24) { /* LE only */
+ case 2: wcr |= 0x060 << (p->addr & 2); break;
+ case 4: wcr |= 0x1e0; break;
+ default: /* do nothing */ break;
+ }
+ setWVR(obcnt, p->addr & ~3);
+ setWCR(obcnt, wcr | 7);
+ obcnt++;
+ } else if (p->atr & BA_I) {
+ if (!EnableCP14()) continue;
+ bcr = getBCR(ibcnt);
+ bcr &= ~0x007FC1E7;
+ bcr |= (p->addr & 2) ? 0x180 : 0x060; /* LE */
+ setBVR(ibcnt, p->addr & ~3);
+ setBCR(ibcnt, bcr | 7);
+ ibcnt++;
+ } else if (p->atr & BA_SET) {
+ readMem(p->addr, &p->code, p->sz, 2);
+ writeMem(p->addr, &sbpCode.b[p->sz], p->sz, 2);
+ }
+ }
+
+ /* if hardware breakpoint is not used at all */
+ /* monitor debug mode is turned off */
+ if (ibcnt == 0 && obcnt == 0) DisableCP14();
+ }
+ stepFlg = 0; /* clear temporary step execution flag */
+}
+/*
+ stop tracing
+*/
+EXPORT void stopTrace(void)
+{
+ traceMode = traceStep = 0;
+}
+/*
+ process program execution
+*/
+EXPORT ER goTrace(W trace, UW pc, UW par)
+{
+ W er;
+
+ /* set trace mode */
+ if ((traceMode = trace) == 0) { /* normal execution */
+ /* set temporary breakpoint */
+ if (par != 0) {
+ er = setBreak(par, BA_S | BA_PRE | BA_TMP, NULL, 0);
+ if (er < E_OK) return er;
+ }
+ } else { /* trace execution */
+ traceStep = par;
+ }
+ setCurPC(pc); /* set execution start address */
+ return E_OK;
+}
+/*
+ prcess break exception
+
+ return 0: continue, 1: command execution (cmd : initial command line)
+*/
+EXPORT W procBreak(W bpflg, UB **cmd)
+{
+ B *mes;
+ BRKPT *bp;
+ UW pc, npc, wfar;
+
+ bp = NULL;
+
+ if (traceMode) { /* trace execution */
+ /*PC holds the next PC value (by resetBreak()) */
+ pc = getCurPC();
+
+ /* disassembly display (next instruction) */
+ disAssemble(&pc, &npc, wrkBuf);
+ DSP_F4(08X,pc, S,": ", S,wrkBuf, CH,'\n');
+
+ if (-- traceStep > 0) return 0; /* continue */
+ stopTrace(); /* stop tracing */
+
+ } else { /* breakpoint */
+ /* During temporary step execution, then do nothing and continue */
+ if (stepFlg) return 0;
+
+ pc = getCurPCX(); /* break address has been adjusted */
+
+ /* this is not a breakpoint set by b command */
+ if ((bpflg & 0xF0) == 0) {
+ DSP_F3(S,"Unknown break at H'", 08X,pc, CH,'\n');
+ *cmd = NULL;
+ return 1;
+ }
+
+ bp = &brkPt[bpflg & 0xF];
+ switch (bp->atr & (BA_S | BA_I | BA_O | BA_R | BA_W)) {
+ case BA_S: mes = "S"; break;
+ case BA_I: mes = "E"; break;
+ case BA_O|BA_R: mes = "R"; break;
+ case BA_O|BA_W: mes = "W"; break;
+ case BA_O|BA_R|BA_W: mes = "RW"; break;
+ default: mes = "?"; break;
+ }
+
+ if ((bp->atr & BA_O) && CheckCP14()) {
+ /* the address of instruction that generated operand break */
+ /* is fetched from WFAR */
+ wfar = getWFAR();
+ wfar -= (getCurCPSR() & PSR_T) ? 4 : 8;
+ DSP_F4(S,"Break (", S,mes, S,") at ", 08X,wfar);
+ DSP_F3(S," (R15/PC:", 08X,pc, S,")\n");
+ } else {
+ DSP_F5(S,"Break (", S,mes, S,") at ", 08X,pc, CH,'\n');
+ }
+ }
+
+ /* restore stopped instruction */
+ *cmd = (bp && bp->cmd[0] != 0) ? bp->cmd : NULL;
+ return 1; /* wait for command */
+}
diff --git a/tkernel_source/monitor/hwdepend/arm/cpu/cpuctrl2.S b/tkernel_source/monitor/hwdepend/arm/cpu/cpuctrl2.S
new file mode 100644
index 0000000..15745de
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/cpu/cpuctrl2.S
@@ -0,0 +1,90 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * cpuctrl2.S
+ *
+ * ARM CPU control
+ *
+ * Assume that system control processor (CP15) exists.
+ */
+#define _in_asm_source_
+
+#include <machine.h>
+#include <tk/sysdef.h>
+
+#define DCACHE_NWAY 4 /* N as in the number of N-way data cache */
+#define DCACHE_NWAY_SHIFT 30
+#define DCACHE_NSEG 256 /* number of segments of data cache */
+#define DCACHE_NSEG_SHIFT 5
+
+/*
+ * flush the entire cache (write back and then invalidate)
+ * void FlushCache( void )
+ */
+ .text
+ .balign 4
+ .globl Csym(FlushCache)
+ .type Csym(FlushCache), %function
+Csym(FlushCache):
+ ldr r2, =DCACHE_NWAY-1
+ l_flush_dcache1:
+ ldr r3, =DCACHE_NSEG-1
+ l_flush_dcache2:
+ mov ip, r2, lsl #DCACHE_NWAY_SHIFT
+ orr ip, ip, r3, lsl #DCACHE_NSEG_SHIFT
+ mcr p15, 0, ip, cr7, c14, 2 // data cache is written back,
+ subs r3, r3, #1 // and is invalidated
+ bpl l_flush_dcache2
+ subs r2, r2, #1
+ bpl l_flush_dcache1
+
+ ldr ip, =0
+ mcr p15, 0, ip, cr7, c7, 0 // Invalidate I/D-Cache
+ mcr p15, 0, ip, cr7, c10, 4 // Drain Write Buffer
+
+ bx lr
+
+/*
+ * cache and MMU control
+ * void setCacheMMU( UW cp15r1 )
+ */
+ .text
+ .balign 4
+ .globl Csym(setCacheMMU)
+ .type Csym(setCacheMMU), %function
+Csym(setCacheMMU):
+ stmfd sp!, {r4, lr} // save registers
+ mov r4, r0 // save argument
+
+ /* flush cache */
+ bl Csym(FlushCache)
+
+ /* TLB flush */
+ ldr ip, =0
+ mcr p15, 0, ip, cr8, c7, 0 // Invalidate I/D-TLB
+
+ /* set new r1 for CP15 */
+ mrc p15, 0, r2, cr1, cr0, 0
+ ldr r3, =0x3307 // V,I,R,S,C,A,M (B = 0)
+ and r0, r4, r3
+ mvn r3, r3 // clear old V,I,R,S,C,A,M
+ and r2, r2, r3
+ orr r0, r0, r2
+ mcr p15, 0, r0, cr1, cr0, 0
+ nop
+ nop
+
+ ldmfd sp!, {r4, lr} // restore registers
+ bx lr
diff --git a/tkernel_source/monitor/hwdepend/arm/cpu/disassemble.c b/tkernel_source/monitor/hwdepend/arm/cpu/disassemble.c
new file mode 100644
index 0000000..5f27062
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/cpu/disassemble.c
@@ -0,0 +1,63 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by T-Engine Forum at 2013/03/04.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * disasemble.c
+ *
+ * disassember
+ */
+
+#include "../cmdsvc.h"
+
+LOCAL UB *make_hex(UB *str, UB byte)
+{
+ LOCAL const UB hex[] = "0123456789ABCDEF";
+
+ *str++ = hex[(byte >> 4) & 0x0f];
+ *str++ = hex[(byte >> 0) & 0x0f];
+
+ return str;
+}
+
+/*
+ disassembler main body
+
+ * disassembly is not fully done. But, during step tracing,
+ memory content is shown (this much is implemented).
+ the content of *naddr is meaningless
+ */
+EXPORT ER disAssemble(UW *saddr, UW *naddr, UB *str)
+{
+ W len;
+ UW inst, addr;
+
+ len = (*saddr & 0x1) ? 2 : 4; /* Thumb or Arm instruction */
+ addr = (*saddr &= ~(len - 1)); /* address adjustment */
+
+ /* extract op code */
+ if (readMem(addr, &inst, len, 2) != len) return E_MACV;
+
+ /* binary dump */
+ if (len == 4) {
+ str = make_hex(str, inst >> 24);
+ str = make_hex(str, inst >> 16);
+ }
+ str = make_hex(str, inst >> 8);
+ str = make_hex(str, inst >> 0);
+
+ *str = '\0';
+
+ return E_OK;
+}
diff --git a/tkernel_source/monitor/hwdepend/arm/cpu/eitent.S b/tkernel_source/monitor/hwdepend/arm/cpu/eitent.S
new file mode 100644
index 0000000..c37c818
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/cpu/eitent.S
@@ -0,0 +1,313 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * eitentry.S
+ *
+ * EM1D512 (ARM1176JZF-S) exception branch handling
+ */
+
+#define _in_asm_source_
+
+#include <machine.h>
+#include <tk/sysdef.h>
+#include <arm/em1d512.h>
+#include <sys/sysinfo.h>
+
+#define base(n) ( (n) & 0xfffff000 )
+#define offs(n) ( (n) & 0x00000fff )
+
+// see <sys/sysdepend/tef_em1d/sysinfo_depend.h>
+#define N_INTVEC 256
+
+/*
+ * EIT entry
+ */
+
+ .section EITBRA, "ax"
+ .arm
+ .org 0x00000000
+ b startup_entry // 00 : reset
+ b undef_entry // 04 : undefined instruction exception
+ b svc_entry // 08 : supervisor call (SVC)
+ b iabort_entry // 0C : prefetch abort
+ b dabort_entry // 10 : data abort
+ nop // 14 : (reserved)
+ b irq_entry // 18 : interrupt
+ .org 0x0000001c // 1C : fast interrupt
+
+/*
+ * fast interrupt
+ * calls the handler defined at FIQ interrupt vector unconditionally.
+ * no saving of registers to stack is performed.
+ * the content of R12_fiq(ip) register is overwritten.
+ */
+fiq_entry:
+ ldr ip, =base(EIT_VECTBL)
+ ldr ip, [ip, #offs(EITVEC(EIT_FIQ))]
+ bx ip
+
+/*
+ * interrupt
+ * ACPU interrupt mask status register of Interrupt controller (AINT)
+ * Judge the priority of interrupts using (IT0_MST0,1,2),
+ * the highest interrupt's handler is called by jumping into it.
+ * Interrupt priority is descending order of interrupt factor (INT 0-95) , and INT 95 (IRQ 95) is highest.
+ * INT 0 (IRQ 0) has the lowest priority.
+ * If there is no cause of the interrupt, the handler of INT 95 (IRQ95) is called.
+ * +---------------+
+ * sp -> |R3 |
+ * |R12=ip |
+ * |R14=lr | <- return address from interrupt
+ * |SPSR |
+ * +---------------+
+ * registers upon handler invocation
+ * ip = vector table address
+ * lr = indeterminate
+ */
+irq_entry:
+ sub lr, lr, #4 // return address adjustment
+ srsdb sp!, #PSR_IRQ // save registers
+ stmfd sp!, {r3, ip}
+
+ ldr lr, =base(AINTBase)
+ ldr ip, =EITVEC(EIT_IRQ(95))
+
+ ldr r3, [lr, #offs(IT0_MST2)]
+ cmp r3, #0
+ bne l_irq_br
+
+ sub ip, ip, #32*4
+ ldr r3, [lr, #offs(IT0_MST1)]
+ cmp r3, #0
+ bne l_irq_br
+
+ sub ip, ip, #32*4
+ ldr r3, [lr, #offs(IT0_MST0)]
+ cmp r3, #0
+ bne l_irq_br
+
+ ldr ip, =EITVEC(EIT_IRQ(95))
+
+ l_irq_br:
+ clzne r3, r3
+ ldr lr, [ip, -r3, lsl #2]!
+ cmp lr, #0
+ bxne lr
+ b default_entry
+
+/*
+ * GPIO interrupt
+ * Interrupt obtained by means of input port interrupt maskable status register (GIO_MST)
+ * is analyzed to check the interrupt priority, and if appropriate, the highest priority interrupt handler is entered.
+ * branch and call handler.
+ * interrupt priority is descending order of input port NUMBER (port 0 - port 127). port 127 has the highest priority, and
+ * port 0 has the lowest priority GPIO interrupts are grouped : each group has 16 interrupts, and
+ * their priorities are considered only within the context of each group.
+ * if there is no cause of interupt, the handler of IRQ95 is called.
+ * +---------------+
+ * sp -> |R3 |
+ * |R12=ip |
+ * |R14=lr | <- return address from interrupt
+ * |SPSR |
+ * +---------------+
+ * registers upon handler invocation
+ * ip = vector table address
+ * lr = indeterminate
+ */
+ .macro gio_e reg, vec
+ ldr lr, =base(\reg)
+ ldr r3, [lr, #offs(\reg)]
+ lsls r3, r3, #16
+ beq l_gio_spurious
+
+ ldr ip, =\vec
+ clz r3, r3
+ ldr lr, [ip, -r3, lsl #2]!
+ cmp lr, #0
+ bxne lr
+ b default_entry
+ .endm
+ .macro gio_o reg, vec
+ ldr lr, =base(\reg)
+ ldr r3, [lr, #offs(\reg)]
+ lsrs ip, r3, #16
+ beq l_gio_spurious
+
+ ldr ip, =\vec
+ clz r3, r3
+ ldr lr, [ip, -r3, lsl #2]!
+ cmp lr, #0
+ bxne lr
+ b default_entry
+ .endm
+
+ .globl Csym(_gio0Hdr)
+ .type Csym(_gio0Hdr), %function
+ .globl Csym(_gio1Hdr)
+ .type Csym(_gio1Hdr), %function
+ .globl Csym(_gio2Hdr)
+ .type Csym(_gio2Hdr), %function
+ .globl Csym(_gio3Hdr)
+ .type Csym(_gio3Hdr), %function
+ .globl Csym(_gio4Hdr)
+ .type Csym(_gio4Hdr), %function
+ .globl Csym(_gio5Hdr)
+ .type Csym(_gio5Hdr), %function
+ .globl Csym(_gio6Hdr)
+ .type Csym(_gio6Hdr), %function
+ .globl Csym(_gio7Hdr)
+ .type Csym(_gio7Hdr), %function
+Csym(_gio0Hdr): gio_e GIO_MST(GIO_L), EITVEC(EIT_GPIO( 15))
+Csym(_gio1Hdr): gio_o GIO_MST(GIO_L), EITVEC(EIT_GPIO( 31))
+Csym(_gio2Hdr): gio_e GIO_MST(GIO_H), EITVEC(EIT_GPIO( 47))
+Csym(_gio3Hdr): gio_o GIO_MST(GIO_H), EITVEC(EIT_GPIO( 63))
+Csym(_gio4Hdr): gio_e GIO_MST(GIO_HH), EITVEC(EIT_GPIO( 79))
+Csym(_gio5Hdr): gio_o GIO_MST(GIO_HH), EITVEC(EIT_GPIO( 95))
+Csym(_gio6Hdr): gio_e GIO_MST(GIO_HHH), EITVEC(EIT_GPIO(111))
+Csym(_gio7Hdr): gio_o GIO_MST(GIO_HHH), EITVEC(EIT_GPIO(127))
+
+ l_gio_spurious:
+ ldr ip, =base(EITVEC(EIT_IRQ(95)))
+ ldr lr, [ip, #offs(EITVEC(EIT_IRQ(95)))]!
+ cmp lr, #0
+ bxne lr
+ b default_entry
+
+/*
+ * undefined instruction
+ * +---------------+
+ * sp -> |R12=ip |
+ * |R14=lr | <- the return address, i.e., the next address that follows the undefined instruction
+ * |SPSR |
+ * +---------------+
+ * registers upon handler invocation
+ * ip = vector table address
+ * lr = indeterminate
+ */
+undef_entry:
+ srsdb sp!, #PSR_UND // save registers
+ stmfd sp!, {ip}
+
+ ldr ip, =base(EITVEC(EIT_UNDEF))
+ ldr lr, [ip, #offs(EITVEC(EIT_UNDEF))]!
+ cmp lr, #0
+ bxne lr
+ b default_entry
+
+/*
+ * supervisor call(SVC)
+ * the valid range of supervisor call number is 0-255 (N_INTVEC - 1).
+ * if an out of range value is given, treat it as SVC 0, and invokes the default handler.
+ * +---------------+
+ * sp -> |R12=ip |
+ * |R14=lr | <- return address: the address that follows the SVC instruction
+ * |SPSR |
+ * +---------------+
+ * registers upon handler invocation
+ * ip = vector table address
+ * lr = indeterminate
+ */
+svc_entry:
+ srsdb sp!, #PSR_SVC // save registers
+ stmfd sp!, {ip}
+
+ mrs ip, spsr
+ tst ip, #PSR_T
+ ldrneh ip, [lr, #-2] // Thumb instruction
+ ldreq ip, [lr, #-4] // ARM instruction
+ bicne lr, ip, #0xff00
+ biceq lr, ip, #0xff000000
+ cmp lr, #N_INTVEC // lr = software interrupt number
+ movge lr, #0
+
+ ldr ip, =EIT_VECTBL
+ ldr lr, [ip, lr, lsl #2]!
+ cmp lr, #0
+ bxne lr
+ b default_entry
+
+/*
+ * prefetch abort
+ * in the case of debug event, debug abort (instruction) handler is called.
+ * Otherwise, prefetch abort handler is called.
+ * +---------------+
+ * sp -> |R12=ip |
+ * |R14=lr | <- return address: the address of aborted instruction
+ * |SPSR |
+ * +---------------+
+ * registers upon handler invocation
+ * ip = vector table address
+ * lr = indeterminate
+ */
+iabort_entry:
+ sub lr, lr, #4 // return address adjustment
+ srsdb sp!, #PSR_ABT // save registers
+ stmfd sp!, {ip}
+
+ mrc p15, 0, ip, c5, c0, 1 // IFSR
+ tst ip, #0x400 // FS[4]
+ and ip, ip, #0x00f // FS[3:0]
+ cmpeq ip, #FSR_DebugEvent
+
+ ldr ip, =base(EITVEC(EIT_IABORT))
+ ldrne lr, [ip, #offs(EITVEC(EIT_IABORT))]!
+ ldreq lr, [ip, #offs(EITVEC(EIT_IDEBUG))]!
+ cmp lr, #0
+ bxne lr
+ b default_entry
+
+/*
+ * data abort
+ * in the case of debug event, debug abort (data) handler is called.
+ * Otherwise, data abort handler is called.
+ * +---------------+
+ * sp -> |R12=ip |
+ * |R14=lr | <- return address: the address of aborted instruction
+ * |SPSR |
+ * +---------------+
+ * registers upon handler invocation
+ * ip = vector table address
+ * lr = indeterminate
+ */
+dabort_entry:
+ sub lr, lr, #8 // return address adjustment
+ srsdb sp!, #PSR_ABT // save registers
+ stmfd sp!, {ip}
+
+ mrc p15, 0, ip, c5, c0, 0 // DFSR
+ tst ip, #0x400 // FS[4]
+ and ip, ip, #0x00f // FS[3:0]
+ cmpeq ip, #FSR_DebugEvent
+
+ ldr ip, =base(EITVEC(EIT_DABORT))
+ ldrne lr, [ip, #offs(EITVEC(EIT_DABORT))]!
+ ldreq lr, [ip, #offs(EITVEC(EIT_DDEBUG))]!
+ cmp lr, #0
+ bxne lr
+ b default_entry
+
+/*
+ * default handler
+ * stack contains the details of the generated exception.
+ * registers upon handler invocation
+ * ip = address of the vector table for the raised exception
+ * lr = indeterminate
+ */
+default_entry:
+ ldr lr, =base(EITVEC(EIT_DEFAULT))
+ ldr lr, [lr, #offs(EITVEC(EIT_DEFAULT))]
+ bx lr
+
+ .pool
diff --git a/tkernel_source/monitor/hwdepend/arm/cpu/monhdr.S b/tkernel_source/monitor/hwdepend/arm/cpu/monhdr.S
new file mode 100644
index 0000000..6acee3e
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/cpu/monhdr.S
@@ -0,0 +1,224 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * monhdr.S
+ *
+ * Monitor handler (after ARMv6)
+ */
+
+#define _in_asm_source_
+
+#include <machine.h>
+#include <sys/sysinfo.h>
+#include "cpudep.h"
+
+/*
+ * Monitor entry (registered as default handler)
+ * +---------------+
+ * sp -> |R3 | <- only in the case of interrupt
+ * +---------------+
+ * |R12=ip |
+ * |R14=lr | <- return address from exception / interupt
+ * |SPSR |
+ * +---------------+
+ * registers upon handler invocation
+ * r3 = varies according machine type and situation (only in the case of interrupt)
+ * ip = vector table address
+ * lr = indeterminate
+ */
+ .text
+ .balign 4
+ .globl Csym(_defaultHdr)
+ .type Csym(_defaultHdr), %function
+Csym(_defaultHdr):
+ // save register
+ // regStack[0-7] r0 .. r7
+ // [8,9] Entry cspr, ip
+ // [10] return cspr
+ // [11] return r15(pc)
+ // [12-18] USR: r8 ..r12, sp, lr
+ // [19-26] FIQ: spsr, r8 ..r12, sp, lr
+ // [27-29] IRQ: spsr, sp, lr
+ // [30-32] ABT: spsr, sp, lr
+ // [33-35] UND: spsr, sp, lr
+ // [36-38] SVC: spsr, sp, lr
+ // [39] CP15: SCTLR (CP15.c1.0.c0.0)
+ // [40-42] TTBR0,TTBR1,TTBCR (CP15.c2.0.c0.0 - 2)
+ // [43] DACR (CP15.c3.0.c0.0)
+ // [44-45] DFSR,IFSR (CP15.c5.0.c0.0 - 1)
+ // [46-47] DFAR,IFAR (CP15.c6.0.c0.0,2)
+ // [48] CTXIDR (CP15.c13.0.c0.1)
+
+ // save r0 .. r7
+ ldr lr, =Csym(regStack)
+ stmia lr!, {r0-r2} // r0 .. r2
+
+ // restore R3 inside stack in the case of interrupt
+ mrs r1, cpsr // cpsr -> r1
+ and r0, r1, #PSR_M(31)
+ cmp r0, #PSR_FIQ
+ cmpne r0, #PSR_IRQ
+ ldmeqfd sp!, {r3} // in the case of interrupt
+
+ stmia lr!, {r3-r7} // r3 .. r7
+ mov r7, lr // regStack -> r7
+
+ // save the status on entry (cpsr, ip)
+ cpsid aif // disable FIQ and IRQ
+ stmia r7!, {r1, ip} // Entry cspr & ip saved
+
+ // restore ip, lr, spsr from the values inside stack and return
+ ldr r2, =EIT_VECTBL
+ sub r0, ip, r2
+ mov r0, r0, asr #2 // interrupt/exception vector number -> r0
+ ldmfd sp!, {ip, lr} // restore ip and lr
+ ldmfd sp!, {r2} // r2 <- spsr restored
+ stmia r7!, {r2, lr} // save spsr, lr(pc)
+
+ // save registers of each mode
+ stmia r7, {r8-r12,sp,lr}^ // usr: r8 .. r12,sp,lr
+ add r7, r7, #(4*7)
+
+ cps #PSR_FIQ
+ mrs r3, spsr
+ stmia r7!, {r3, r8-r12,sp,lr} // fiq: spsr, r8 .. r12,sp,lr
+
+ cps #PSR_IRQ
+ mrs r3, spsr
+ stmia r7!, {r3, sp, lr} // irq: spsr, sp, lr
+
+ cps #PSR_ABT
+ mrs r3, spsr
+ stmia r7!, {r3, sp, lr} // abt: spsr, sp, lr
+
+ cps #PSR_UND
+ mrs r3, spsr
+ stmia r7!, {r3, sp, lr} // und: spsr, sp, lr
+
+ cps #PSR_SVC
+ mrs r3, spsr
+ stmia r7!, {r3, sp, lr} // svc: spsr, sp, lr
+
+ mrc p15, 0, r2, cr1, cr0, 0
+ mrc p15, 0, r3, cr2, cr0, 0
+ mrc p15, 0, r4, cr2, cr0, 1
+ mrc p15, 0, r5, cr2, cr0, 2
+ mrc p15, 0, r6, cr3, cr0, 0
+ stmia r7!, {r2,r3,r4,r5,r6} // cp15: r1,r2,r3
+
+ mrc p15, 0, r2, cr5, cr0, 0
+ mrc p15, 0, r3, cr5, cr0, 1
+ mrc p15, 0, r4, cr6, cr0, 0
+ mrc p15, 0, r5, cr6, cr0, 2
+ mrc p15, 0, r6, cr13, cr0, 1 // cp15: r5,r6,r13
+ stmia r7!, {r2,r3,r4,r5,r6}
+
+ ldr r2, =0xFFFFFFFF
+ mcr p15, 0, r2, cr3, cr0, 0 // cp15:r3(domain) manager
+
+ // set up stack exclusively used for monitor (SVC mode)
+ ldr r2, =__stack_top
+ ldr r3, =__stack_bottom // stack exclusively used for monitor
+ cmp sp, r2
+ cmpcs r3, sp // using monitor stack?
+ movcc sp, r3 // switch to monitor stack
+
+ // monitor entry: r0 = interrupt/exception vector number (r1 = cpsr) : SVC mode
+ bl Csym(entMonitor) // call entMonitor(vec)
+
+ // restore registers
+ ldr r7, =Csym(regStack) + ((39 + 10) * 4)
+
+ ldmdb r7!, {r2,r3,r4,r5,r6} // cp15: r5,r6,r13
+ mcr p15, 0, r2, cr5, cr0, 0
+ mcr p15, 0, r3, cr5, cr0, 1
+ mcr p15, 0, r4, cr6, cr0, 0
+ mcr p15, 0, r5, cr6, cr0, 2
+ mcr p15, 0, r6, cr13, cr0, 1
+
+ ldmdb r7!, {r2,r3,r4,r5,r6} // cp15: r1,r2,r3
+// mcr p15, 0, r2, cr1, cr0, 0 // already restored inside entMonitor
+//RO mcr p15, 0, r3, cr2, cr0, 0 // no need to restore (Read Only)
+//RO mcr p15, 0, r4, cr2, cr0, 1
+//RO mcr p15, 0, r5, cr2, cr0, 2
+ mcr p15, 0, r6, cr3, cr0, 0
+
+ ldmdb r7!, {r3, sp, lr} // svc: spsr, sp, lr
+ msr spsr_fsxc, r3
+ mov r1, lr // r1: lr_svc (used for forcible terminal of processes)
+
+ cps #PSR_UND
+ ldmdb r7!, {r3, sp, lr} // und: spsr, sp, lr
+ msr spsr_fsxc, r3
+
+ cps #PSR_ABT
+ ldmdb r7!, {r3, sp, lr} // abt: spsr, sp, lr
+ msr spsr_fsxc, r3
+
+ cps #PSR_IRQ
+ ldmdb r7!, {r3, sp, lr} // irq: spsr, sp, lr
+ msr spsr_fsxc, r3
+
+ cps #PSR_FIQ
+ ldmdb r7!, {r3, r8-r12,sp,lr} // fiq: spsr, r8 .. r12,sp,lr
+ msr spsr_fsxc, r3
+
+ sub r7, r7, #(4*7)
+ ldmia r7, {r8-r12,sp,lr}^ // usr: r8 .. r12,sp,lr
+
+ // restore status on etry
+ ldmdb r7!, {r0, r2, r3, r4} // r0:Entry cpsr, r2:Entry ip
+ // r3:cpsr(spsr), r4:pc(lr)
+ msr cpsr_fsxc, r0 // entry cpsr
+ stmfd sp!, {r3} // spsr -> stack
+ stmfd sp!, {r4} // pc(lr) -> stack
+
+ // do we have request for forcible termination of processe(es)?
+ ldr r4, =Csym(killProcReq)
+ ldr r0, [r4]
+ tst r0, #0xff
+ beq no_kill // no request
+ mov r0, #0
+ str r0, [r4] // clear forcible termination request
+
+ // restore to the state on entry completely, and then push lr_svc
+ stmfd sp!, {r1, ip} // sp -> lr_svc, ip
+ mov ip, r2 // restore ip
+ ldmdb r7, {r0-r7} // r0 .. r7
+
+ swi #SWI_KILLPROC // forcible termination of processes request
+ nop // do not return
+ nop
+
+ no_kill:
+ ldmdb r7, {r0-r7} // r0 .. r7
+
+ // return from monitor
+ rfefd sp!
+
+/* ------------------------------------------------------------------------ */
+
+/*
+ * calling an external program
+ * W callExtProg( FP entry )
+ */
+ .text
+ .balign 4
+ .globl Csym(callExtProg)
+ .type Csym(callExtProg), %function
+Csym(callExtProg):
+ stmfd sp!, {r4-r10, fp, lr} // save registers
+ blx r0 // call entry(void)
+ ldmfd sp!, {r4-r10, fp, pc} // restore registers
diff --git a/tkernel_source/monitor/hwdepend/arm/cpu/register.c b/tkernel_source/monitor/hwdepend/arm/cpu/register.c
new file mode 100644
index 0000000..2e24f18
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/cpu/register.c
@@ -0,0 +1,430 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by T-Engine Forum at 2013/03/04.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * register.c
+ *
+ * Register-related operations (after ARMV6)
+ */
+
+#include "../cmdsvc.h"
+#include <sys/sysinfo.h>
+
+EXPORT UW regStack[39 + 10 + 2];
+
+/*
+ register definition table
+
+ * registers are saved to regStack on entry to the monitor.
+ The value in register ID follows the order saved in register stack (below).
+ (See eitent.S)
+
+ regStack[0-7] r0 .. r7
+ [8,9] Entry cspr, ip
+ [10] return cspr
+ [11] return r15(pc)
+ [12-18] USR: r8 ..r12, sp, lr
+ [19-26] FIQ: spsr, r8 ..r12, sp, lr
+ [27-29] IRQ: spsr, sp, lr
+ [30-32] ABT: spsr, sp, lr
+ [33-35] UND: spsr, sp, lr
+ [36-38] SVC: spsr, sp, lr
+
+ [39] CP15: SCTLR (CP15.c1.0.c0.0)
+ [40-42] TTBR0,TTBR1,TTBCR (CP15.c2.0.c0.0 - 2)
+ [43] DACR (CP15.c3.0.c0.0)
+ [44-45] DFSR,IFSR (CP15.c5.0.c0.0 - 1)
+ [46-47] DFAR,IFAR (CP15.c6.0.c0.0,2)
+ [48] CTXIDR (CP15.c13.0.c0.1)
+*/
+
+#define L_REGNM 8
+typedef struct {
+ UB name[L_REGNM]; /* register name */
+ UW id; /* register ID */
+} REGTAB;
+
+#define R_GEN 0x001000 /* general register */
+#define R_CTL 0x002000 /* control register */
+#define R_GRP 0x010000 /* register group */
+
+#define R_LF 0x080000 /* forced linefeed */
+#define R_GAP 0x040000 /* empty line */
+
+#define R_ONLY 0x100 /* disable setup */
+#define SPEC(n) (0x200 | (n)) /* special */
+
+#define ixCPSR 10 /* CPSR index */
+#define ixPC 11 /* PC index */
+
+#define ixUSR 12
+#define ixFIQ (19 + 1) /* FIQ: SPSR,R8-R14 */
+#define ixIRQ (27 - 4) /* IRQ: SPSR,R13,R14 */
+#define ixABT (30 - 4) /* ABT: SPSR,R13,R14 */
+#define ixUND (33 - 4) /* UND: SPSR,R13,R14 */
+#define ixSVC (36 - 4) /* SVC: SPSR,R13,R14 */
+#define ixSP_SVC (ixSVC + 5) /* SVC SP index */
+
+#define ixCP15 39 /* CP15 index */
+#define ixCP15R1 (ixCP15 + 0)
+
+#define N_ACTREGS (16 + 7 + 7 + 8 + 7 + 10)
+#define N_REGS (N_ACTREGS + 3)
+
+LOCAL const REGTAB regTab[N_REGS] = {
+ {"R0 ", R_GEN + 0x00 }, /* 0 */
+ {"R1 ", R_GEN + 0x01 }, /* 1 */
+ {"R2 ", R_GEN + 0x02 }, /* 2 */
+ {"R3 ", R_GEN + 0x03 + R_LF }, /* 3 */
+ {"R4 ", R_GEN + 0x04 }, /* 4 */
+ {"R5 ", R_GEN + 0x05 }, /* 5 */
+ {"R6 ", R_GEN + 0x06 }, /* 6 */
+ {"R7 ", R_GEN + 0x07 + R_LF }, /* 7 */
+ {"R8 ", R_GEN + SPEC(0x00) }, /* 8 */
+ {"R9 ", R_GEN + SPEC(0x01) }, /* 9 */
+ {"R10/SL ", R_GEN + SPEC(0x02) }, /* 10 */
+ {"R11/FP ", R_GEN + SPEC(0x03) + R_LF }, /* 11 */
+ {"R12/IP ", R_GEN + SPEC(0x04) }, /* 12 */
+ {"R13/SP ", R_GEN + SPEC(0x05) }, /* 13 */
+ {"R14/LR ", R_GEN + SPEC(0x06) }, /* 14 */
+ {"R15/PC ", R_GEN + ixPC + R_LF }, /* 15 */
+
+ {"R8_USR ", R_GEN + ixUSR + 0 + R_GAP }, /* 16 */
+ {"R9_USR ", R_GEN + ixUSR + 1 }, /* 17 */
+ {"R10_USR ", R_GEN + ixUSR + 2 }, /* 18 */
+ {"R11_USR ", R_GEN + ixUSR + 3 + R_LF }, /* 19 */
+ {"R12_USR ", R_GEN + ixUSR + 4 }, /* 20 */
+ {"R13_USR ", R_GEN + ixUSR + 5 }, /* 21 */
+ {"R14_USR ", R_GEN + ixUSR + 6 + R_LF }, /* 22 */
+
+ {"R8_FIQ ", R_GEN + ixFIQ + 0 }, /* 23 */
+ {"R9_FIQ ", R_GEN + ixFIQ + 1 }, /* 24 */
+ {"R10_FIQ ", R_GEN + ixFIQ + 2 }, /* 25 */
+ {"R11_FIQ ", R_GEN + ixFIQ + 3 + R_LF }, /* 26 */
+ {"R12_FIQ ", R_GEN + ixFIQ + 4 }, /* 27 */
+ {"R13_FIQ ", R_GEN + ixFIQ + 5 }, /* 28 */
+ {"R14_FIQ ", R_GEN + ixFIQ + 6 + R_LF }, /* 29 */
+
+ {"R13_IRQ ", R_GEN + ixIRQ + 5 }, /* 30 */
+ {"R14_IRQ ", R_GEN + ixIRQ + 6 }, /* 31 */
+ {"R13_SVC ", R_GEN + ixSVC + 5 }, /* 32 */
+ {"R14_SVC ", R_GEN + ixSVC + 6 + R_LF }, /* 33 */
+ {"R13_ABT ", R_GEN + ixABT + 5 }, /* 34 */
+ {"R14_ABT ", R_GEN + ixABT + 6 }, /* 35 */
+ {"R13_UND ", R_GEN + ixUND + 5 }, /* 36 */
+ {"R14_UND ", R_GEN + ixUND + 6 + R_LF }, /* 37 */
+
+ {"CPSR ", R_CTL + ixCPSR + R_GAP }, /* 38 */
+ {"SPSR ", R_CTL + SPEC(0x08) }, /* 39 */
+ {"SPSR_FIQ", R_CTL + ixFIQ - 1 }, /* 40 */
+ {"SPSR_IRQ", R_CTL + ixIRQ + 4 + R_LF }, /* 41 */
+ {"SPSR_SVC", R_CTL + ixSVC + 4 }, /* 42 */
+ {"SPSR_ABT", R_CTL + ixABT + 4 }, /* 43 */
+ {"SPSR_UND", R_CTL + ixUND + 4 + R_LF }, /* 44 */
+
+ {"SCTLR ", R_CTL + SPEC(0x0F) + 0 + R_GAP }, /* 45 */
+ {"TTBR0 ", R_CTL + ixCP15 + 1 + R_ONLY }, /* 46 */
+ {"TTBR1 ", R_CTL + ixCP15 + 2 + R_ONLY }, /* 47 */
+ {"TTBCR ", R_CTL + ixCP15 + 3 + R_ONLY + R_LF}, /* 48 */
+ {"DACR ", R_CTL + ixCP15 + 4 }, /* 49 */
+ {"DFSR ", R_CTL + ixCP15 + 5 }, /* 50 */
+ {"IFSR ", R_CTL + ixCP15 + 6 }, /* 51 */
+ {"DFAR ", R_CTL + ixCP15 + 7 + R_LF }, /* 52 */
+ {"IFAR ", R_CTL + ixCP15 + 8 }, /* 53 */
+ {"CTXIDR ", R_CTL + ixCP15 + 9 + R_LF }, /* 54 */
+
+ {"G ", R_GRP|R_GEN },
+ {"C ", R_GRP|R_CTL },
+ {"A ", R_GRP|R_GEN|R_CTL },
+};
+/*
+ Searching register name
+*/
+EXPORT W searchRegister(UB *name, W grp)
+{
+ W i, n, a;
+ UB bf[L_REGNM];
+ REGTAB *p;
+
+ if (name[L_REGNM] != ' ') return -1;
+
+ for (p = (REGTAB*)regTab, i = 0; i < N_REGS; p++, i++) {
+ for (n = 0; n < L_REGNM; n++) if (p->name[n] == '/') break;
+ if (n == L_REGNM) { /* no separator '/' -> a single register name */
+ if (memcmp(name, p->name, L_REGNM)) continue;
+ } else { /* has alias */
+ /* check the name(s) after the separator */
+ memset(bf, ' ', sizeof(bf));
+ memcpy(bf, p->name + (n + 1), L_REGNM - (n + 1));
+ a = memcmp(name, bf, L_REGNM - n);
+
+ /* check the name before the separator */
+ memset(bf, ' ', sizeof(bf));
+ memcpy(bf, p->name, n);
+ if (a && memcmp(name, bf, n + 1)) continue;
+ }
+ if (grp == 0 && (p->id & R_GRP)) break;
+ return i;
+ }
+ return -1;
+}
+/*
+ obtain CPU mode index
+*/
+LOCAL W ixCpuMode(void)
+{
+ /* obtain mode */
+ switch(regStack[ixCPSR] & PSR_M(31)) {
+ case PSR_USR:
+ case PSR_SYS: return ixUSR;
+ case PSR_FIQ: return ixFIQ;
+ case PSR_IRQ: return ixIRQ;
+ case PSR_SVC: return ixSVC;
+ case PSR_ABT: return ixABT;
+ case PSR_UND: return ixUND;
+ }
+ return 0;
+}
+/*
+ obtain register value
+*/
+EXPORT UW getRegister(W regno)
+{
+ W i, ix;
+
+ i = regTab[regno].id & (R_GRP | 0x3ff);
+
+ /* normal register */
+ if (i < SPEC(0)) return regStack[i & 0xff];
+
+ /* obtain mode */
+ ix = ixCpuMode();
+
+ /* special register */
+ switch(i) {
+ case SPEC(0x00): /* R8 */
+ case SPEC(0x01): /* R9 */
+ case SPEC(0x02): /* R10 */
+ case SPEC(0x03): /* R11 */
+ case SPEC(0x04): /* R12 */
+ if (ix != ixFIQ) ix = ixUSR;
+ case SPEC(0x05): /* R13 */
+ case SPEC(0x06): /* R14 */
+ return regStack[ix + i - SPEC(0)];
+ case SPEC(0x08): /* SPSR */
+ if (ix == ixUSR) return 0; /* undefined */
+ if (ix == ixFIQ) ix -= 5;
+ return regStack[ix + 4];
+ case SPEC(0x0F): /* CP15 R1 */
+ return regStack[ixCP15R1];
+ }
+ /* retur 0 on error */
+ return 0;
+}
+/*
+ Set register value
+*/
+EXPORT ER setRegister(W regno, UW val)
+{
+ W i, ix;
+
+ i = regTab[regno].id & (R_GRP | 0x3ff);
+ if (i & R_ONLY) return E_RONLY; /* cannot be set */
+
+ if (i < SPEC(0)) { /* normal register */
+ regStack[i & 0xff] = val;
+ return 0;
+ }
+
+ /* obtain mode */
+ ix = ixCpuMode();
+
+ /* special register */
+ switch(i) {
+ case SPEC(0x00): /* R8 */
+ case SPEC(0x01): /* R9 */
+ case SPEC(0x02): /* R10 */
+ case SPEC(0x03): /* R11 */
+ case SPEC(0x04): /* R12 */
+ if (ix != ixFIQ) ix = ixUSR;
+ case SPEC(0x05): /* R13 */
+ case SPEC(0x06): /* R14 */
+ regStack[ix + i - SPEC(0x00)] = val;
+ break;
+ case SPEC(0x08): /* SPSR */
+ if (ix == ixUSR) break; /* undefined */
+ if (ix == ixFIQ) ix -= 5;
+ regStack[ix + 4] = val;
+ break;
+ case SPEC(0x0F): /* CP15 R1 */
+ regStack[ixCP15R1] &= MASK_CACHEMMU;
+ regStack[ixCP15R1] |= val & VALID_CACHEMMU;
+ break;
+ default:
+ return E_PAR;
+ }
+ return 0;
+}
+/*
+ List the values of register (group)
+ regno < 0 : default group (not specified)
+*/
+EXPORT void dispRegister(W regno)
+{
+ W i, j, n, id, rid;
+
+ if (regno >= N_REGS) return;
+
+ id = (regno < 0) ? (R_GRP | R_GEN) : regTab[regno].id;
+
+ for (n = i = 0; i < N_ACTREGS; i++) {
+ rid = regTab[i].id;
+ if (!(i == regno || ((id & R_GRP) && (rid & id)))) continue;
+ if (n != 0 && (rid & R_GAP)) DSP_LF;
+ if (n++ & 0x0f) DSP_S(" ");
+ for (j = 0; j < L_REGNM; j++) DSP_CH(regTab[i].name[j]);
+ DSP_F2(S,": ", 08X,getRegister(i));
+ if (rid & R_LF) {DSP_LF; n = 0x10;}
+ if ((id & R_GRP) == 0) break;
+ }
+ if (n & 0x0f) DSP_LF;
+}
+/*
+ obtain CPSR register value
+*/
+EXPORT UW getCurCPSR(void)
+{
+ return regStack[ixCPSR];
+}
+/*
+ obtain SPSR register value
+*/
+EXPORT UW getCurSPSR(void)
+{
+ return getRegister(39);
+}
+/*
+ obtain PC register value
+*/
+EXPORT UW getCurPC(void)
+{
+ /* set LSB = 1 for Thumb mode. */
+ return regStack[ixPC] | ((regStack[ixCPSR] & PSR_T) ? 1 : 0);
+}
+EXPORT UW getCurPCX(void)
+{
+ return regStack[ixPC];
+}
+EXPORT UW getCP15(W reg, W opcd)
+{
+ W i, d;
+ LOCAL const UH reg_op[] = {
+ 0x1000, 0x2000, 0x2001, 0x2002, 0x3000, 0x5000, 0x5001, 0x6000,
+ 0x6002, 0xd001,
+ };
+
+ d = ((reg & 0x0f) << 12) | (opcd & 0x0fff);
+
+ for (i = 0; i < sizeof(reg_op) / sizeof(UH); i++) {
+ if (reg_op[i] == d) return regStack[ixCP15 + i];
+ }
+ return 0;
+}
+/*
+ Set PC register value
+*/
+EXPORT void setCurPC(UW val)
+{
+ if (regStack[ixPC] != val) {
+ /* Thumb Bit is changed according to the LSB value of PC. */
+ if (val & 0x3) regStack[ixCPSR] |= PSR_T;
+ else regStack[ixCPSR] &= ~PSR_T;
+ regStack[ixPC] = val & ~0x1;
+ }
+}
+EXPORT void setCurPCX(UW val)
+{
+ /* Thumb Bit is not changed. */
+ regStack[ixPC] = val & ~0x1;
+}
+/*
+ Set registers for BOOT
+*/
+EXPORT void setUpBoot( void *start, BootInfo *bootinfo )
+{
+ bootFlag = 1; /* suppress the setting register R0 upon exit of the monitor */
+
+ regStack[ixCPSR] = PSR_I | PSR_F | PSR_SVC;
+ regStack[0] = (UW)bootinfo; /* R0 boot parameter */
+ regStack[ixPC] = (UW)start; /* PC start address */
+ regStack[ixSP_SVC] = (UW)&__stack_bottom; /* SP monitor stack */
+
+ /* MMU enabled, Cache / Write Buffer not enabled */
+ regStack[ixCP15R1] &= MASK_CACHEMMU;
+ regStack[ixCP15R1] |= ENB_MMUONLY;
+
+ /* system initialization processing */
+ resetSystem(1);
+}
+/*
+ Check whether we can use KILL command
+*/
+EXPORT W isKillValid(void)
+{
+ /* Has TRAP for KILL been define? */
+ if ( SCArea->intvec[SWI_KILLPROC] == NULL ) return -1;
+ return 0;
+}
+
+#ifdef REF_TKOBJECT
+/*
+ Check whether T-Kernel/DS functions can be executed?
+*/
+EXPORT W isTKDSValid(void)
+{
+ /* Has TRAP for T-Kernel/DS been defined? */
+ if ( SCArea->intvec[SWI_DEBUG] == NULL ) return -1;
+ return 0;
+}
+
+/*
+ Display register of tasks
+*/
+EXPORT W PrintTaskRegister( int (*prfn)( const char *format, ... ),
+ T_REGS *gr, T_EIT *er, T_CREGS *cr )
+{
+/*
+ * PC: 12345678 CPSR:12345678 TMF:12345678
+ * R0: 12345678 R1: 12345678 R2: 12345678 R3: 12345678
+ * R4: 12345678 R5: 12345678 R6: 12345678 R7: 12345678
+ * R8: 12345678 R9: 12345678 R10:12345678 R11:12345678
+ * IP: 12345678 LR: 12345678
+ * USP:12345678 SSP:12345678 LSID:1234 UATB:12345678
+ */
+ (*prfn)("PC: %08x CPSR:%08x TMF:%08x\n",
+ (UW)er->pc, er->cpsr, er->taskmode);
+ (*prfn)("R0: %08x R1: %08x R2: %08x R3: %08x\n",
+ gr->r[0], gr->r[1], gr->r[2], gr->r[3]);
+ (*prfn)("R4: %08x R5: %08x R6: %08x R7: %08x\n",
+ gr->r[4], gr->r[5], gr->r[6], gr->r[7]);
+ (*prfn)("R8: %08x R9: %08x R10:%08x R11:%08x\n",
+ gr->r[8], gr->r[9], gr->r[10], gr->r[11]);
+ (*prfn)("IP: %08x LR: %08x\n",
+ gr->r[12], (UW)gr->lr);
+ (*prfn)("USP:%08x SSP:%08x LSID:%-4d UATB:%08x\n",
+ (UW)cr->usp, (UW)cr->ssp, cr->lsid, (UW)cr->uatb);
+ return 6; /* number of display lines */
+}
+#endif /* REF_TKOBJECT */
diff --git a/tkernel_source/monitor/hwdepend/arm/cpu/reset.S b/tkernel_source/monitor/hwdepend/arm/cpu/reset.S
new file mode 100644
index 0000000..50e90ee
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/cpu/reset.S
@@ -0,0 +1,639 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * reset.S
+ *
+ * EM1-D512: initial setting after a reset.
+ */
+
+#define _in_asm_source_
+
+#include <machine.h>
+#include <tk/sysdef.h>
+#include <arm/em1d512.h>
+#include <sys/sysinfo.h>
+
+#include "setup_em1d512.h"
+
+/*
+ * macro for setting up registers
+ */
+.macro out_w reg, val
+ .ifnes "\val", "" // when val is empty, do nothing.
+ ldr r0, =\reg
+ ldr r1, =\val
+ str r1, [r0]
+ .endif
+.endm
+
+.macro setup_param // r0: address of parameter string.
+0: // * r0, r2, and r3 are going to be clobbered.
+ ldmia r0!, {r2, r3}
+ cmp r2, #0
+ strne r3, [r2]
+ bne 0b
+.endm
+
+.macro wait_nsec // r0: wait time (nsec)
+ // * Assume one step is 4 ns @ (500MHz)
+ lsr r0, r0, #2
+0:
+ subs r0, r0, #1
+ bne 0b
+.endm
+
+/*
+ * memory barrier macros
+ */
+.macro _mov reg, val
+ .ifnes "\reg", "\val"
+ mov \reg, \val
+ .endif
+.endm
+.macro .ISB reg, val=#0
+ _mov \reg, \val
+ mcr p15, 0, \reg, cr7, c5, 4
+.endm
+.macro .DSB reg, val=#0
+ _mov \reg, \val
+ mcr p15, 0, \reg, cr7, c10, 4
+.endm
+.macro .DMB reg, val=#0
+ _mov \reg, \val
+ mcr p15, 0, \reg, cr7, c10, 5
+.endm
+
+/*----------------------------------------------------------------------
+ T-Monitor boot processing
+----------------------------------------------------------------------*/
+ .section .startup, "ax"
+ .balign 4
+ .globl startup_entry
+ .type startup_entry, %function
+ .org 0x00000000
+startup_entry:
+// SVC mode, FIQ/IRQ interrupt disabled
+ mov r0, #(PSR_SVC | PSR_I | PSR_F)
+ msr cpsr_fsxc, r0
+
+// use On-Chip SRAM as stack area
+ ldr sp, =0xa0020000
+
+// not in effect: MMU, cache (D/I), program-flow prediction, High-Vector, VIC
+// in effect: Force AP, TEX remap, Subpage AP
+ .DSB r0
+ mrc p15, 0, r0, cr1, cr0, 0
+ ldr r1, =~0x01003f85
+ and r0, r0, r1
+ ldr r1, =0x30800000
+ orr r0, r0, r1
+ mcr p15, 0, r0, cr1, cr0, 0
+
+// Setup clock divider
+ mov r0, #0
+ ldr r2, =CHG_L1_HOLD
+ str r0, [r2] // release data hold when L1 is off
+ mov r0, #0x30000000
+ ldr r2, =AUTO_FRQ_CHANGE
+ str r0, [r2] // automatic frequency change function is off
+
+setup_clock_divider:
+ adr r0, param_table0
+ setup_param
+
+// Setup PLL1 (PLL3 is operating)
+setup_pll1:
+ // We assume Power ON mode: In other mode setting, we simply take it for granted that PLL has been configured already
+ ldr r2, =CLK_MODE_SEL
+ ldr r0, [r2]
+ ands r0, r0, #0x00000f00
+ bne setup_power_mode
+
+ mov r0, #0x79 // (default) PLL1=499.712MHz
+ ldr r2, =PLL1CTRL0
+ str r0, [r2]
+ mov r0, #0
+ ldr r2, =PLL1CTRL1
+ str r0, [r2] // PLL starts to operate
+ ldr r2, =PLL_STATUS
+wait_pll1:
+ ldr r0, [r2] // Wait for PLL1 operation completion
+ ands r0, r0, #0x00000001
+ beq wait_pll1
+
+// Setup power mode
+setup_power_mode:
+ // Transition from Power ON to Normal Mode A
+ mov r0, #1
+ ldr r2, =CLK_MODE_SEL
+ str r0, [r2]
+wait_power_mode_change:
+ ldr r0, [r2]
+ and r0, r0, #0x00000f00
+ cmp r0, #0x00000100
+ bne wait_power_mode_change
+
+// Setup PLL2 (needs to be configured in Normal Mode)
+setup_pll2:
+ mov r0, #0xff // PLL2 ceases to operate
+ ldr r2, =PLL2CTRL1
+ str r0, [r2]
+ ldr r2, =PLL_STATUS
+wait_pll2_0:
+ ldr r0, [r2] // Wait for PLL1 operation
+ ands r0, r0, #0x00000100
+ bne wait_pll2_0
+
+ mov r0, #0x61 // PLL2=401.408MHz
+ ldr r2, =PLL2CTRL0
+ str r0, [r2]
+ mov r0, #0 // PLL2 starts to operate
+ ldr r2, =PLL2CTRL1
+ str r0, [r2]
+ ldr r2, =PLL_STATUS
+wait_pll2_1:
+ ldr r0, [r2] // wait for PLL2 to stop operation.
+ ands r0, r0, #0x00000100
+ beq wait_pll2_1
+
+// Setup pin multiplexer
+setup_pin_mux:
+ mov r1, #0xff000000 // since 'adr' cannot be used, we manually make sure
+ ldr r0, =Csym(GPIOConfig) // that the code is relocatable at 16MB units boundary.
+ bic r0, r0, r1
+ and r1, pc, r1
+ orr r0, r0, r1
+ setup_param
+
+// release reset of the internal modules
+setup_module:
+ adr r0, param_table1
+ setup_param
+ ldr r0, =100000
+ wait_nsec
+
+// supplying clock to modules.
+setup_clock_distribution:
+ adr r0, param_table2
+ setup_param
+
+// Setup Bus controller
+setup_bcr:
+ adr r0, param_table3
+ setup_param
+
+// initialization of DDR memory
+ bl setup_ddr
+
+// creation of temporary page table
+ ldr r0, =PAGETBL_BASE
+ ldr r1, =0x00000000
+ ldr r2, =0x00000402 // Kernel/RW, Strongly-order
+tmptable_loop:
+ orr r3, r1, r2
+ str r3, [r0], #4
+ adds r1, r1, #0x00100000
+ bne tmptable_loop
+
+// Mapping of FlashROM area (0x70000000 - 0x72000000 --> 0x00000000 -)
+ ldr r0, =(PAGETBL_BASE + (0x700 << 2))
+ ldr r1, =0x00000000
+ ldr r2, =0x0000940e // Kernel/RO, Normal WB/WA
+flashtable_loop:
+ orr r3, r1, r2
+ str r3, [r0], #4
+ adds r1, r1, #0x00100000
+ cmp r1, #0x02000000
+ bne flashtable_loop
+
+// initialization of CP15
+ ldr r0, =0x00000004
+ mcr p15, 0, r0, cr2, cr0, 2 // TTBCR
+ ldr r0, =(PAGETBL_BASE + 0x09) // WB/WA, no-shared, cachable
+ mcr p15, 0, r0, cr2, cr0, 1 // TTBR1
+ mcr p15, 0, r0, cr2, cr0, 0 // TTBR0
+ ldr r0, =EITENT_BASE
+ mcr p15, 0, r0, cr12, cr0, 0 // VBAR
+ ldr r0, =0x000a8aa4
+ mcr p15, 0, r0, cr10, cr2, 0 // PRRR
+ ldr r0, =0x44e048e0
+ mcr p15, 0, r0, cr10, cr2, 1 // NMRR
+ ldr r0, =0x55555555 // All client
+ mcr p15, 0, r0, cr3, cr0, 0 // Domain access
+
+// MMU enable
+ .DSB r0
+ mcr p15, 0, r0, cr8, cr7, 0 // I/D TLB invalidate
+ mcr p15, 0, r0, cr7, cr5, 6 // invalidate BTC
+ .DSB r0
+ .ISB r0
+ mrc p15, 0, r0, cr1, cr0, 0
+ orr r0, r0, #0x00000001
+ mcr p15, 0, r0, cr1, cr0, 0
+ .ISB r0
+
+// perform reset processing
+ ldr pc, =reset_entry
+
+// initialization of DDR memory
+setup_ddr:
+ ldr r0, =MEMCCLK270_SEL
+ ldr r1, =0x00000001 // MEMCCLK270 no phase delay
+ str r1, [r0]
+
+ ldr r0, =MEMC_DDR_CONFIGT1
+ ldr r1, =0x00000006 // start auto-calibration
+ str r1, [r0]
+calibrate_loop:
+ ldr r1, [r0]
+ ands r1, r1, #0x00000002 // wait for complete
+ beq calibrate_loop
+
+ ldr r0, =MEMC_DDR_CONFIGT3
+ ldr r1, [r0] // get calibration result
+ ldr r0, =MEMC_DDR_CONFIGT2
+ str r1, [r0] // apply calibrated value
+
+ ldr r0, =MEMCCLK270_SEL
+ ldr r1, =0x00000000 // MEMCCLK270 270degree delay
+ str r1, [r0]
+
+ ldr r0, =MEMC_DDR_CONFIGT1
+ ldr r1, =0x000d0803
+ str r1, [r0]
+
+ ldr r0, =MEMC_DDR_CONFIGF
+ ldr r1, =0x00000015
+ str r1, [r0]
+
+ ldr r0, =MEMC_DDR_CONFIGA1
+ ldr r1, =0x53443203
+ str r1, [r0]
+
+ ldr r0, =MEMC_DDR_CONFIGA2
+ ldr r1, =0x28da1042
+ str r1, [r0]
+
+ ldr r0, =MEMC_DDR_CONFIGC2
+ ldr r1, =0x0000001d
+ str r1, [r0]
+
+ ldr r0, =200000
+ wait_nsec
+
+ ldr r0, =MEMC_DDR_CONFIGC1
+ ldr r1, =0x80200033
+ str r1, [r0]
+
+ ldr r0, =MEMC_DDR_CONFIGC2
+ ldr r1, =0x00000018 // CS0: memory initialize sequence
+ str r1, [r0]
+ddr_init_loop:
+ ldr r1, [r0]
+ ands r1, r1, #0x00000100
+ beq ddr_init_loop
+
+ ldr r0, =MEMC_REQSCH
+ ldr r1, =0x0000001f // memory request schedule
+ str r1, [r0]
+
+ ldr r0, =MEMC_DDR_CONFIGC2
+ ldr r1, =0x00000090 // CS0: CMD_REQ release
+ str r1, [r0]
+
+ ldr r0, =MEMC_DDR_CONFIGR1
+ ldr r1, =0x00690069 // refresh counter
+ str r1, [r0]
+
+ ldr r0, =MEMC_DDR_CONFIGR2
+ ldr r1, =0x3777011f
+ str r1, [r0]
+
+ ldr r0, =MEMC_DDR_CONFIGR3
+ ldr r1, =0x00001415
+ str r1, [r0]
+
+ bx lr
+
+ .pool
+
+param_table0:
+ .long NORMALA_DIV // ACPU =PLL1/1 (499.712MHz)
+ .long 0x00244200 // ADSP =PLL1/1 (499.712MHz)
+ // HBUS =PLL1/3 (166.571MHz)
+ // LBUS =PLL1/6 ( 83.285MHz)
+ // FLASH=PLL1/6 ( 83.285MHz)
+ // MEMC =PLL1/3 (166.571MHz)
+ .long DIVU70SCLK
+ .long 0x00000000 // U70_SCLK=PLL3/1 (229.376MHz)
+ .long DIVU71SCLK
+ .long 0x00000000 // U71_SCLK=PLL3/1 (229.376MHz)
+ .long DIVU72SCLK
+ .long 0x00000000 // U72_SCLK=PLL3/1 (229.376MHz)
+ .long DIVLCDLCLK
+ .long 0x00000004 // LCD_LCLK=PLL2/16 (25.088MHz)
+ .long DIVIICSCLK
+ .long 0x00530053 // IIC_SCLK=PLL3/48 (4.779MHz)
+ .long DIVTIMTIN
+ .long 0x00000003 // Txx_TIN=PLL3/8 (28.672MHz)
+ .long DIVSP0SCLK
+ .long 0x00000074 // SP0_SCLK=PLL3/128 (1.792MHz)
+ .long TI0TIN_SEL
+ .long 0x00000000
+ .long TI1TIN_SEL
+ .long 0x00000000
+ .long TI2TIN_SEL
+ .long 0x00000000
+ .long TI3TIN_SEL
+ .long 0x00000000
+ .long TIGnTIN_SEL
+ .long 0x00000000
+
+ .long 0x00000000 // (terminate)
+ .long 0x00000000
+
+param_table1:
+ .long RESETREQ0ENA
+ .long 0xffffffff
+ .long RESETREQ0
+ .long 0xffffffe7 // Reset everything, but DSP
+ .long RESETREQ0ENA
+ .long 0x00000000
+ .long RESETREQ1ENA
+ .long 0xffffffff
+ .long RESETREQ1
+ .long 0xffffffff // Reset everything
+ .long RESETREQ1ENA
+ .long 0x00000000
+ .long RESETREQ2ENA
+ .long 0xffffffff
+ .long RESETREQ2
+ .long 0xffffffff // Reset everything
+ .long RESETREQ2ENA
+ .long 0x00000000
+ .long RESETREQ3ENA
+ .long 0xffffffff
+ .long RESETREQ3
+ .long 0xffffffff // Reset everything
+ .long RESETREQ3ENA
+ .long 0x00000000
+
+ .long 0x00000000 // (terminate)
+ .long 0x00000000
+
+param_table2:
+ .long GCLKCTRL0ENA
+ .long 0xffffffff
+ .long GCLKCTRL0
+ .long 0xffffffff // (default) module clock on
+ .long GCLKCTRL0ENA
+ .long 0x00000000
+ .long GCLKCTRL1ENA
+ .long 0xffffffff
+ .long GCLKCTRL1
+ .long 0xffffffff // (default) module clock on
+ .long GCLKCTRL1ENA
+ .long 0x00000000
+ .long GCLKCTRL2ENA
+ .long 0xffffffff
+ .long GCLKCTRL2
+ .long 0xffffffff // (default) module clock on
+ .long GCLKCTRL2ENA
+ .long 0x00000000
+ .long GCLKCTRL3ENA
+ .long 0xffffffff
+ .long GCLKCTRL3
+ .long 0xffffffff // (default) module clock on
+ .long GCLKCTRL3ENA
+ .long 0x00000000
+ .long GCLKCTRL4ENA
+ .long 0xffffffff
+ .long GCLKCTRL4
+ .long 0xffffffff // (default) module clock on
+ .long GCLKCTRL4ENA
+ .long 0x00000000
+ .long AHBCLKCTRL0
+ .long 0x00000000 // (default) prohibit automatic control
+ .long AHBCLKCTRL1
+ .long 0x00000000 // (default) prohibit automatic control
+ .long APBCLKCTRL0
+ .long 0x00000000 // (default) prohibit automatic control
+ .long APBCLKCTRL1
+ .long 0x00000000 // (default) prohibit automatic control
+ .long CLKCTRL
+ .long 0x00000000 // (default) prohibit automatic control
+ .long CLKCTRL1
+ .long 0x00000000
+
+ .long 0x00000000 // (terminate)
+ .long 0x00000000
+
+param_table3:
+ .long AB1_U70WAITCTRL
+ .long 0x00010200 // recommended value for 83MHz operation
+ .long AB1_U71WAITCTRL
+ .long 0x00010200 // recommended value for 83MHz operation
+ .long AB1_U72WAITCTRL
+ .long 0x00010200 // recommended value for 83MHz operation
+ .long AB1_IIC2WAITCTRL
+ .long 0x00010300 // recommended value for 83MHz operation
+ .long AB1_IICWAITCTRL
+ .long 0x00010300 // recommended value for 83MHz operation
+ .long AB1_SDIAWAITCTRL
+ .long 0x00010300
+ .long AB1_SDIBWAITCTRL
+ .long 0x00010300
+ .long AB1_SDICWAITCTRL
+ .long 0x00010300
+ .long AB1_U70READCTRL
+ .long 0x00000000 // (default)
+ .long AB1_U71READCTRL
+ .long 0x00000000 // (default)
+ .long AB1_U72READCTRL
+ .long 0x00000000 // (default)
+ .long AB1_IIC2READCTRL
+ .long 0x00000000 // (default)
+ .long AB1_IICREADCTRL
+ .long 0x00000000 // (default)
+ .long AB1_SDIAREADCTRL
+ .long 0x00000000 // (default)
+ .long AB1_SDIBREADCTRL
+ .long 0x00000000 // (default)
+ .long AB1_SDICREADCTRL
+ .long 0x00000000 // (default)
+
+ // memory map setup (CS0-3)
+ //
+ // 0x00000000 +----------------------------+
+ // | Bank0/CS0 (not used) |
+ // 0x10000000 +----------------------------+
+ // | Bank1/CS1 (not used) |
+ // 0x20000000 +----------------------------+
+ // | Bank2/CS2 (not used) |
+ // 0x28000000 +----------------------------+
+ // | Bank2/CS3 (LAN controller) |
+ // 0x30000000 +----------------------------+
+ .long AB0_CSnBASEADD(0)
+ .long 0x00000000
+ .long AB0_CSnBITCOMP(0)
+ .long 0xf0000000
+ .long AB0_CSnBASEADD(1)
+ .long 0x10000000
+ .long AB0_CSnBITCOMP(1)
+ .long 0xf0000000
+ .long AB0_CSnBASEADD(2)
+ .long 0x20000000
+ .long AB0_CSnBITCOMP(2)
+ .long 0xf8000000
+ .long AB0_CSnBASEADD(3)
+ .long 0x28000000
+ .long AB0_CSnBITCOMP(3)
+ .long 0xf8000000
+ .long AB0_FLASHCLKCTRL
+ .long 0x00000001 // AB0:Flash=1:2
+
+ // set up LAN controller
+ // Assuming the use of 83.333 MHz (12ns/1clk), we set the following values.
+ // CSint=1clk (Read+1clk=24ns, Write+2clk=36ns)
+ // T0=0clk (0ns), T1=3clk(36ns), T2=2clk(24ns)
+ .long AB0_CSnWAITCTRL(3)
+ .long 0x01020300
+ .long AB0_CSnWAITCTRL_W(3)
+ .long 0x00020300
+ .long AB0_CSnREADCTRL(3)
+ .long 0x00000000 // (default)
+ .long AB0_CSnWAIT_MASK(3)
+ .long 0x00000000 // (default)
+ .long AB0_CSnCONTROL(3)
+ .long 0x00010100 // (default)
+ .long AB0_FLASHCOMSET
+ .long 0x00000008 // CS3 value above is reflected.
+
+ .long 0x00000000 // (terminate)
+ .long 0x00000000
+
+/*----------------------------------------------------------------------
+ Reset processing
+----------------------------------------------------------------------*/
+ .text
+ .balign 4
+ .globl reset_entry
+ .type reset_entry, %function
+reset_entry:
+
+// SVC mode, FIQ/IRQ interrupt disabled
+ mov r0, #(PSR_SVC | PSR_I | PSR_F)
+ msr cpsr_fsxc, r0
+
+// Switch to T-Monitor stack
+ ldr sp, =__stack_bottom
+
+// not in effect: cache (D/I), program-flow prediction, High-Vector, VIC
+// in effect: Force AP, TEX remap, Subpage AP
+ .DSB r0
+ mrc p15, 0, r0, cr1, cr0, 0
+ ldr r1, =~0x01003f84
+ and r0, r0, r1
+ ldr r1, =0x30800000
+ orr r0, r0, r1
+ mcr p15, 0, r0, cr1, cr0, 0
+
+ .ISB r0
+ mcr p15, 0, r0, cr8, cr7, 0 // I/D TLB invalidate
+ .DSB r0
+ bl Csym(FlushCache) // Clean/invalidate I/D cache
+
+// Turn on VFP
+ mrc p15, 0, r0, cr1, cr0, 2
+ orr r0, r0, #0x00f00000 // VFP(CP11,CP10) enable
+ bic r0, r0, #0xc0000000 // Should be Zero
+ mcr p15, 0, r0, cr1, cr0, 2
+ .ISB r0 // Flush Prefetch buffer
+
+// initialize data area
+ ldr r1, =__data_org
+ ldr r2, =__data_start
+ ldr r3, =_edata
+data_loop:
+ ldmia r1!, {r4-r7} // copy in unit of 16 bytes
+ stmia r2!, {r4-r7}
+ cmp r2, r3
+ blo data_loop
+
+// clear bss and stack area
+ ldr r2, =__bss_start
+ ldr r3, =__stack_bottom
+ ldr r4, =0
+ ldr r5, =0
+ ldr r6, =0
+ ldr r7, =0
+bss_loop:
+ stmia r2!, {r4-r7} // clear in units of 16 bytes
+ cmp r2, r3
+ blo bss_loop
+
+// reset processing
+ bl procReset
+
+// clear registers & initialize stack pointer
+ ldr r7, =__stack_top // since it is 0-cleared, why not use it.
+
+ ldmia r7, {r8-r12,sp,lr}^ // usr: r8-r12, sp, lr
+
+ mov r0, #(PSR_FIQ | PSR_I | PSR_F)
+ msr cpsr_fsxc, r0
+ ldmia r7, {r8-r12,sp,lr} // fiq: r8-r12, sp, lr, spsr
+ msr spsr_fsxc, lr
+ ldr sp, =__stack_top + 32
+
+ mov r0, #(PSR_IRQ | PSR_I | PSR_F)
+ msr cpsr_fsxc, r0
+ ldr sp, =__stack_top + 16 // irq: sp, lr, spsr
+ mov lr, #0
+ msr spsr_fsxc, lr
+
+ mov r0, #(PSR_ABT | PSR_I | PSR_F)
+ msr cpsr_fsxc, r0
+ ldr sp, =__stack_top + 64 // abt: sp, lr, spsr
+ mov lr, #0
+ msr spsr_fsxc, lr
+
+ mov r0, #(PSR_UND | PSR_I | PSR_F)
+ msr cpsr_fsxc, R0
+ ldr sp, =__stack_top + 48 // und: sp, lr, spsr
+ mov lr, #0
+ msr spsr_fsxc, lr
+
+ // clear VFP
+ mov r0, #0x40000000 // EX=0,EN=1,SBZ/other flags = 0
+ fmxr fpexc, r0
+
+ mov r1, #0x00000000 // SBZ/other flags = 0
+ fmxr fpscr, r1
+
+ fldmiad r7, {d0-d15} // zero clear
+
+ // return to SVC mode
+ mov r0, #(PSR_SVC | PSR_I | PSR_F)
+ msr cpsr_fsxc, r0
+
+ ldmia r7, {r0-r7} // r0-r7
+
+// enter monitor by means of SVC #0 instruction (SVC mode)
+ resetLoop:
+ svc #0
+ b resetLoop // return will cause another reset
+
+ .pool
diff --git a/tkernel_source/monitor/hwdepend/arm/cpu/step.c b/tkernel_source/monitor/hwdepend/arm/cpu/step.c
new file mode 100644
index 0000000..6b1310d
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/cpu/step.c
@@ -0,0 +1,499 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by T-Engine Forum at 2013/03/04.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * step.c
+ *
+ * calculate step address
+ */
+
+#include "../cmdsvc.h"
+
+#define aINSTSZ 4 /* ARM instruction size */
+#define tINSTSZ 2 /* THUMB instruction size */
+#define REGBIT(reg) (1 << (reg)) /* register bit */
+#define REGSZ 4 /* register size */
+#define regPC 15 /* PC register */
+#define regSP 13 /* SP register */
+
+LOCAL UW curCPSR; /* cpsr */
+LOCAL UW nextPC; /* the next PC value */
+LOCAL W nextLen; /* size of the next instruction(2 or 4) */
+LOCAL UW repInst; /* instruction to replace */
+LOCAL W repReg; /* register to be replaced */
+LOCAL W trcNext; /* NEXT trace mode */
+
+/*
+ extraction of fields of an instruction
+*/
+LOCAL UW getInstField(UW mask, W sht)
+{
+ return (repInst & mask) >> sht;
+}
+/*
+ set the register field of the instruction to be replaced
+*/
+LOCAL void setRepInst(UW mask, W sht)
+{
+ repInst = (repInst & ~mask) | ((repReg & 0xF) << sht);
+}
+/*
+ Obtain an unused register for replacement
+*/
+LOCAL W getRepReg(UW reg)
+{
+ W i;
+
+ for (i = 0; i < 16 && (reg & 0x1); i++, reg >>= 1);
+ return i + 0x10; /* register number + flag */
+}
+/*
+ Validate instruction execution condition
+*/
+LOCAL W checkCond(W cond)
+{
+ UW sr = curCPSR;
+
+ switch(cond) {
+ case 0: /* EQ: z */
+ if (sr & PSR_Z) return 1; break;
+ case 1: /* NE: !z */
+ if (!(sr & PSR_Z)) return 1; break;
+ case 2: /* CS: c */
+ if (sr & PSR_C) return 1; break;
+ case 3: /* CC: !c */
+ if (!(sr & PSR_C)) return 1; break;
+ case 4: /* MI: n */
+ if (sr & PSR_N) return 1; break;
+ case 5: /* PL: !n */
+ if (!(sr & PSR_N)) return 1; break;
+ case 6: /* VS: v */
+ if (sr & PSR_V) return 1; break;
+ case 7: /* VC: !v */
+ if (!(sr & PSR_V)) return 1; break;
+ case 8: /* HI: c && !z */
+ if ((sr & (PSR_C | PSR_Z)) == PSR_C) return 1; break;
+ case 9: /* LS: !c || z */
+ if (!(sr& PSR_C) || (sr & PSR_Z)) return 1; break;
+ case 12: /* GT: !z && (n == v) */
+ if (sr & PSR_Z) return 0;
+ case 10: /* GE: n == v */
+ sr &= PSR_N | PSR_V;
+ if (sr == 0 || sr == (PSR_N | PSR_V)) return 1; break;
+ case 13: /* LE: z || (n != v) */
+ if (sr & PSR_Z) return 1;
+ case 11: /* LT: n != v */
+ sr &= PSR_N | PSR_V;
+ if (sr == PSR_N || sr == PSR_V) return 1; break;
+ case 14: /* AL: */
+ case 15: /* NV: */
+ return 1;
+ }
+ return 0;
+}
+/*
+ non-branching instruction
+*/
+LOCAL void noBranch(UW inst)
+{
+}
+/*
+ ARM: Bcond / BLX(1) instruction
+*/
+LOCAL void armBInst(UW inst)
+{
+ W off;
+
+ /* BL is not handled during NEXT trace */
+ if (trcNext) {
+ if (inst & 0x01000000) return; /* BL */
+ if (inst >= 0xF0000000) return; /* BLX(1) */
+ }
+ off = (inst & 0x00FFFFFF) << 2;
+ if (off & 0x02000000) off -= 0x04000000; /* sign extension */
+ nextPC += aINSTSZ + off;
+
+ if (inst >= 0xF0000000) { /* BLX(1) */
+ nextPC += getInstField(0x01000000, 24) << 1;
+ /* adjust for Thumb mode (on two bytes boundary) */
+ nextLen = tINSTSZ; /* THUMB mode */
+ }
+}
+/*
+ ARM: BX / BLX(2) instruction
+*/
+LOCAL void armBxInst(UW inst)
+{
+ /* BL is not handled during NEXT trace */
+ if (trcNext) {
+ if (inst & 0x00000020) return; /* BLX(2) */
+ }
+ inst &= 0x0000000F;
+ if (inst == regPC) {
+ nextPC += aINSTSZ;
+ } else {
+ nextPC = getRegister(inst);
+ }
+ if (nextPC & 1) nextLen = tINSTSZ; /* THUMB mode */
+}
+/*
+ ARM: data processing instruction rd = pc
+*/
+LOCAL void armOpInst(UW inst)
+{
+ W rn, rm;
+ UW usereg;
+
+ /* TST, TEQ, CMP, CMPN instructions are not handled */
+ rm = inst & 0x01E00000;
+ if (rm >= 0x01000000 && rm <= 0x01600000) return;
+
+ /* OP1 register */
+ rn = getInstField(0x000F0000, 16);
+ usereg = REGBIT(rn);
+
+ /* OP2 register */
+ if (!(inst & 0x02000000)) {
+ rm = getInstField(0x0000000F, 0);
+ usereg |= REGBIT(rm);
+ if (inst & 0x00000010) /* shift length register */
+ usereg |= REGBIT(getInstField(0x00000F00, 8));
+ }
+ /*register to be replaced */
+ repReg = getRepReg(usereg);
+
+ /* Dest register replacement */
+ setRepInst(0x0000F000, 12);
+
+ /* OP1 register replacement */
+ if (rn == regPC) setRepInst(0x000F0000, 16);
+
+ /* OP2 register replacement */
+ if (rm == regPC) setRepInst(0x0000000F, 0);
+
+ /* if S bit is set, we obtain the next mode from spsr. */
+ if ((inst & 0x00100000) && (getCurSPSR() & PSR_T)) nextLen = tINSTSZ;
+}
+/*
+ ARM: LDR pc instruction
+*/
+LOCAL void armLdrInst(UW inst)
+{
+ W rn, roff;
+ UW usereg;
+
+ /* base register */
+ rn = getInstField(0x000F0000, 16);
+ usereg = REGBIT(rn);
+
+ /* OFF register */
+ roff = 0;
+ if (inst & 0x02000000) {
+ roff = getInstField(0x0000000F, 0);
+ usereg |= REGBIT(roff);
+ }
+
+ /*register to be replaced */
+ repReg = getRepReg(usereg);
+
+ /* Dest register replacement */
+ setRepInst(0x0000F000, 12);
+
+ /* base register replacement */
+ if (rn == regPC) setRepInst(0x000F0000, 16);
+
+ /* offset register replacement */
+ if (roff == regPC) setRepInst(0x0000000F, 0);
+}
+/*
+ ARM: LDM {pc} instruction
+*/
+LOCAL void armLdmInst(UW inst)
+{
+ W i, off;
+ UW baddr;
+
+ /* memory base address */
+ baddr = getRegister(getInstField(0x000F0000, 16));
+
+ /* obtain PC address offset */
+ off = (inst & 0x01000000) ? REGSZ : 0; /* preindex */
+
+ if (inst & 0x00800000) { /* UP */
+ for (i = 0; i < regPC; i++) {
+ if (inst & REGBIT(i)) off += REGSZ;
+ }
+ baddr += off;
+ } else { /* DOWN */
+ baddr -= off;
+ }
+
+ /* Extract the value set to PC */
+ readMem(baddr, &nextPC, REGSZ, 2);
+
+ /* if S bit is set, we obtain the next mode from spsr. */
+ if ((inst & 0x00400000) && (getCurSPSR() & PSR_T)) nextLen = tINSTSZ;
+}
+/*
+ ARM: MRS / MRC instruction rd = pc
+*/
+LOCAL void armMrcsInst(UW inst)
+{
+ /* register to be replaced */
+ repReg = getRepReg(0);
+
+ /* Dest register replacement */
+ setRepInst(0x0000F000, 12);
+}
+#if CPU_ARMv6
+/*
+ ARM: RFE instruction
+*/
+LOCAL void armRfeInst(UW inst)
+{
+ W off;
+ UW baddr, saddr, paddr, spsr;
+
+ /* memory base address */
+ baddr = getRegister(getInstField(0x000F0000, 16));
+
+ /* obtain PC address offset */
+ off = (inst & 0x01000000) ? REGSZ : 0; /* preindex */
+
+ if (inst & 0x00800000) { /* UP */
+ paddr = baddr + off;
+ saddr = baddr + off + REGSZ;
+ } else { /* DOWN */
+ paddr = baddr - off - REGSZ;
+ saddr = baddr - off;
+ }
+
+ /* Extract the value set to PC */
+ readMem(paddr, &nextPC, REGSZ, 2);
+
+ /* obtain the next mode from the saved spsr inside stack. */
+ readMem(saddr, &spsr, REGSZ, 2);
+ if (spsr & PSR_T) nextLen = tINSTSZ;
+}
+#endif
+/*
+ THUMB: Bcond instruction
+*/
+LOCAL void thumbBcondInst(UW inst)
+{
+ W cond, off;
+
+ cond = getInstField(0x0F00, 8);
+
+ /* undefined instruction is not supported */
+ if (cond == 14) return;
+
+ /* check conditions */
+ if (!checkCond(cond)) return;
+
+ off = (inst & 0x00FF) << 1;
+ if (off >= 0x100) off -= 0x200; /* sign extension */
+ nextPC += tINSTSZ + off;
+}
+/*
+ THUMB: B instruction
+*/
+LOCAL void thumbBInst(UW inst)
+{
+ W off;
+
+ off = (inst & 0x07FF) << 1;
+ if (off >= 0x800) off -= 0x1000; /* sign extension */
+ nextPC += tINSTSZ + off;
+}
+/*
+ THUMB: BX / BLX(2) instruction
+*/
+LOCAL void thumbBxInst(UW inst)
+{
+ /* BL is not handled during NEXT trace */
+ if (inst & 0x0080) { /* BLX(2) */
+ if (trcNext) return;
+ }
+ inst = getInstField(0x0078, 3);
+ if (inst == regPC) {
+ nextPC += tINSTSZ;
+ } else {
+ nextPC = getRegister(inst); /* including Hi register */
+ }
+ if (!(nextPC & 1)) nextLen = aINSTSZ;
+}
+/*
+ THUMB: BL / BLX(1) instruction
+*/
+LOCAL void thumbBlInst(UW inst)
+{
+ W off;
+ UH inst2;
+
+ /* BL is not handled during NEXT trace */
+ if (trcNext) return;
+
+ /* Extract 2nd instruction */
+ readMem(nextPC, &inst2, tINSTSZ, 2);
+
+ off = (inst & 0x07FF) << 12;
+ if (off >= 0x400000) off -= 0x800000; /* sign extension */
+ nextPC += tINSTSZ + off + ((inst2 & 0x07FF) << 1);
+ if (!(inst2 & 0x1000)) nextLen = aINSTSZ; /* BLX(1) */
+}
+/*
+ THUMB: ADD|CMP|MOV Rd/Rn,Rm instruction rd = pc
+*/
+LOCAL void thumbOp6Inst(UW inst)
+{
+ UW op, dreg, mreg;
+
+ op = inst & 0x0300;
+ if (op == 0x0100) return; /* compare instruction */
+
+ dreg = getInstField(0x0007, 0);
+ if (inst & 0x0080) dreg |= 0x8; /* Hi register */
+ if (dreg != regPC) return; /* not PC register */
+
+ mreg = getInstField(0x0078, 3); /* including Hi register */
+ nextPC = getRegister(mreg) & ~(tINSTSZ - 1);
+
+ /* calculate PC */
+ if (op == 0x0000) nextPC += getRegister(dreg); /* ADD */
+}
+/*
+ THUMB: POP instruction pc
+*/
+LOCAL void thumbPopInst(UW inst)
+{
+ W i;
+ UW sp;
+
+ sp = getRegister(regSP);
+ for (i = 0; i < 8; i++) {
+ if (inst & REGBIT(i)) sp += REGSZ;
+ }
+ /* extract PC */
+ readMem(sp, &nextPC, REGSZ, 2);
+}
+
+/* Arm instruction decode table */
+typedef struct {
+ UW mask; /* mask */
+ UW code; /* code */
+ void (*calcNextPC)(UW inst); /* calculate PC */
+} INST_T;
+
+LOCAL const INST_T instArm[] = {
+ { 0xFFFFFFFF, 0xE1A00000, noBranch}, /* NOP */
+ { 0xFFF000F0, 0xE1200070, noBranch}, /* BKPT(ARM5T) */
+ { 0x0FFFFFF0, 0x012FFF10, armBxInst}, /* BX */
+ { 0xFE000000, 0xFA000000, armBInst}, /* BLX(1)(ARM5T) */
+ { 0x0FF000F0, 0x01200030, armBxInst}, /* BLX(2)(ARM5T) */
+ { 0x0E000000, 0x0A000000, armBInst}, /* B,BL */
+ { 0x0F000000, 0x0F000000, noBranch}, /* SWI */
+ { 0x0C10F000, 0x0410F000, armLdrInst}, /* LDR pc */
+ { 0x0E108000, 0x08108000, armLdmInst}, /* LDM {pc} */
+/* { 0x0F000010, 0x0E000000, noBranch}, */ /* CDP */
+/* { 0x0E000000, 0x0C000000, noBranch}, */ /* LDC/STC */
+ { 0x0F10F010, 0x0E10F010, armMrcsInst}, /* MRC pc */
+ { 0x0FBFFFFF, 0x010FF000, armMrcsInst}, /* MRS pc */
+/* { 0x0F0000F0, 0x00000090, noBranch},*/ /* MULL */
+ { 0x0E000090, 0x00000090, noBranch}, /* LDR/STR Half/SByte */
+/* { 0x0DB0F000, 0x0120F000, noBranch},*/ /* MSR */
+/* { 0x0FB00FF0, 0x01000090, noBranch},*/ /* SWP */
+ { 0x0C00F000, 0x0000F000, armOpInst}, /* ADD/SUB.. rd = pc */
+#if CPU_ARMv6
+ { 0xFE50FFFF, 0xF8100A00, armRfeInst}, /* RFE(ARMv6) */
+#endif
+ { 0 }
+};
+
+/* Thumb instruction decode table */
+LOCAL const INST_T instThumb[] = {
+ /* { 0xF801, 0xE800, thumbBlInst}, // BLX(1)(ARM5T) 2Nd Inst */
+ { 0xFF00, 0xBE00, noBranch}, /* BKPT(ARM5T) */
+ { 0xFFFF, 0x46C0, noBranch}, /* NOP */
+ { 0xFF00, 0xDF00, noBranch}, /* SWI */
+ { 0xF800, 0xE000, thumbBInst}, /* B <label> */
+ { 0xF000, 0xD000, thumbBcondInst},/* B<cond> <label> */
+ { 0xF000, 0xF000, thumbBlInst}, /* BL,BLX(1)(ARM5T) */
+ { 0xFF80, 0x4780, thumbBxInst}, /* BLX(2)(ARM5T) */
+ { 0xFF00, 0x4700, thumbBxInst}, /* BX */
+#if 0
+ { 0xFC00, 0x1800, noBranch}, /* OP(1)ADD|SUB Rd,Rn,Rm */
+ { 0xFC00, 0x1C00, noBranch}, /* OP(2)ADD|SUB Rd,Rn,#imm3 */
+ { 0xE000, 0x2000, noBranch}, /* OP(3)<OP> Rd/Rn,#imm8 */
+ { 0xE000, 0x0000, noBranch}, /* OP(4)LSL|LSR|ASR Rd, Rn, Rn,#shift */
+ { 0xFC00, 0x4000, noBranch}, /* OP(5)<OP> Rd/Rn,Rm/Rs */
+#endif
+ { 0xFC00, 0x4400, thumbOp6Inst}, /* OP(6)ADD|CMP|MOV Rd/Rn,Rm */
+#if 0
+ { 0xF000, 0xA000, noBranch}, /* OP(7)ADD Rd,SP|PC,#imm8 */
+ { 0xFF00, 0xB000, noBranch}, /* OP(8)ADD|SUB SP,SP,#imm7 */
+ { 0xE000, 0x6000, noBranch}, /* LS(1)LDR|STR(B) Rd,[Rn,#off5] */
+ { 0xF000, 0x8000, noBranch}, /* LS(2)LDRH|STRH Rd,[Rn,#off5] */
+ { 0xF000, 0x5000, noBranch}, /* LS(3)LDR|STR(S){H|B} Rd,[Rn,Rm] */
+ { 0xF800, 0x4800, noBranch}, /* LS(4)LDR Rd,[PC,#off8] */
+ { 0xF000, 0x9000, noBranch}, /* LS(5)LDR|STR Rd,[SP,#off8] */
+ { 0xF000, 0xC000, noBranch}, /* LDMIA|STMIA Rn!,{<reg list>} */
+#endif
+ { 0xFD00, 0xBD00, thumbPopInst}, /* POP {<reg list,PC}>} */
+ { 0 }
+};
+/*
+ Obtain the next step address
+*/
+EXPORT W getStepAddr(UW pc, UW cpsr, W mode, UW* npc, UW *rep)
+{
+ W len;
+ UW inst;
+ INST_T *tab;
+
+ /* set mode */
+ len = (cpsr & PSR_T) ? tINSTSZ : aINSTSZ;
+ curCPSR = cpsr; /* cpsr */
+ repReg = 0; /* register to replace */
+ repInst = 0; /* instruction to replace */
+ nextPC = pc + len; /* the next PC value for non-branching instruction */
+ nextLen = len; /* size of the next instruction */
+ trcNext = mode; /* NEXT trace */
+
+ /* extract op code */
+ if (readMem(pc, &inst, len, 2) != len) goto EXIT;
+ repInst = inst; /* instruction to replace */
+
+ if (len == 4) { /* ARM instruction */
+ /* check the conditional execution */
+ if (!checkCond(getInstField(0xF0000000, 28))) goto EXIT;
+ tab = (INST_T*)instArm;
+ } else { /* THUMB instruction */
+ tab = (INST_T*)instThumb;
+ inst &= 0xFFFF;
+ }
+
+ /* search instruction and calculate next PC */
+ for ( ; tab->mask != 0; tab++) {
+ if ((inst & tab->mask) == tab->code) {
+ (*(tab->calcNextPC))(inst);
+ break;
+ }
+ }
+EXIT:
+ *npc = nextPC & ~(nextLen - 1);
+ *rep = repInst;
+ return nextLen | (repReg << 4);
+}
diff --git a/tkernel_source/monitor/hwdepend/arm/include/asm/cpudep.h b/tkernel_source/monitor/hwdepend/arm/include/asm/cpudep.h
new file mode 100644
index 0000000..e7ef92d
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/include/asm/cpudep.h
@@ -0,0 +1,79 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * cpudep.h
+ *
+ * CPU-dependent definitions(ARM)
+ */
+
+#include <tk/sysdef.h>
+
+#ifndef _in_asm_source_
+
+IMPORT W bootFlag; /* boot flag */
+
+/*
+ * Memory access through physical address
+ * In the case of ARM, actually it is an access by logical address.
+ */
+Inline UW rd_w( UW *pa )
+{
+ return *pa;
+}
+Inline UH rd_h( UH *pa )
+{
+ return *pa;
+}
+Inline UB rd_b( UB *pa )
+{
+ return *pa;
+}
+
+Inline void wr_w( UW *pa, UW data )
+{
+ *pa = data;
+}
+Inline void wr_h( UH *pa, UH data )
+{
+ *pa = data;
+}
+Inline void wr_b( UB *pa, UB data )
+{
+ *pa = data;
+}
+
+/*
+ * read/write the ARM-specific registered under monitor management
+ * read/set the value of registers at the time of monitor entry.
+ */
+IMPORT UW getCP15( W reg, W opcd ); /* CP15 register reg: CRn, opcd: Op2 */
+IMPORT UW getCurPCX( void ); /* PC register (unmodified) */
+IMPORT void setCurPCX( UW val ); /* PC register (unmodified) */
+IMPORT UW getCurCPSR( void ); /* CPSR register */
+IMPORT UW getCurSPSR( void ); /* SPSR register */
+
+/*
+ * Validate PC address
+ * Allow only ARM instructions (on 4 bytes boundary).
+ * If addr is valid then return 0, otherwise return -1.
+ */
+IMPORT W invalidPC2( UW addr );
+
+/*
+ * obtain step address
+ */
+IMPORT W getStepAddr( UW pc, UW cpsr, W mode, UW* npc, UW *rep );
+
+#endif /* _in_asm_source_ */
diff --git a/tkernel_source/monitor/hwdepend/arm/lib/monitor.lnk b/tkernel_source/monitor/hwdepend/arm/lib/monitor.lnk
new file mode 100644
index 0000000..590651c
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/lib/monitor.lnk
@@ -0,0 +1,112 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * monitor.lnk
+ *
+ * link specification for monitor
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+
+SECTIONS {
+ __loadaddr = 0x70000000;
+ _start = 0x70000000;
+ .eitbra _start : AT(__loadaddr) {
+ __eitbra_start = .;
+ *(EITBRA)
+ . = ALIGN(0x10);
+ }
+ .startup : {
+ *(.startup)
+ . = ALIGN(0x10);
+ }
+ __text_org = __loadaddr + SIZEOF(.startup) + SIZEOF(.eitbra);
+ .text __text_org : {
+ _stext = .;
+ KEEP (*(.init))
+ *(.text)
+ *(.text.*)
+ *(.stub)
+ *(.glue_7t)
+ *(.glue_7)
+ KEEP (*(.fini))
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+ *(.rodata)
+ *(.rodata.*)
+ *(.rodata1)
+ . = ALIGN(0x10);
+ } =0
+ __data_org = . ;
+ .data 0x30004440 : AT(LOADADDR(.text) + SIZEOF(.text)) {
+ __data_start = . ;
+ *(flashwr.rodata)
+ *(.data)
+ *(.data.*)
+ SORT(CONSTRUCTORS)
+ *(.data1)
+ KEEP (*(.eh_frame))
+ *(.gcc_except_table)
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ *(.got.plt)
+ *(.got)
+ *(.sdata)
+ *(.sdata.*)
+ . = ALIGN(0x10);
+ _edata = .;
+ PROVIDE (edata = .);
+ }
+ .bss (NOLOAD) : AT(LOADADDR(.data) + SIZEOF(.data)) {
+ __bss_start = .;
+ PROVIDE (__sbss_start = .);
+ PROVIDE (___sbss_start = .);
+ *(.sbss)
+ *(.sbss.*)
+ *(.scommon)
+ PROVIDE (__sbss_end = .);
+ PROVIDE (___sbss_end = .);
+ *(.bss)
+ *(.bss.*)
+ *(EXCLUDE_FILE(*/wrkbuf.o) COMMON)
+ . = ALIGN(0x10);
+ _end = .;
+ PROVIDE (end = .);
+ }
+ __flashwr_org = __data_org + SIZEOF(.data);
+ OVERLAY : AT(LOADADDR(.bss)) {
+ .flashwr {
+ __flashwr_start = .;
+ *(flashwr.text)
+ __flashwr_end = .;
+ }
+ .wrkbuf {
+ */wrkbuf.o(COMMON)
+ }
+ }
+ .stack ALIGN(0x10) (NOLOAD) : {
+ __stack_top = .;
+ __stack_bottom = 0x30006000 - ABSOLUTE(.);
+ }
+}
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-em1d/chkaddr.c b/tkernel_source/monitor/hwdepend/arm/mach-em1d/chkaddr.c
new file mode 100644
index 0000000..1e88e62
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-em1d/chkaddr.c
@@ -0,0 +1,136 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * chkaddr.c
+ *
+ * Check address
+ */
+
+#include "../cmdsvc.h"
+
+LOCAL UW validLA; /* valid logical start address */
+LOCAL UW validSz; /* valid logical address size */
+LOCAL UW mmuStat; /* MMU state */
+
+/*
+ Initialize address check data (executed upon monitor entry)
+*/
+EXPORT void initChkAddr(void)
+{
+ validLA = validSz = 0; /* clear the previous effective addresses */
+ mmuStat = getCP15(1, 0); /* MMU state */
+}
+/*
+ Check memory address
+ return contiguous range <= len (0 means illegal value)
+ * pa physical address to access
+*/
+EXPORT W chkMemAddr(UW addr, UW *pa, W len, W rw)
+{
+ const MEMSEG *mp;
+ UW n;
+
+ if (mmuStat & 0x1) { /* MMU is enabled */
+ /* if the prevous check range doesn't include the address, */
+ /* if the address is a valid existing address is checked by looking at page table. */
+ if (addr < validLA || addr >= validLA + validSz) {
+ UW pte, *ppte;
+
+ /* Depending on the valid rage of TTBR0 described in TTBCR */
+ /* TTBR0/TTBR1(=TopPageTable) is switched */
+ pte = 0xfe000000 << (7 - (getCP15(2, 2) & 0x07));
+ /* TTBCR */
+ ppte = (addr & pte) ? TopPageTable :
+ (UW *)(getCP15(2, 0) & ~0x7f); /* TTBR0 */
+ pte = ppte[addr >> 20];
+
+ validSz = 0;
+ switch(pte & 0x3) {
+ case 0x2: /* Section Entry */
+ pte &= 0xFFF00000; /* Section Address */
+ if (rw && AddrMatchMemArea(pte,
+ MSA_ROM|MSA_FROM) != NULL)
+ errinfo = E_ROM;
+ else validSz = 0x100000; /* 1 MB */
+ break;
+ case 0x1: /* Page Table Entry */
+ pte &= 0xFFFFFC00; /* Page Table Address */
+ pte = *((UW*)(pte + ((addr >>(12-2))& 0x3FC)));
+ switch(pte & 0x3) {
+ case 0x1: /* Large Page : 16 KB x 4 */
+ validSz = 0x10000; /* 64 KB */
+ break;
+ case 0x2: /* Small Page : 1 KB x 4 */
+ case 0x3: /* Small Page with XN */
+ validSz = 0x1000; /* 4 KB */
+ break;
+ }
+ break;
+ case 0x3: /* Fine Page Table Entry */
+ break; /* unsupported */
+ }
+ validLA = (validSz) ? (addr & ~(validSz - 1)) : 0;
+ }
+
+ n = (validSz) ? (validLA + validSz - addr) : 0;
+
+ } else { /* MMU is disabled, the unmodified address is used */
+ mp = AddrMatchMemArea(addr, MSA_HW);
+ if ( mp != NULL ) {
+ if ( rw && (mp->attr & (MSA_ROM|MSA_FROM)) != 0 ) {
+ n = 0;
+ errinfo = E_ROM;
+ } else {
+ n = mp->end - addr;
+ }
+ } else {
+ n = 0;
+ }
+ }
+ *pa = addr; /* access by logical address */
+ return (len > n) ? n : len;
+}
+/*
+ I/O address check & conversion to physical address
+ return contiguous range <= len (0 means illegal value)
+ * pa I/O address to access
+*/
+EXPORT W chkIOAddr(UW addr, UW *pa, W len)
+{
+ const MEMSEG *mp;
+ UW n;
+
+ mp = AddrMatchMemArea(addr, MSA_IO);
+ n = ( mp != NULL )? mp->end - addr: 0;
+
+ *pa = addr; /* access by logical address */
+ return (len > n) ? n : len;
+}
+/*
+ Validate PC
+ return 0: OK, -1: illegal
+*/
+EXPORT W invalidPC(UW addr)
+{
+ /* memory range check is not performed */
+ /* an odd address needs to be regarded as THUMB, and so nothing is done here. */
+ return 0;
+}
+EXPORT W invalidPC2(UW addr)
+{
+ /* memory range check is not performed */
+ /* PC of an ARM instruction is always on WORD-boundary */
+ return (addr & 0x03) ? -1 : 0;
+}
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-em1d/config.c b/tkernel_source/monitor/hwdepend/arm/mach-em1d/config.c
new file mode 100644
index 0000000..d6fda24
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-em1d/config.c
@@ -0,0 +1,669 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by T-Engine Forum at 2011/09/08.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * config.c
+ *
+ * system-related processing / system configuration information
+ *
+ * target: T-Engine/EM1D-512
+ */
+
+#include "sysdepend.h"
+#include <arm/em1d512.h>
+
+/* used device driver */
+IMPORT ER initSIO_ns16550(SIOCB *, const CFGSIO *, W speed);
+IMPORT ER initMemDisk(DISKCB *, const CFGDISK *);
+
+/* memory region definition */
+EXPORT MEMSEG MemSeg[] = {
+ /* Bank1/2/3 */
+ {0x10000000, 0x30000000, MSA_IO, PGA_RW|PGA_D |PGA_S|PGA_XN},
+ /* DDR2 SDRAM, 64Mbyte */
+ {0x30000000, 0x40000000, MSA_RAM, PGA_RW|PGA_C},
+ /* EM1 internal device (1) */
+ {0x40000000, 0x70000000, MSA_IO, PGA_RW|PGA_D |PGA_S|PGA_XN},
+ /* Bank0 */
+ {0x70000000, 0x72000000, MSA_FROM, PGA_RO|PGA_C |0x90000000},
+ /* EM1 internal SRAM */
+ {0xa0000000, 0xb0000000, MSA_SRAM, PGA_RW|PGA_NC},
+ /* EM1 internal device (2) */
+ {0xb0000000, 0xd0000000, MSA_IO, PGA_RW|PGA_D |PGA_S|PGA_XN},
+ /* EM1 internal Boot ROM */
+ {0xf0000000, 0xffffffff, MSA_ROM, PGA_RO|PGA_NC},
+
+ {0x70000000, 0x70020000, MSA_MON, 0},
+ {0x70030000, 0x72000000, MSA_RDA, 0},
+ {0x30006000, 0x34000000, MSA_OS, 0},
+};
+
+EXPORT W N_MemSeg = sizeof(MemSeg) / sizeof(MEMSEG);
+
+/* unused memory region definition */
+EXPORT MEMSEG NoMemSeg[] = {
+ {0x00000000, 0x10000000, 0, 0},
+ {0x72000000, 0xa0000000, 0, 0},
+ {0xd0000000, 0xf0000000, 0, 0},
+};
+
+EXPORT W N_NoMemSeg = sizeof(NoMemSeg) / sizeof(MEMSEG);
+
+/*
+ * serial port configuration definition
+ * list in the order of port number
+ */
+EXPORT const CFGSIO ConfigSIO[] = {
+ {initSIO_ns16550, 0},
+};
+
+EXPORT const W N_ConfigSIO = sizeof(ConfigSIO) / sizeof(CFGSIO);
+
+
+/*
+ * disk drive configuration definition
+ * list in the order of port number
+ */
+EXPORT const CFGDISK ConfigDisk[] = {
+ {"rda", DA_RONLY, initMemDisk, 0}, /* FlashROM */
+};
+
+EXPORT const W N_ConfigDisk = sizeof(ConfigDisk) / sizeof(CFGDISK);
+
+/* boot information */
+EXPORT const UH BootSignature = 0xe382; /* signature */
+EXPORT UB * const PBootAddr = (UB *)0x30200000; /* primary boot loader address */
+
+/* ------------------------------------------------------------------------ */
+
+#define IICC_IICE (1 << 7)
+#define IICC_WREL (1 << 5)
+#define IICC_WTIM (1 << 3)
+#define IICC_ACKE (1 << 2)
+#define IICC_STT (1 << 1)
+#define IICC_SPT (1 << 0)
+
+#define IICCL_SMC (1 << 3)
+#define IICCL_DFC (1 << 2)
+
+#define IICSE_MSTS (1 << 15)
+#define IICSE_ALD (1 << 14)
+#define IICSE_ACKD (1 << 10)
+#define IICSE_SPD (1 << 8)
+
+#define IICF_IICBSY (1 << 6)
+#define IICF_STCEN (1 << 1)
+#define IICF_IICRSV (1 << 0)
+
+#define IIC_TOPDATA (1 << 11)
+#define IIC_LASTDATA (1 << 10)
+
+#define TIMEOUT 1000000 /* microsec */
+
+#define IIC2_IRQ 39
+#define IRQbit(x) (1 << ((x) % 32))
+
+/* wait for register state information */
+LOCAL ER wait_state(UW addr, UW mask, UW value)
+{
+ W i;
+
+ for (i = TIMEOUT; i > 0; i--) {
+ waitUsec(1);
+ if ((in_w(addr) & mask) == value) break;
+ }
+
+ return i ? E_OK : E_TMOUT;
+}
+
+/* interrupt Raw status / clear */
+LOCAL void clear_int(void)
+{
+ out_w(IT0_IIR, IRQbit(IIC2_IRQ)); /* IRQ39 clear */
+ return;
+}
+
+/* interrupt Raw status / useable */
+LOCAL void setup_int(void)
+{
+ out_w(IT_PINV_CLR1, IRQbit(IIC2_IRQ));
+ out_w(IT0_IENS1, IRQbit(IIC2_IRQ));
+ clear_int();
+ return;
+}
+
+/* wait for interrupt Raw status */
+LOCAL ER wait_int(void)
+{
+ ER er;
+
+ er = wait_state(IT0_RAW1, IRQbit(IIC2_IRQ), IRQbit(IIC2_IRQ));
+ clear_int();
+
+ return er;
+}
+
+/* start / restart */
+LOCAL ER send_start(UB addr)
+{
+ ER er;
+ UW sts;
+
+ /* generate start condition */
+ out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) & ~IICC_ACKE);
+ out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_STT);
+
+ /* wait for reserving a master */
+ er = wait_state(IIC_IICSE(IIC2), IICSE_MSTS, IICSE_MSTS);
+ if (er < E_OK) goto fin0;
+
+ /* slave address / communication mode transmission */
+ out_w(IIC_IIC(IIC2), addr);
+ er = wait_int();
+ if (er < E_OK) goto fin0;
+
+ /* error check */
+ sts = in_w(IIC_IICSE(IIC2));
+ if ((sts & IICSE_ALD) || !(sts & IICSE_ACKD)) {
+ er = E_IO;
+ goto fin0;
+ }
+
+ er = E_OK;
+fin0:
+ return er;
+}
+
+/* stop */
+LOCAL ER send_stop(void)
+{
+ ER er;
+
+ /* generate stop condition */
+ out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_SPT);
+
+ /* wait for sending STOP bit(s) */
+ er = wait_state(IIC_IICSE(IIC2), IICSE_SPD, IICSE_SPD);
+
+ return er;
+}
+
+/* data transmission */
+LOCAL ER send_data(UB data)
+{
+ ER er;
+ UW sts;
+
+ /* data transmission */
+ out_w(IIC_IIC(IIC2), data);
+ er = wait_int();
+ if (er < E_OK) goto fin0;
+
+ /* NAK check */
+ sts = in_w(IIC_IICSE(IIC2));
+ if (!(sts & IICSE_ACKD)) {
+ er = E_IO;
+ goto fin0;
+ }
+
+ er = E_OK;
+fin0:
+ return er;
+}
+
+/* data receive */
+LOCAL W recv_data(W attr)
+{
+ W er;
+
+ /* when the first data is received, switch to receive mode */
+ if (attr & IIC_TOPDATA) {
+ out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) & ~IICC_WTIM);
+ out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_ACKE);
+ }
+
+ /* instruct the reception of data */
+ out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_WREL);
+ er = wait_int();
+ if (er < E_OK) goto fin0;
+
+ /* read data */
+ er = in_w(IIC_IIC(IIC2)) & 0xff;
+fin0:
+ /* when an error occurs, or the last byte is seen, then perform the post processing */
+ if ((attr & IIC_LASTDATA) || er < E_OK) {
+ out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_WTIM);
+ out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) & ~IICC_ACKE);
+ out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_WREL);
+ wait_int();
+ }
+
+ return er;
+}
+
+/* start IIC send/receive */
+LOCAL ER iic_start(void)
+{
+ ER er;
+
+ /* initialization default */
+ out_w(IIC_IICC(IIC2), 0); /* stop completely */
+ out_w(IIC_IICCL(IIC2), IICCL_SMC | IICCL_DFC); /* fast mode + filter */
+ out_w(IIC_IICF(IIC2), IICF_STCEN | IICF_IICRSV);/* forcibly start transmission */
+ out_w(IIC_IICC(IIC2), IICC_IICE | IICC_WTIM); /* IIC mode, 9bit mode */
+ clear_int();
+
+ /* wait for bus to become available (since there is only one master, the bus is supposed to be unoccupied) */
+ er = wait_state(IIC_IICF(IIC2), IICF_IICBSY, 0);
+
+ return er;
+}
+
+/* stop IIC send/receive */
+LOCAL void iic_finish(void)
+{
+ out_w(IIC_IICC(IIC2), 0); /* stop completely */
+ return;
+}
+
+/* read IIC-GPIO */
+LOCAL W IICGPIORead(W addr)
+{
+ W dat;
+
+ setup_int();
+
+ iic_start();
+ send_start(addr);
+ dat = recv_data(IIC_TOPDATA | IIC_LASTDATA);
+ send_stop();
+ iic_finish();
+
+ clear_int();
+
+ return dat;
+}
+
+/* IIC-GPIO write */
+LOCAL void IICGPIOWrite(W addr, W dat)
+{
+ setup_int();
+
+ iic_start();
+ send_start(addr);
+ send_data(dat);
+ send_stop();
+ iic_finish();
+
+ clear_int();
+
+ return;
+}
+
+/* ------------------------------------------------------------------------ */
+
+IMPORT W pmicRead(W reg);
+IMPORT W pmicWrite(W reg, W dat);
+#define pmicDelay(x) waitUsec(4) /* about 16msec */
+#define USBPowerOn 0xe0 /* GPIO13(OD), High * power is supplied to A connector only */
+#define USBPowerOff 0xe0 /* GPIO13(OD), High */
+
+/* obtain DipSw status */
+EXPORT UW DipSwStatus(void)
+{
+ UW d;
+
+ /* read data from read port */
+ d = IICGPIORead(0xd9);
+
+ /* unnecessary bits are masked and then invert logic. */
+ d = (d ^ SW_MON) & SW_MON;
+
+ /* check abort switch */
+ if (in_w(GIO_I(GIO_L)) & 0x00000100) d |= SW_ABT;
+
+ return d;
+}
+
+/* USB power control */
+EXPORT void usbPower(BOOL power)
+{
+ pmicWrite(27, (pmicRead(27) & 0x0f) |
+ (power ? USBPowerOn : USBPowerOff));
+ pmicDelay();
+}
+
+/* power off */
+EXPORT void powerOff(void)
+{
+ W i;
+
+ for (i = 10; i < 14; i++) pmicWrite(i, 0xff); /* IRQ_MASK_A-D (mask) */
+ pmicDelay();
+
+ for (i = 5 ; i < 9; i++) pmicWrite(i, 0xff); /* EVENT_A-D (clear) */
+ pmicDelay();
+
+ while (1) {
+ pmicWrite(15, 0x60); /* DEEP_SLEEP */
+ pmicDelay();
+ }
+}
+
+/* reset start*/
+EXPORT void resetStart(void)
+{
+ while (1) {
+ /* reset */
+ pmicWrite(15, 0xac); /* SHUTDOWN */
+ pmicDelay();
+ }
+}
+
+/* initialize hardware peripherals (executed only during reset) */
+EXPORT void initHardware(void)
+{
+ /* enable abort switch interrupt */
+ out_w(GIO_IDT1(GIO_L), 0x00000008); /* asynchronous leading-edge high interrupt */
+ out_w(GIO_IIR(GIO_L), 0x00000100);
+ out_w(GIO_IIA(GIO_L), 0x00000100);
+ out_w(GIO_IEN(GIO_L), 0x00000100);
+
+ return;
+}
+
+/* LED on/off */
+EXPORT void cpuLED(UW v)
+{
+ UB m, d, r, c;
+
+ m = ~((v >> 16) | 0xf0); /* mask (0:unmodified 1:modify) */
+ d = ~((v >> 0) | 0xf0); /* set value (0:on 1:off) */
+ r = IICGPIORead(0xb9);
+ c = (r ^ d) & m; /* modify flag (0:unmodified 1:modify) */
+ IICGPIOWrite(0xb8, r ^ c);
+}
+
+/*
+ * machine-dependent interrupt processing
+ * vec interrupt vector number
+ * return value 0: unsupported target
+ * 1: for the supported target, processing was performed. (monitor still continues)
+ * 2: for the supported target, proceesing was performed (interrupt handler is exited)
+ */
+EXPORT W procHwInt(UW vec)
+{
+ /* only abort switch (GPIO(P8)) is supported */
+ if (vec != EIT_GPIO(8)) return 0;
+
+ /* clear interrupt */
+ out_w(GIO_IIR(GIO_L), 0x00000100);
+
+ DSP_S("Abort Switch (SW1) Pressed");
+ return 1;
+}
+
+/* ------------------------------------------------------------------------ */
+
+/*
+ configure GPIO pin multiplexer
+
+ * : used functions
+
+ pin name function 0(00) function1(01) function2(10) function3(11)
+ GIO_P0 GIO_P0*
+ GIO_P1 GIO_P1* USB_WAKEUP USB_PWR_FAULT
+ GIO_P2 GIO_P2*
+ GIO_P3 GIO_P3*
+ GIO_P4 GIO_P4* NAND_RB1
+ GIO_P5 GIO_P5 NAND_RB2 CAM_SCLK*
+ GIO_P6 GIO_P6* NAND_RB3
+ GIO_P7 GIO_P7* NAND_CE0
+ GIO_P8 GIO_P8* NAND_CE1
+ GIO_P9 GIO_P9* NAND_CE2
+ GIO_P10 GIO_P10* NAND_CE3
+ AB0_CLK GIO_P11 AB0_CLK* NTS_CLK
+ AB0_AD0 GIO_P12 AB0_AD0*
+ AB0_AD1 GIO_P13 AB0_AD1*
+ AB0_AD2 GIO_P14 AB0_AD2*
+ AB0_AD3 GIO_P15 AB0_AD3*
+
+ pin name function 0(00) function1(01) function2(10) function3(11)
+ AB0_AD4 GIO_P16 AB0_AD4*
+ AB0_AD5 GIO_P17 AB0_AD5*
+ AB0_AD6 GIO_P18 AB0_AD6*
+ AB0_AD7 GIO_P19 AB0_AD7*
+ AB0_AD8 GIO_P20 AB0_AD8*
+ AB0_AD9 GIO_P21 AB0_AD9*
+ AB0_AD10 GIO_P22 AB0_AD10*
+ AB0_AD11 GIO_P23 AB0_AD11*
+ AB0_AD12 GIO_P24 AB0_AD12*
+ AB0_AD13 GIO_P25 AB0_AD13*
+ AB0_AD14 GIO_P26 AB0_AD14*
+ AB0_AD15 GIO_P27 AB0_AD15*
+ AB0_A17 GIO_P28 AB0_A17*
+ AB0_A18 GIO_P29 AB0_A18*
+ AB0_A19 GIO_P30 AB0_A19*
+ AB0_A20 GIO_P31 AB0_A20*
+
+ pin name function 0(00) function1(01) function2(10) function3(11)
+ AB0_A21 GIO_P32 AB0_A21*
+ AB0_A22 GIO_P33 AB0_A22*
+ AB0_A23 GIO_P34 AB0_A23*
+ AB0_A24 GIO_P35 AB0_A24*
+ AB0_A25 GIO_P36* AB0_A25
+ AB0_A26 GIO_P37* AB0_A26
+ AB0_ADV GIO_P38 AB0_ADV*
+ AB0_RDB GIO_P39 AB0_RDB* NTS_DATA3
+ AB0_WRB GIO_P40 AB0_WRB* NTS_DATA4
+ AB0_WAIT GIO_P41 AB0_WAIT* NTS_DATA5
+ AB0_CSB0 GIO_P42 AB0_CSB0* NTS_DATA6
+ AB0_CSB1 GIO_P43 AB0_CSB1* NTS_DATA7
+ AB0_CSB2 GIO_P44* AB0_CSB2 NTS_VS
+ AB0_CSB3 GIO_P45 AB0_CSB3* NTS_HS
+ AB0_BEN0 GIO_P46 AB0_BEN0*
+ AB0_BEN1 GIO_P47 AB0_BEN1*
+
+ pin name function 0(00) function1(01) function2(10) function3(11)
+ SP0_CS1 GIO_P48 SP0_CS1*
+ SP0_CS2 GIO_P49 SP0_CS2*
+ LCD_PXCLK GIO_P50 LCD_PXCLK*
+ LCD_R0 GIO_P51 LCD_R0*
+ LCD_R1 GIO_P52 LCD_R1*
+ LCD_R2 GIO_P53 LCD_R2*
+ LCD_R3 GIO_P54 LCD_R3*
+ LCD_R4 GIO_P55 LCD_R4*
+ LCD_R5 GIO_P56 LCD_R5*
+ LCD_G0 GIO_P57 LCD_G0*
+ LCD_G1 GIO_P58 LCD_G1*
+ LCD_G2 GIO_P59 LCD_G2*
+ LCD_G3 GIO_P60 LCD_G3*
+ LCD_G4 GIO_P61 LCD_G4*
+ LCD_G5 GIO_P62 LCD_G5*
+ LCD_B0 GIO_P63 LCD_B0*
+
+ pin name function 0(00) function1(01) function2(10) function3(11)
+ LCD_B1 GIO_P64 LCD_B1*
+ LCD_B2 GIO_P65 LCD_B2*
+ LCD_B3 GIO_P66 LCD_B3*
+ LCD_B4 GIO_P67 LCD_B4*
+ LCD_B5 GIO_P68 LCD_B5*
+ LCD_HSYNC GIO_P69 LCD_HSYNC*
+ LCD_VSYNC GIO_P70 LCD_VSYNC*
+ LCD_ENABLE GIO_P71 LCD_ENABLE*
+ NTS_CLK GIO_P72* NTS_CLK PM1_CLK
+ NTS_VS GIO_P73* NTS_VS SP1_CLK
+ NTS_HS GIO_P74* NTS_HS SP1_SI
+ NTS_DATA0 GIO_P75 NTS_DATA0 SP1_SO CAM_YUV0*
+ NTS_DATA1 GIO_P76 NTS_DATA1 SP1_CS0 CAM_YUV1*
+ NTS_DATA2 GIO_P77 NTS_DATA2 SP1_CS1 CAM_YUV2*
+ NTS_DATA3 GIO_P78 NTS_DATA3 SP1_CS2 CAM_YUV3*
+ NTS_DATA4 GIO_P79 NTS_DATA4 SP1_CS3 CAM_YUV4*
+
+ pin name function 0(00) function1(01) function2(10) function3(11)
+ NTS_DATA5 GIO_P80* NTS_DATA5 SP1_CS4 PM1_SEN
+ NTS_DATA6 GIO_P81* NTS_DATA6 SP1_CS5 PM1_SI
+ NTS_DATA7 GIO_P82* NTS_DATA7 PM1_SO
+ IIC_SCL GIO_P83 IIC_SCL*
+ IIC_SDA GIO_P84 IIC_SDA*
+ URT0_CTSB GIO_P85 URT0_CTSB URT1_SRIN*
+ URT0_RTSB GIO_P86 URT0_RTSB URT1_SOUT*
+ PM0_SI GIO_P87 PM0_SI*
+ SD0_DATA1 GIO_P88 SD0_DATA1*
+ SD0_DATA2 GIO_P89 SD0_DATA2*
+ SD0_DATA3 GIO_P90 SD0_DATA3*
+ SD0_CKI GIO_P91 SD0_CKI*
+ SD1_CKI GIO_P92 SD1_CKI CAM_CLKI*
+ SD2_CKI GIO_P93 SD2_CKI* NAND_OE
+ PWM0 GIO_P94* PWM0
+ PWM1 GIO_P95* PWM1
+
+ pin name function 0(00) function1(01) function2(10) function3(11)
+ USB_CLK GIO_P96 USB_CLK*
+ USB_DATA0 GIO_P97 USB_DATA0*
+ USB_DATA1 GIO_P98 USB_DATA1*
+ USB_DATA2 GIO_P99 USB_DATA2*
+ USB_DATA3 GIO_P100 USB_DATA3*
+ USB_DATA4 GIO_P101 USB_DATA4*
+ USB_DATA5 GIO_P102 USB_DATA5*
+ USB_DATA6 GIO_P103 USB_DATA6*
+ USB_DATA7 GIO_P104 USB_DATA7*
+ USB_DIR GIO_P105 USB_DIR*
+ USB_STP GIO_P106 USB_STP*
+ USB_NXT GIO_P107 USB_NXT*
+ URT2_SRIN GIO_P108 URT2_SRIN*
+ URT2_SOUT GIO_P109 URT2_SOUT*
+ URT2_CTSB GIO_P110 URT2_CTSB*
+ URT2_RTSB GIO_P111 URT2_RTSB*
+
+ pin name function 0(00) function1(01) function2(10) function3(11)
+ SD2_CKO GIO_P112 SD2_CKO* NAND_D2
+ SD2_CMD GIO_P113 SD2_CMD* NAND_D3
+ SD2_DATA0 GIO_P114 SD2_DATA0* NAND_D4
+ SD2_DATA1 GIO_P115 SD2_DATA1* NAND_D5
+ SD2_DATA2 GIO_P116 SD2_DATA2* NAND_D6
+ SD2_DATA3 GIO_P117 SD2_DATA3* NAND_D7
+*/
+EXPORT const UW GPIOConfig[] __attribute__((section(".startup"))) = {
+ CHG_PINSEL_G(0),
+ 0x55400C00, /* AB0_CLK,AB0_AD3-0,CAM_SCLK */
+ CHG_PINSEL_G(16),
+ 0x55555555, /* AB0_AD15-4,AB0_A20-17 */
+ CHG_PINSEL_G(32),
+ 0x54555055, /* AB0_BEN1-0,AB0_CSB3,AB0_CSB1-0, */
+ /* AB0_WAIT,AB0_WRB,AB0_RDB,AB0_ADV, */
+ /* AB0_A24-21 */
+
+ CHG_CTRL_AB0_BOOT, /* AB0(AsyncBus0) pin: */
+ 0x00000001, /* configured by PINSEL */
+
+ CHG_PINSEL_G(48),
+ 0x55555555, /* LCD,SP0_CS2-1 */
+ CHG_PINSEL_G(64),
+ 0xffc05555, /* CAM_YUV4-0,LCD */
+ CHG_PINSEL_G(80),
+ 0x06556940, /* SD2_CKI,CAM_CLKI,SD0_CKI,SD0_DATA3-1, */
+ /* PM0,URT1,IIC */
+ CHG_PINSEL_G(96),
+ 0x55555555, /* URT2,USB */
+ CHG_PINSEL_G(112),
+ 0x00000555, /* SD2 */
+ CHG_PINSEL_SP0,
+ 0x00000000,
+ CHG_PINSEL_DTV,
+ 0x00000001,
+ CHG_PINSEL_SD0,
+ 0x00000000,
+ CHG_PINSEL_SD1,
+ 0x00000002,
+ CHG_PINSEL_IIC2,
+ 0x00000000,
+ CHG_PULL_G(0),
+ 0x55055005, /* P7,P6,P4,P3,P0: IN, pull-up/down dis */
+ CHG_PULL_G(8),
+ 0x00000005, /* P8: IN, pull-up/down dis */
+ CHG_PULL_G(16),
+ 0x00000000, /* (default) */
+ CHG_PULL_G(24),
+ 0x00000000, /* (default) */
+ CHG_PULL_G(32),
+ 0x00550000, /* P37,36: IN, pull-up/down dis */
+ CHG_PULL_G(40),
+ 0x00050000, /* P44: IN, pull-up/down dis */
+ CHG_PULL_G(48),
+ 0x11111111, /* (default) */
+ CHG_PULL_G(56),
+ 0x11111111, /* (default) */
+ CHG_PULL_G(64),
+ 0x11111111, /* (default) */
+ CHG_PULL_G(72),
+ 0x00000005, /* P72: IN, pull-up/down dis */
+ CHG_PULL_G(80),
+ 0x00400050, /* P81: IN, pull-up/down dis */
+ /* URT1_SRIN: IN, pull-down */
+ CHG_PULL_G(88),
+ 0x55000444, /* P95,94: IN, pull-up/down dis */
+ /* SD0_DATA3-1: IN, pull-down */
+ CHG_PULL_G(96),
+ 0x44444444, /* USB signals: IN, pull-down */
+ CHG_PULL_G(104),
+ 0x04044444, /* USB signals: IN, pull-down */
+ /* URT2_CTSB,URT2_SRIN: IN, pull-down */
+ CHG_PULL_G(112),
+ 0x00000000, /* (default) */
+ CHG_PULL_G(120),
+ 0x00000000, /* (default) */
+
+ CHG_PULL(0),
+ 0x50000004, /* URT0_SRIN: IN, pull-up/down dis */
+ /* DEBUG_EN: IN, pull-down */
+ CHG_PULL(1),
+ 0x15110600, /* SP0_SO: OUT, pull-up/down dis */
+ /* SP0_SI: IN, pull-up/down dis */
+ /* SP0_CS: OUT, pull-up/down dis */
+ /* SP0_CK: OUT, pull-up/down dis */
+ /* JT0C: IN, pull-up */
+ /* JT0B: OUT, pull-down */
+ /* JT0A: OUT, pull-down */
+ CHG_PULL(2),
+ 0x60000661, /* PM0_SEN: IN, pull-up */
+ /* SD0_DAT: IN, pull-up */
+ /* SD1_CMD: IN, pull-up */
+ /* SD0_CLK: OUT, pull-up/down dis */
+ CHG_PULL(3),
+ 0x00000000, /* (default) */
+
+ GIO_E0(GIO_L),
+ 0x000001d9, /* P8,P7,P6,P4,P3,P0: IN */
+ GIO_E1(GIO_L),
+ 0x00000604, /* P10,P9,P2: OUT */
+ GIO_E0(GIO_H),
+ 0x00001030, /* P44,P37,P36: IN */
+ GIO_E1(GIO_H),
+ 0x00000000, /* (default) */
+ GIO_E0(GIO_HH),
+ 0xc0020100, /* P95,P94,P81,P72:IN */
+ GIO_E1(GIO_HH),
+ 0x00040200, /* P82,P73: OUT */
+ GIO_OL(GIO_L),
+ 0x06040000, /* P10,P9,P2=0 */
+ GIO_OL(GIO_HH),
+ 0x02000000, /* P73=0 */
+ GIO_OH(GIO_HH),
+ 0x00040000, /* P82=0 */
+
+ 0x00000000, /* (terminate) */
+ 0x00000000,
+};
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-em1d/cpuctrl.c b/tkernel_source/monitor/hwdepend/arm/mach-em1d/cpuctrl.c
new file mode 100644
index 0000000..2580cef
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-em1d/cpuctrl.c
@@ -0,0 +1,82 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * cpuctrl.c
+ *
+ * ARM CPU control
+ */
+
+#include "sysdepend.h"
+
+/*
+ * Location of the 1st level page table
+ */
+EXPORT UW* const TopPageTable = (UW*)PAGETBL_BASE;
+
+/* ------------------------------------------------------------------------ */
+/*
+ * cache control
+ * acts on the whole address space.
+ */
+
+/*
+ * turn on cache
+ */
+EXPORT void EnableCache( void )
+{
+ setCacheMMU(ENB_CACHEMMU);
+}
+
+/*
+ * turn off cache
+ */
+EXPORT void DisableCache( void )
+{
+ /* MMU can NOT be turned off with this CPU. */
+ setCacheMMU(DIS_CACHEONLY);
+}
+
+/* ------------------------------------------------------------------------ */
+/*
+ * processing on monitor entry
+ */
+
+/*
+ * entry
+ * info, return value is meaningless
+ */
+EXPORT W enterMonitor( UW info )
+{
+ /* cache and MMU is flushed */
+ setCacheMMU(ENB_CACHEMMU);
+
+ return 0;
+}
+
+/*
+ * exit
+ * only in the case of system control processor (CP15)
+ * info is the cache and MMU mode
+ * return value is meaningless
+ */
+EXPORT W leaveMonitor( UW info )
+{
+ /* restore cache && MMU to the original state. */
+ setCacheMMU(info);
+
+ return 0;
+}
+
+/* ------------------------------------------------------------------------ */
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-em1d/diskio.c b/tkernel_source/monitor/hwdepend/arm/mach-em1d/diskio.c
new file mode 100644
index 0000000..aa730c4
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-em1d/diskio.c
@@ -0,0 +1,250 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * diskio.c
+ *
+ * Disk I/O
+ */
+
+#include "hwdepend.h"
+#include <device/disk.h>
+
+/*
+ * misaligned data is read as a little-endian data
+ */
+#define GMW(vp) ( (UW)((UB*)vp)[0] \
+ | (UW)((UB*)vp)[1] << 8 \
+ | (UW)((UB*)vp)[2] << 16 \
+ | (UW)((UB*)vp)[3] << 24 )
+#define GMH(vp) ( (UH)((UB*)vp)[0] \
+ | (UH)((UB*)vp)[1] << 8 )
+
+/*
+ * control block for a disk drive
+ * When their number is smaller than the number of disks,
+ * already used block is re-used in place of missing block after it is cleared
+ */
+#define N_DISKCB 3
+LOCAL struct dcblist {
+ const CFGDISK *cfg; /* target device */
+ DISKCB dcb;
+} dcbList[N_DISKCB];
+
+LOCAL W last_dcb = 0; /* the last allocated number from dcbList */
+
+/*
+ * allocating a disk control block
+ */
+LOCAL DISKCB* getDISKCB( const CFGDISK *cfg )
+{
+ W i, n;
+ DISKCB *dcb;
+
+ /* searching for disk drive control block */
+ n = last_dcb;
+ do {
+ i = n;
+ if ( dcbList[i].cfg == cfg ) break;
+ if ( ++n >= N_DISKCB ) n = 0;
+ } while ( n != last_dcb );
+ dcb = &dcbList[i].dcb;
+ last_dcb = i;
+ if ( dcbList[i].cfg != cfg ) {
+ /* re-use after clear */
+ memset(dcb, 0, sizeof(DISKCB));
+ dcbList[i].cfg = cfg;
+ }
+
+ return dcb;
+}
+
+/*
+ * search for a device
+ * return the configuration information of device (indicated by devnm) to cfg_p.
+ * return value is a partition number or error.
+ */
+LOCAL W searchDevice( const UB *devnm, const CFGDISK **cfg_p )
+{
+ UB name[L_DEVNM + 1];
+ W i, pno, c;
+
+ /* checking device name */
+ strncpy(name, devnm, L_DEVNM + 1);
+ if ( name[L_DEVNM] != '\0' ) return E_PAR;
+ i = strlen(name);
+ if ( i <= 0 ) return E_PAR;
+
+ /* check for logical device (partition: 0-3) */
+ pno = 0;
+ c = name[i - 1];
+ if ( c >= '0' && c <='3' ) {
+ if ( --i <= 0 ) return E_PAR;
+ name[i] = '\0'; /* partition number is removed */
+ pno = c - '0' + 1; /* partition number (1 - ) */
+ }
+
+ /* search for a device */
+ for ( i = 0; i < N_ConfigDisk; i++ ) {
+ if ( strncmp(name, ConfigDisk[i].name, L_DEVNM) == 0 ) break;
+ }
+ if ( i >= N_ConfigDisk ) return E_NOEXS;
+
+ *cfg_p = &ConfigDisk[i];
+ return pno;
+}
+
+/*
+ * obtain partition information
+ */
+LOCAL ER readPart( DISKCB *dcb )
+{
+ DiskBlock0 buf;
+ W i, pno;
+ ER err;
+
+ dcb->boot = 0;
+
+ /* if an unexpected disk block size is seen, raise an error */
+ if ( dcb->blksz != sizeof(buf) ) return E_NOSPT;
+
+ /* read master boot record */
+ err = (*dcb->rwdisk)(dcb, 0, 1, &buf, FALSE);
+ if ( err < E_OK ) return err;
+
+ /* check the signature in the boot block */
+ if ( GMH(&buf.signature) != 0xaa55 ) return E_OK; /* no partition */
+
+ /* obtain partition information */
+ for ( i = 0; i < MAX_PARTITION; i++ ) {
+ pno = i + 1;
+ dcb->part[pno].sblk = GMW(buf.part[i].StartBlock);
+ dcb->part[pno].nblk = GMW(buf.part[i].BlockCnt);
+
+ if ( buf.part[i].BootInd == 0x80
+ && dcb->part[pno].nblk > 0
+ && dcb->boot == 0 ) dcb->boot = pno;
+ }
+
+ return E_OK;
+}
+
+/*
+ * open disk (obtain disk drive control block)
+ * open a device indicated by `devnm', and return the disk information in `dcb'.
+ * devnm can specify a device name with partition number.
+ * return the partition number specified by devnm.
+ * return value 0 : entire disks
+ * 1 - : partition number
+ * < 0 : error
+ */
+EXPORT W openDisk( const UB *devnm, DISKCB **dcb_p )
+{
+ const CFGDISK *cfg;
+ DISKCB *dcb;
+ W pno;
+ ER err;
+
+ /* search for a device */
+ pno = searchDevice(devnm, &cfg);
+ if ( pno < E_OK ) return pno;
+
+ /* allocating a disk control block */
+ dcb = getDISKCB(cfg);
+
+ /* initialize disk */
+ err = (*cfg->initdisk)(dcb, cfg);
+ if ( err < E_OK ) return err;
+ if ( dcb->blksz == 0 ) return E_NOMDA;
+
+ if ( dcb->boot == 0xff ) {
+ /* read the partition information */
+ err = readPart(dcb);
+ if ( err < E_OK ) return err;
+ }
+
+ *dcb_p = dcb;
+ return pno;
+}
+
+/*
+ * disk access
+ * devnm device name (possibly with the partition number)
+ * blk start block number
+ * if device name has a partition number, then the block number in that partition
+ * if there is no partition number in the disk anme, the block number in the entire disk
+ * nblk number of blocks
+ * buf buffer (* )
+ * wrt FALSE : read
+ * TRUE : write
+ * return value error code
+ * argument marked with (* ) may be an address specified from external sources.
+ */
+EXPORT ER rwDisk( const UB *devnm, W blk, W nblk, void *buf, BOOL wrt )
+{
+ DISKCB *dcb;
+ W pno, nb;
+ ER err;
+
+ /* initialize disk */
+ pno = openDisk(devnm, &dcb);
+ if ( pno < E_OK ) return pno;
+
+ nb = dcb->part[pno].nblk;
+
+ /* range check of the block number */
+ if ( blk < 0 || blk >= nb
+ || nblk <= 0 || nblk > nb - blk ) return E_PAR;
+
+ /* convert the relative block number in a partiton to a block number in the entire disk */
+ blk += dcb->part[pno].sblk;
+
+ /* read from, or write to disk */
+ err = (*dcb->rwdisk)(dcb, blk, nblk, buf, wrt);
+ if ( err < E_OK ) return err;
+
+ return E_OK;
+}
+
+/*
+ * obtain disk information
+ * devnm device name (possibly with the partition number)
+ * blksz return block size (* )
+ * tblks return the number of all blocks (* )
+ * return value error code
+ * if there is a partition number to the device name, return the specific information to that partition.
+ * argument marked with (* ) may be an address specified from external sources.
+ */
+EXPORT ER infoDisk( const UB *devnm, W *blksz, W *tblks )
+{
+ DISKCB *dcb;
+ W pno, buf, n;
+
+ /* initialize disk */
+ pno = openDisk(devnm, &dcb);
+ if ( pno < E_OK ) return pno;
+
+ /* obtain disk information
+ * since there are addresses specified from external source, use writeMem()
+ */
+ buf = dcb->part[pno].nblk;
+ n = writeMem((UW)tblks, &buf, sizeof(W), sizeof(W));
+ if ( n < sizeof(W) ) return E_MACV;
+
+ buf = dcb->blksz;
+ n = writeMem((UW)blksz, &buf, sizeof(W), sizeof(W));
+ if ( n < sizeof(W) ) return E_MACV;
+
+ return E_OK;
+}
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-em1d/eitproc.c b/tkernel_source/monitor/hwdepend/arm/mach-em1d/eitproc.c
new file mode 100644
index 0000000..b109c95
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-em1d/eitproc.c
@@ -0,0 +1,132 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * eitproc.c
+ *
+ * EIT processing
+ */
+
+#include "sysdepend.h"
+#include <tk/sysdef.h>
+
+/*
+ * vector information
+ */
+typedef struct vecinfo VECINFO;
+struct vecinfo {
+ UW vec; /* initial vector numer */
+ B *msg; /* message */
+
+ /* processing function
+ * return value 1 : adjust PC by decrementing it by one instruction worth
+ * 0 : PC needs no adjustment
+ */
+ W (*func)( const VECINFO*, UW vec, UW pc, UW cpsr );
+};
+
+/* display message */
+LOCAL W vf_msg( const VECINFO *vi, UW vec, UW pc, UW cpsr )
+{
+ B *msg = vi->msg;
+ B opt;
+
+ if ( msg == NULL ) return 0;
+
+ /* if the first byte of the message is not a letter, treat it as option.
+ * opt = 0 - 037 (the code prior to ' ' )
+ * \020 PC is adjusted to the previous instruction's address
+ */
+ opt = 0;
+ if ( *msg < ' ' ) opt = *msg++;
+
+ DSP_F5(S,"Exception ", D,vec, S," (", S,msg, CH,')');
+
+ return ( opt & 020 )? 1: 0;
+}
+
+/* undefined instruction */
+LOCAL W vf_undef( const VECINFO *vi, UW vec, UW pc, UW cpsr )
+{
+ if (cpsr & PSR_T) {
+ DSP_F3(S,vi->msg, CH,' ', 04X,*((UH*)(pc - 2)));
+ } else {
+ DSP_F3(S,vi->msg, CH,' ', 08X,*((UW*)(pc - 4)));
+ }
+ return 1;
+}
+
+/* data abort */
+LOCAL W vf_dabort( const VECINFO *vi, UW vec, UW pc, UW cpsr )
+{
+ DSP_F1(S,vi->msg);
+ DSP_F4(S," ADDR: ", 08X,getCP15(6, 0), S," STAT: ", 08X,getCP15(5, 0));
+ return 0;
+}
+
+/*
+ * vector information table
+ * this has to be filled in the ascending order of the vector number
+ */
+LOCAL const VECINFO VecInfoTable[] = {
+ { 0, "\020" "Undefined SWI", vf_msg },
+ { EIT_UNDEF, "Undefined Instruction", vf_undef },
+ { EIT_IABORT, "Prefetch Abort", vf_msg },
+ { EIT_DABORT, "Data Abort", vf_dabort },
+ { EIT_DABORT+1, "\020" "Undefined SWI", vf_msg },
+
+ { EIT_FIQ, "Undefined FIQ", vf_msg },
+ { EIT_IRQ(0), "Undefined IRQ", vf_msg },
+ { EIT_GPIO(0), "Undefined GPIO-INT", vf_msg },
+ { EIT_GPIO(127)+1,"\020" "Undefined SWI", vf_msg },
+
+ { N_INTVEC, NULL, vf_msg } /* terminating mark (the last vector number + 1) */
+};
+#define N_VECINFO ( sizeof(VecInfoTable) / sizeof(VECINFO) )
+
+/*
+ * EIT processing
+ * * return value 0 : monitor should keep on running
+ * 1 : return from the interrupt handler
+ */
+EXPORT W procEIT( UW vec )
+{
+ const VECINFO *vp;
+ UW pc, cpsr;
+ W i;
+
+ pc = getCurPCX();
+ cpsr = getCurCPSR();
+
+ /* machine-dependent interrupt processing */
+ i = procHwInt(vec);
+ if ( i == 2 ) return 1; /* exit from the interrupt handler immediately */
+
+ if ( i == 0 ) {
+ /* other EIT processing */
+ for ( i = 1; i < N_VECINFO; ++i ) {
+ if ( vec < VecInfoTable[i].vec ) break;
+ }
+ vp = &VecInfoTable[i-1];
+ i = (*vp->func)(vp, vec, pc, cpsr);
+ if ( i > 0 ) {
+ /* PC is adjusted to the previous instruction's address */
+ pc -= ( (cpsr & PSR_T) != 0 )? 2: 4;
+ }
+ }
+
+ DSP_F5(S,"\nPC: ", 08X,pc, S," CPSR: ", 08X,cpsr, CH,'\n');
+
+ return 0;
+}
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-em1d/hwdepend.h b/tkernel_source/monitor/hwdepend/arm/mach-em1d/hwdepend.h
new file mode 100644
index 0000000..0e98fe0
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-em1d/hwdepend.h
@@ -0,0 +1,63 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * hwdepend.h
+ *
+ * T-Monitor hardware-dependent processing
+ */
+
+#ifndef __MONITOR_CMDSVC_HWDEPEND_H__
+#define __MONITOR_CMDSVC_HWDEPEND_H__
+
+#include <tmonitor.h>
+#include "sysdepend.h"
+
+IMPORT UW DipSw; /* dip switch status */
+
+/*
+ * system configuration information
+ */
+IMPORT MEMSEG MemSeg[]; /* memory area definition */
+IMPORT W N_MemSeg; /* number of memory areas */
+
+IMPORT const CFGSIO ConfigSIO[]; /* serial port configuration definition */
+IMPORT const W N_ConfigSIO; /* serial port number */
+
+IMPORT const CFGDISK ConfigDisk[]; /* disk drive configuration definition */
+IMPORT const W N_ConfigDisk; /* nuber of disk drives */
+
+/*
+ * initial processing after reset
+ */
+IMPORT void procReset( void );
+
+/*
+ * initialize hardware (peripherals)
+ */
+IMPORT void initHardware( void );
+
+/*
+ * setting up the initial count for micro-wait()
+ */
+IMPORT void setupWaitUsec( void );
+
+/*
+ * obtain the console port number
+ * console port number (0 - )
+ * if there is no console port, return -1.
+ */
+IMPORT W getConPort( void );
+
+#endif /* __MONITOR_CMDSVC_HWDEPEND_H__ */
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-em1d/hwinfo.c b/tkernel_source/monitor/hwdepend/arm/mach-em1d/hwinfo.c
new file mode 100644
index 0000000..3ef3db8
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-em1d/hwinfo.c
@@ -0,0 +1,147 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * hwinfo.c
+ *
+ * hardware configuration information
+ */
+
+#include "hwdepend.h"
+
+/* ------------------------------------------------------------------------ */
+/*
+ * memory region definition
+ */
+
+/*
+ * obtaining memory region information
+ * no = 1 - (and up)
+ * 'no'-th information in the region specified by the attr is returned.
+ * if attr = 0, no matter what the attribute is, 'no'-th information is returned unconditionally.
+ * If there was no such information, return NULL.
+ */
+EXPORT MEMSEG* MemArea( UW attr, W no )
+{
+ MEMSEG *mp;
+ W i;
+
+ if ( attr == 0 ) {
+ i = no - 1;
+ return ( i >= 0 && i < N_MemSeg )? &MemSeg[i]: NULL;
+ }
+
+ for ( i = 0; i < N_MemSeg; ++i ) {
+ mp = &MemSeg[i];
+ if ( (mp->attr & attr) != 0 ) {
+ if ( --no <= 0 ) return mp;
+ }
+ }
+
+ return NULL;
+}
+
+/*
+ * obtaining memory region information (specify address)
+ * within the region specified by `attr', return the information that surrounds the position specified by `addr'.
+ *
+ * if no such information is found, return NULL.
+ */
+EXPORT MEMSEG* AddrMatchMemArea( UW addr, UW attr )
+{
+ MEMSEG *mp;
+ W i;
+
+ for ( i = 0; i < N_MemSeg; ++i ) {
+ mp = &MemSeg[i];
+ if ( (mp->attr & attr) == 0 ) continue;
+
+ if ( addr >= mp->top && addr <= mp->end-1 ) return mp;
+ }
+
+ return NULL;
+}
+
+/*
+ * Decide whether two memory regions are included in another.
+ * if the region, from `top' to `end', is completely included in the region specified by `attr',
+ * TRUE
+ * the location of end is NOT included in the region (end - top) is the region size
+ * end = 0x00000000, by the way, means 0x100000000.
+ */
+EXPORT BOOL inMemArea( UW top, UW end, UW attr )
+{
+ const MEMSEG *mp;
+ W i;
+
+ for ( i = 0; i < N_MemSeg; ++i ) {
+ mp = &MemSeg[i];
+ if ( (mp->attr & attr) == 0 ) continue;
+
+ if ( top >= mp->top && end-1 <= mp->end-1 ) return TRUE;
+ }
+ return FALSE;
+}
+
+/*
+ * Decide whether two memory regions overlap with each other
+ * if the area, from top to end, is included even partially in the region specified by `attr' - 'end',
+ * it is TRUE
+ * the location of end is NOT included in the region (end - top) is the region size
+ * end = 0x00000000, by the way, means 0x100000000.
+ */
+EXPORT BOOL isOverlapMemArea( UW top, UW end, UW attr )
+{
+ const MEMSEG *mp;
+ W i;
+
+ for ( i = 0; i < N_MemSeg; ++i ) {
+ mp = &MemSeg[i];
+ if ( (mp->attr & attr) == 0 ) continue;
+
+ if ( top <= mp->end-1 && end-1 >= mp->top ) return TRUE;
+ }
+ return FALSE;
+}
+
+/* ------------------------------------------------------------------------ */
+/*
+ * boot device following the standard boot order
+ * return the device name that is the 'no'-th device in the standard boot order.
+ *
+ * if no such device name exists (when 'no' is given as a value larger or equal to the last number), it is NULL.
+ */
+EXPORT const UB* bootDevice( W no )
+{
+ if ( no < 0 || no >= N_ConfigDisk ) return NULL;
+
+ return ConfigDisk[no].name;
+}
+
+/*
+ * list of disk drives
+ * returns the disk drive device name, indicated by 'no' ( 0 - : a consecutive number )
+ * if no such device name exists (when 'no' is given as a value larger or equal to the last number), it is NULL.
+ * if attr is not NULL, disk driver attribute returns in `attr' )
+ */
+EXPORT const UB* diskList( W no, UW *attr )
+{
+ if ( no < 0 || no >= N_ConfigDisk ) return NULL;
+
+ if ( attr != NULL ) *attr = ConfigDisk[no].attr;
+
+ return ConfigDisk[no].name;
+}
+
+/* ------------------------------------------------------------------------ */
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-em1d/include/mach/cpudepend.h b/tkernel_source/monitor/hwdepend/arm/mach-em1d/include/mach/cpudepend.h
new file mode 100644
index 0000000..4cbb714
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-em1d/include/mach/cpudepend.h
@@ -0,0 +1,96 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * cpudepend.h
+ *
+ * ARM-related definitions
+ */
+
+#ifndef __MONITOR_ARM_CPUDEPEND_H__
+#define __MONITOR_ARM_CPUDEPEND_H__
+
+#include <machine.h>
+
+/*
+ * monitor stack area
+ * stack area is from &__stack_top to &__stack_bottom
+ * initial stack pointer = &__stack_bottom
+ */
+IMPORT UB __stack_top, __stack_bottom;
+
+/*
+ * first level page table
+ */
+IMPORT UW* const TopPageTable; /* location of page table */
+#define N_PageTableEntry 0x1000 /* number of entries */
+
+/*
+ * address conversion to non-cached and cached area
+ * in the case of ARM, all address have the same cache mode, and hence
+ * return as it is.
+ */
+#define NOCACHE_ADDR(p) (p)
+#define CACHE_ADDR(p) (p)
+
+/*
+ * I/O port access functions
+ */
+Inline void out_w( INT port, UW data )
+{
+ *(_UW*)port = data;
+}
+Inline void out_h( INT port, UH data )
+{
+ *(_UH*)port = data;
+}
+Inline void out_b( INT port, UB data )
+{
+ *(_UB*)port = data;
+}
+
+Inline UW in_w( INT port )
+{
+ return *(_UW*)port;
+}
+Inline UH in_h( INT port )
+{
+ return *(_UH*)port;
+}
+Inline UB in_b( INT port )
+{
+ return *(_UB*)port;
+}
+
+/*
+ * value of control register (r1) of system control coprocessor cp15
+ */
+#if CPU_ARM1176
+#define MASK_CACHEMMU (0xFFFFCC78) /* V,I,R,S,C,A,M (B = 0) */
+#define VALID_CACHEMMU (0x3307) /* B = 0 */
+#define DIS_CACHEMMU (0x0000) /* I=0,R=0,S=0,C=0,A=0,M=0 */
+#define DIS_CACHEONLY (0x0001) /* I=0,R=0,S=0,C=0,A=0,M=1 */
+#define ENB_CACHEMMU (0x1007) /* I=1,R=0,S=0,C=1,A=1,M=1 */
+#define ENB_MMUONLY (0x0003) /* I=0,R=0,S=0,C=0,A=1,M=1 */
+#endif
+
+/*
+ * references registers under monitor control
+ * references the value of registers at the time of monitor entry.
+ */
+IMPORT UW getCP15( W reg, W opcd ); /* CP15 register CRn: reg, Op2: opcd */
+IMPORT UW getCurPCX( void ); /* PC register (raw value) */
+IMPORT UW getCurCPSR( void ); /* CPSR register */
+
+#endif /* __MONITOR_ARM_CPUDEPEND_H__ */
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-em1d/include/mach/em1d512.h b/tkernel_source/monitor/hwdepend/arm/mach-em1d/include/mach/em1d512.h
new file mode 100644
index 0000000..b1eb46f
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-em1d/include/mach/em1d512.h
@@ -0,0 +1,464 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * em1d.h
+ *
+ * EMMA Mobile(TM)1-D register definitions (excerpt)
+ *
+ * * this is included from assembler program source files
+ */
+
+#ifndef __MONITOR_ARM_EM1D_H__
+#define __MONITOR_ARM_EM1D_H__
+
+#include <tk/sysdef.h>
+
+#define AB0Base 0x2fff0000
+#define AB0_FLASHCOMSET (AB0Base + 0x0000)
+#define AB0_FLASHCOMLATCH (AB0Base + 0x0004)
+#define AB0_FLASHCOMADD0 (AB0Base + 0x0010)
+#define AB0_FLASHCOMDATA0 (AB0Base + 0x0014)
+#define AB0_FLASHCOMADD1 (AB0Base + 0x0018)
+#define AB0_FLASHCOMDATA1 (AB0Base + 0x001c)
+#define AB0_FLASHCLKCTRL (AB0Base + 0x0080)
+#define AB0_FLA_RCLK_DLY (AB0Base + 0x0084)
+#define AB0_WAIT_STATUS (AB0Base + 0x0090)
+#define AB0_CSnBASEADD(n) (AB0Base + 0x0100 + 0x0010 * (n))
+#define AB0_CSnBITCOMP(n) (AB0Base + 0x0104 + 0x0010 * (n))
+#define AB0_CSnWAITCTRL(n) (AB0Base + 0x0200 + 0x0020 * (n))
+#define AB0_CSnWAITCTRL_W(n) (AB0Base + 0x0204 + 0x0020 * (n))
+#define AB0_CSnREADCTRL(n) (AB0Base + 0x0208 + 0x0020 * (n))
+#define AB0_CSnWAIT_MASK(n) (AB0Base + 0x020c + 0x0020 * (n))
+#define AB0_CSnCONTROL(n) (AB0Base + 0x0210 + 0x0020 * (n))
+#define AB0_CSnFLASHRCR(n) (AB0Base + 0x0214 + 0x0020 * (n))
+#define AB0_CSnFLASHWCR(n) (AB0Base + 0x0218 + 0x0020 * (n))
+#define AB0_CSnWAITCTRL2(n) (AB0Base + 0x0300 + 0x0020 * (n))
+#define AB0_CSnWAITCTRL_W2(n) (AB0Base + 0x0304 + 0x0020 * (n))
+#define AB0_CSnREADCTRL2(n) (AB0Base + 0x0308 + 0x0020 * (n))
+#define AB0_CSnWAIT_MASK2(n) (AB0Base + 0x030c + 0x0020 * (n))
+#define AB0_CSnCONTROL2(n) (AB0Base + 0x0310 + 0x0020 * (n))
+#define AB0_CSnFLASHRCR2(n) (AB0Base + 0x0314 + 0x0020 * (n))
+#define AB0_CSnFLASHWCR2(n) (AB0Base + 0x0318 + 0x0020 * (n))
+
+#define LCDBase 0x40270000
+#define LCD_CONTROL (LCDBase + 0x0000)
+#define LCD_QOS (LCDBase + 0x0004)
+#define LCD_DATAREQ (LCDBase + 0x0008)
+#define LCD_LCDOUT (LCDBase + 0x0010)
+#define LCD_BUSSEL (LCDBase + 0x0014)
+#define LCD_STATUS (LCDBase + 0x0018)
+#define LCD_BACKCOLOR (LCDBase + 0x001c)
+#define LCD_AREAADR (LCDBase + 0x0020)
+#define LCD_HOFFSET (LCDBase + 0x0024)
+#define LCD_IFORMAT (LCDBase + 0x0028)
+#define LCD_RESIZE (LCDBase + 0x002c)
+#define LCD_HTOTAL (LCDBase + 0x0030)
+#define LCD_HAREA (LCDBase + 0x0034)
+#define LCD_HEDGE1 (LCDBase + 0x0038)
+#define LCD_HEDGE2 (LCDBase + 0x003c)
+#define LCD_VTOTAL (LCDBase + 0x0040)
+#define LCD_VAREA (LCDBase + 0x0044)
+#define LCD_VEDGE1 (LCDBase + 0x0048)
+#define LCD_VEDGE2 (LCDBase + 0x004c)
+#define LCD_INTSTATUS (LCDBase + 0x0060)
+#define LCD_INTRAWSTATUS (LCDBase + 0x0064)
+#define LCD_INTENSET (LCDBase + 0x0068)
+#define LCD_INTENCLR (LCDBase + 0x006c)
+#define LCD_INTFFCLR (LCDBase + 0x0070)
+#define LCD_FRAMECNT (LCDBase + 0x0074)
+
+#define UARTnBase(n) (0x50000000 + 0x00010000 * (n))
+#define UART0 0x00
+#define UART1 0x01
+#define UART2 0x02
+/* omitted */
+
+#define SDIxBase(x) (0x50050000 + 0x00010000 * (x))
+#define SDIA 0x00
+#define SDIB 0x01
+#define SDIC 0x04
+#define SDIx_CMD(x) (SDIxBase(x) + 0x0000)
+#define SDIx_PORT(x) (SDIxBase(x) + 0x0004)
+#define SDIx_ARG0(x) (SDIxBase(x) + 0x0008)
+#define SDIx_ARG1(x) (SDIxBase(x) + 0x000c)
+#define SDIx_STOP(x) (SDIxBase(x) + 0x0010)
+#define SDIx_SECCNT(x) (SDIxBase(x) + 0x0014)
+#define SDIx_RSP0(x) (SDIxBase(x) + 0x0018)
+#define SDIx_RSP1(x) (SDIxBase(x) + 0x001c)
+#define SDIx_RSP2(x) (SDIxBase(x) + 0x0020)
+#define SDIx_RSP3(x) (SDIxBase(x) + 0x0024)
+#define SDIx_RSP4(x) (SDIxBase(x) + 0x0028)
+#define SDIx_RSP5(x) (SDIxBase(x) + 0x002c)
+#define SDIx_RSP6(x) (SDIxBase(x) + 0x0030)
+#define SDIx_RSP7(x) (SDIxBase(x) + 0x0034)
+#define SDIx_INFO1(x) (SDIxBase(x) + 0x0038)
+#define SDIx_INFO2(x) (SDIxBase(x) + 0x003c)
+#define SDIx_INFO1_MASK(x) (SDIxBase(x) + 0x0040)
+#define SDIx_INFO2_MASK(x) (SDIxBase(x) + 0x0044)
+#define SDIx_CLK_CTRL(x) (SDIxBase(x) + 0x0048)
+#define SDIx_SIZE(x) (SDIxBase(x) + 0x004c)
+#define SDIx_OPTION(x) (SDIxBase(x) + 0x0050)
+#define SDIx_ERR_STS1(x) (SDIxBase(x) + 0x0058)
+#define SDIx_ERR_STS2(x) (SDIxBase(x) + 0x005c)
+#define SDIx_BUF0(x) (SDIxBase(x) + 0x0060)
+#define SDIx_SDIO_MODE(x) (SDIxBase(x) + 0x0068)
+#define SDIx_SDIO_INFO1(x) (SDIxBase(x) + 0x006c)
+#define SDIx_SDIO_INFO1_MASK(x) (SDIxBase(x) + 0x0070)
+#define SDIx_CC_EXT_MODE(x) (SDIxBase(x) + 0x01b0)
+#define SDIx_SOFT_RST(x) (SDIxBase(x) + 0x01c0)
+#define SDIx_VERSION(x) (SDIxBase(x) + 0x01c4)
+#define SDIx_USER(x) (SDIxBase(x) + 0x0200)
+#define SDIx_USER2(x) (SDIxBase(x) + 0x0204)
+#define SDIx_DMA(x) (SDIxBase(x) + 0x0300)
+
+#define AB1Base 0x50070000
+#define AB1_ERROR (AB1Base + 0x0000)
+#define AB1_GENERAL (AB1Base + 0x0004)
+#define AB1_DEBUG0 (AB1Base + 0x0008)
+
+#define USBBase 0x60000000
+/* omitted */
+
+#define TimerBase(x) (0xc0000000 + 0x00000100 * (x))
+#define TI0 0x00
+#define TI1 0x01
+#define TI2 0x02
+#define TI3 0x03
+#define TW0 0x10
+#define TW1 0x11
+#define TW2 0x12
+#define TW3 0x13
+#define TG0 0x20
+#define TG1 0x21
+#define TG2 0x22
+#define TG3 0x23
+#define TG4 0x24
+#define TG5 0x25
+#define Txx_OP(x) (TimerBase(x) + 0x0000)
+#define Txx_CLR(x) (TimerBase(x) + 0x0004)
+#define Txx_SET(x) (TimerBase(x) + 0x0008)
+#define Txx_RCR(x) (TimerBase(x) + 0x000c)
+#define Txx_SCLR(x) (TimerBase(x) + 0x0014)
+
+#define AINTBase 0xc0020000
+#define IT0_IEN0 (AINTBase + 0x0000)
+#define IT0_IEN1 (AINTBase + 0x0004)
+#define IT0_IDS0 (AINTBase + 0x0008)
+#define IT0_IDS1 (AINTBase + 0x000c)
+#define IT0_RAW0 (AINTBase + 0x0010)
+#define IT0_RAW1 (AINTBase + 0x0014)
+#define IT0_MST0 (AINTBase + 0x0018)
+#define IT0_MST1 (AINTBase + 0x001c)
+#define IT0_IIR (AINTBase + 0x0024)
+#define IT0_IPI3_SET (AINTBase + 0x003c)
+#define IT3_IPI0_CLR (AINTBase + 0x005c)
+#define IT0_FIE (AINTBase + 0x0080)
+#define IT0_FID (AINTBase + 0x0084)
+#define IT0_IEN2 (AINTBase + 0x0100)
+#define IT0_IDS2 (AINTBase + 0x0104)
+#define IT0_RAW2 (AINTBase + 0x0108)
+#define IT0_MST2 (AINTBase + 0x010c)
+#define IT_PINV_SET0 (AINTBase + 0x0300)
+#define IT_PINV_SET1 (AINTBase + 0x0304)
+#define IT_PINV_SET2 (AINTBase + 0x0308)
+#define IT_PINV_CLR0 (AINTBase + 0x0310)
+#define IT_PINV_CLR1 (AINTBase + 0x0314)
+#define IT_PINV_CLR2 (AINTBase + 0x0318)
+#define IT0_LIIS (AINTBase + 0x0320)
+#define IT0_LIIR (AINTBase + 0x0324)
+#define IT3_IEN0 (AINTBase + 0xc000)
+#define IT3_IEN1 (AINTBase + 0xc004)
+#define IT3_IDS0 (AINTBase + 0xc008)
+#define IT3_IDS1 (AINTBase + 0xc00c)
+#define IT3_RAW0 (AINTBase + 0xc010)
+#define IT3_RAW1 (AINTBase + 0xc014)
+#define IT3_MST0 (AINTBase + 0xc018)
+#define IT3_MST1 (AINTBase + 0xc01c)
+#define IT3_IIR (AINTBase + 0xc024)
+#define IT3_IPI0_SET (AINTBase + 0xc030)
+#define IT0_IPI3_CLR (AINTBase + 0xc050)
+#define ID_VBS (AINTBase + 0xc090)
+#define ID_CLR (AINTBase + 0xc094)
+#define IT3_IEN2 (AINTBase + 0xc100)
+#define IT3_IDS2 (AINTBase + 0xc104)
+#define IT3_RAW2 (AINTBase + 0xc108)
+#define IT3_MST2 (AINTBase + 0xc10c)
+
+#define ASINTBase 0xcc010000
+#define IT0_IENS0 (ASINTBase + 0xe200)
+#define IT0_IENS1 (ASINTBase + 0xe204)
+#define IT0_IENS2 (ASINTBase + 0xe208)
+#define IT0_IDSS0 (ASINTBase + 0xe20c)
+#define IT0_IDSS1 (ASINTBase + 0xe210)
+#define IT0_IDSS2 (ASINTBase + 0xe214)
+
+#define GIOBase(x) (0xc0050000 + 0x00000040 * (x))
+#define GIO_L 0x00
+#define GIO_H 0x01
+#define GIO_HH 0x02
+#define GIO_HHH 0x08
+#define GIO_E1(x) (GIOBase(x) + 0x0000)
+#define GIO_E0(x) (GIOBase(x) + 0x0004)
+#define GIO_EM(x) (GIOBase(x) + 0x0004)
+#define GIO_OL(x) (GIOBase(x) + 0x0008)
+#define GIO_OH(x) (GIOBase(x) + 0x000c)
+#define GIO_I(x) (GIOBase(x) + 0x0010)
+#define GIO_IIA(x) (GIOBase(x) + 0x0014)
+#define GIO_IEN(x) (GIOBase(x) + 0x0018)
+#define GIO_IDS(x) (GIOBase(x) + 0x001c)
+#define GIO_IIM(x) (GIOBase(x) + 0x001c)
+#define GIO_RAW(x) (GIOBase(x) + 0x0020)
+#define GIO_MST(x) (GIOBase(x) + 0x0024)
+#define GIO_IIR(x) (GIOBase(x) + 0x0028)
+#define GIO_GSW(x) (GIOBase(x) + 0x003c)
+#define GIO_IDT0(x) (GIOBase(x) + 0x0100)
+#define GIO_IDT1(x) (GIOBase(x) + 0x0104)
+#define GIO_IDT2(x) (GIOBase(x) + 0x0108)
+#define GIO_IDT3(x) (GIOBase(x) + 0x010c)
+#define GIO_RAWBL(x) (GIOBase(x) + 0x0110)
+#define GIO_RAWBH(x) (GIOBase(x) + 0x0114)
+#define GIO_IRBL(x) (GIOBase(x) + 0x0118)
+#define GIO_IRBH(x) (GIOBase(x) + 0x011c)
+
+#define MEMCBase 0xc00a0000
+#define MEMC_CACHE_MODE (MEMCBase + 0x0000)
+#define MEMC_DEGFUN (MEMCBase + 0x0008)
+#define MEMC_INTSTATUS_A (MEMCBase + 0x0014)
+#define MEMC_INTRAWSTATUS_A (MEMCBase + 0x0018)
+#define MEMC_INTENSET_A (MEMCBase + 0x001c)
+#define MEMC_INTENCLR_A (MEMCBase + 0x0020)
+#define MEMC_INTFFCLR_A (MEMCBase + 0x0024)
+#define MEMC_ERRMID (MEMCBase + 0x0068)
+#define MEMC_ERRADR (MEMCBase + 0x006c)
+#define MEMC_REQSCH (MEMCBase + 0x1000)
+#define MEMC_DDR_CONFIGF (MEMCBase + 0x2000)
+#define MEMC_DDR_CONFIGA1 (MEMCBase + 0x2004)
+#define MEMC_DDR_CONFIGA2 (MEMCBase + 0x2008)
+#define MEMC_DDR_CONFIGC1 (MEMCBase + 0x200c)
+#define MEMC_DDR_CONFIGC2 (MEMCBase + 0x2010)
+#define MEMC_DDR_CONFIGR1 (MEMCBase + 0x2014)
+#define MEMC_DDR_CONFIGR2 (MEMCBase + 0x2018)
+#define MEMC_DDR_CONFIGR3 (MEMCBase + 0x201c)
+#define MEMC_DDR_CONFIGT1 (MEMCBase + 0x2020)
+#define MEMC_DDR_CONFIGT2 (MEMCBase + 0x2024)
+#define MEMC_DDR_CONFIGT3 (MEMCBase + 0x2028)
+#define MEMC_DDR_STATE8 (MEMCBase + 0x202c)
+
+#define PMUBase 0xc0100000
+#define PMU_PC (PMUBase + 0x0004)
+#define PMU_START (PMUBase + 0x0008)
+#define PMU_POWER_ON_PC (PMUBase + 0x0030)
+#define PMU_WDT_COUNT_EN (PMUBase + 0x0060)
+#define PMU_WDT_COUNT_LMT (PMUBase + 0x0064)
+#define PMU_INT_HANDLER_PC (PMUBase + 0x0068)
+#define PMU_PSR (PMUBase + 0x0070)
+#define PMU_TRIG_STATUS (PMUBase + 0x0074)
+#define PMU_REGA (PMUBase + 0x0078)
+#define PMU_REGB (PMUBase + 0x007c)
+#define PMU_INTSTATUS_A (PMUBase + 0x0080)
+#define PMU_INTRAWSTATUS_A (PMUBase + 0x0084)
+#define PMU_INTENSET_A (PMUBase + 0x0088)
+#define PMU_INTENCLR_A (PMUBase + 0x008c)
+#define PMU_INTFFCLR_A (PMUBase + 0x0090)
+#define PMU_PCERR (PMUBase + 0x00a8)
+#define PMU_CMD_BUF_RAM (PMUBase + 0x1000)
+#define PMU_CMD_BUF_FF (PMUBase + 0x2000)
+
+#define ASMUBase 0xc0110000
+#define RESETCTRL0 (ASMUBase + 0x0000)
+#define RESETREQ0 (ASMUBase + 0x0004)
+#define RESETREQ0ENA (ASMUBase + 0x0008)
+#define RESETREQ1 (ASMUBase + 0x000c)
+#define RESETREQ1ENA (ASMUBase + 0x0010)
+#define RESETREQ2 (ASMUBase + 0x0018)
+#define RESETREQ2ENA (ASMUBase + 0x001c)
+#define WDT_INT_RESET (ASMUBase + 0x0020)
+#define RESET_PCLK_COUNT (ASMUBase + 0x0024)
+#define AUTO_MODE_EN (ASMUBase + 0x007c)
+#define CLK_MODE_SEL (ASMUBase + 0x0080)
+#define PLL1CTRL0 (ASMUBase + 0x0084)
+#define PLL1CTRL1 (ASMUBase + 0x0088)
+#define PLL2CTRL0 (ASMUBase + 0x008c)
+#define PLL2CTRL1 (ASMUBase + 0x0090)
+#define PLL3CTRL0 (ASMUBase + 0x0094)
+#define PLL3CTRL1 (ASMUBase + 0x0098)
+#define PLLLOCKTIME (ASMUBase + 0x009c)
+#define AUTO_PLL_STANDBY (ASMUBase + 0x00a8)
+#define PLLVDDWAIT (ASMUBase + 0x00b4)
+#define CLKSTOPSIG_ST (ASMUBase + 0x00c4)
+#define CLK32_STATUS (ASMUBase + 0x00c8)
+#define POWER_RECORD (ASMUBase + 0x00cc)
+#define ASMU_INT_STATUS (ASMUBase + 0x00d0)
+#define ASMU_INT_RAW_STATUS (ASMUBase + 0x00d4)
+#define ASMU_INT_ENSET (ASMUBase + 0x00d8)
+#define ASMU_INT_ENCLR (ASMUBase + 0x00dc)
+#define ASMU_INT_ENMON (ASMUBase + 0x00e0)
+#define ASMU_INT_CLEAR (ASMUBase + 0x00e4)
+#define NORMALA_DIV (ASMUBase + 0x00f0)
+#define NORMALB_DIV (ASMUBase + 0x00f4)
+#define NORMALC_DIV (ASMUBase + 0x00f8)
+#define NORMALD_DIV (ASMUBase + 0x00fc)
+#define ECONOMY_DIV (ASMUBase + 0x0100)
+#define STANDBY_DIV (ASMUBase + 0x0104)
+#define POWERON_DIV (ASMUBase + 0x0108)
+#define DIVSP0SCLK (ASMUBase + 0x0118)
+#define DIVSP1SCLK (ASMUBase + 0x011c)
+#define DIVSP2SCLK (ASMUBase + 0x0120)
+#define DIVMEMCRCLK (ASMUBase + 0x0128)
+#define DIVCAMSCLK (ASMUBase + 0x012c)
+#define DIVLCDLCLK (ASMUBase + 0x0130)
+#define DIVIICSCLK (ASMUBase + 0x0134)
+#define TI0TIN_SEL (ASMUBase + 0x0138)
+#define TI1TIN_SEL (ASMUBase + 0x013c)
+#define TI2TIN_SEL (ASMUBase + 0x0140)
+#define TI3TIN_SEL (ASMUBase + 0x0144)
+#define TIGnTIN_SEL (ASMUBase + 0x0148)
+#define DIVTIMTIN (ASMUBase + 0x014c)
+#define DIVMWISCLK (ASMUBase + 0x0150)
+#define DIVDMATCLK (ASMUBase + 0x0154)
+#define DIVU70SCLK (ASMUBase + 0x0158)
+#define DIVU71SCLK (ASMUBase + 0x015c)
+#define DIVU72SCLK (ASMUBase + 0x0160)
+#define DIVPM0SCLK (ASMUBase + 0x016c)
+#define DIVPM1SCLK (ASMUBase + 0x0170)
+#define DIVREFCLK (ASMUBase + 0x0178)
+#define DIVPWMPWCLK (ASMUBase + 0x0184)
+#define AHBCLKCTRL0 (ASMUBase + 0x01a0)
+#define AHBCLKCTRL1 (ASMUBase + 0x01a4)
+#define APBCLKCTRL0 (ASMUBase + 0x01a8)
+#define APBCLKCTRL1 (ASMUBase + 0x01ac)
+#define CLKCTRL (ASMUBase + 0x01b0)
+#define GCLKCTRL0 (ASMUBase + 0x01b4)
+#define GCLKCTRL0ENA (ASMUBase + 0x01b8)
+#define GCLKCTRL1 (ASMUBase + 0x01bc)
+#define GCLKCTRL1ENA (ASMUBase + 0x01c0)
+#define GCLKCTRL2 (ASMUBase + 0x01c4)
+#define GCLKCTRL2ENA (ASMUBase + 0x01c8)
+#define GCLKCTRL3 (ASMUBase + 0x01cc)
+#define GCLKCTRL3ENA (ASMUBase + 0x01d0)
+#define AUTO_FRQ_CHANGE (ASMUBase + 0x01dc)
+#define AUTO_FRQ_MASK0 (ASMUBase + 0x01e0)
+#define AUTO_FRQ_MASK1 (ASMUBase + 0x01e4)
+#define DFS_HALFMODE (ASMUBase + 0x01e8)
+#define FLA_CLK_DLY (ASMUBase + 0x01f0)
+#define MEMCCLK270_SEL (ASMUBase + 0x01fc)
+#define ASMU_BGCTRL (ASMUBase + 0x0208)
+#define QR_ENA (ASMUBase + 0x0220)
+#define QR_CLKDIV (ASMUBase + 0x0224)
+#define FAKE_MODE (ASMUBase + 0x0238)
+#define POWERSW_STATUS (ASMUBase + 0x023c)
+#define POWERSW_ENA (ASMUBase + 0x0240)
+#define L1_POWERSW (ASMUBase + 0x0244)
+#define ACPU_POWERSW (ASMUBase + 0x0248)
+#define ADSP_POWERSW (ASMUBase + 0x024c)
+#define ACPU_BUB (ASMUBase + 0x0254)
+#define ADSP_BUB (ASMUBase + 0x0258)
+#define POWERSW_ACTRL_EN (ASMUBase + 0x025c)
+#define LOG1SW_ACTRL (ASMUBase + 0x0260)
+#define ADSPSW_ACTRL (ASMUBase + 0x0264)
+#define L1_BUZ (ASMUBase + 0x0268)
+#define L1_BUZ2 (ASMUBase + 0x026c)
+#define ACPUBUFTYPE (ASMUBase + 0x0288)
+#define ADSPUBUFTYPE (ASMUBase + 0x028c)
+#define HXBBUFTYPE (ASMUBase + 0x0290)
+#define STATUS_RECORD(n) (ASMUBase + 0x0320 + 0x004 *(n))
+#define ACPU_INIT (ASMUBase + 0x0360)
+#define AB1_U70WAITCTRL (ASMUBase + 0x03c0)
+#define AB1_U71WAITCTRL (ASMUBase + 0x03c4)
+#define AB1_U72WAITCTRL (ASMUBase + 0x03c8)
+#define AB1_IIC2WAITCTRL (ASMUBase + 0x03cc)
+#define AB1_IICWAITCTRL (ASMUBase + 0x03d0)
+#define AB1_U70READCTRL (ASMUBase + 0x03d4)
+#define AB1_U71READCTRL (ASMUBase + 0x03d8)
+#define AB1_U72READCTRL (ASMUBase + 0x03dc)
+#define AB1_IIC2READCTRL (ASMUBase + 0x03e0)
+#define AB1_IICREADCTRL (ASMUBase + 0x03e4)
+#define AB1_SDIBWAITCTRL (ASMUBase + 0x03e8)
+#define AB1_SDIBREADCTRL (ASMUBase + 0x03ec)
+#define AB1_SDICWAITCTRL (ASMUBase + 0x03f0)
+#define AB1_SDICREADCTRL (ASMUBase + 0x03f4)
+#define FLASHCLK_CTRL (ASMUBase + 0x0494)
+#define L2_POWERSW_BUZ (ASMUBase + 0x0500)
+#define LOG2SW_ACTRLEN (ASMUBase + 0x0504)
+#define LOG2SW_ACTRL (ASMUBase + 0x0508)
+#define L3_POWERSW_BUZ (ASMUBase + 0x050c)
+#define LOG3SW_ACTRLEN (ASMUBase + 0x0510)
+#define LOG3SW_ACTRL (ASMUBase + 0x0514)
+#define PLL_STATUS (ASMUBase + 0x0520)
+#define IO_L0_LM_BUZ (ASMUBase + 0x0814)
+#define RESETREQ3 (ASMUBase + 0x083c)
+#define RESETREQ3ENA (ASMUBase + 0x0840)
+#define APBCLKCTRL2 (ASMUBase + 0x0848)
+#define GCLKCTRL4 (ASMUBase + 0x084c)
+#define GCLKCTRL4ENA (ASMUBase + 0x0850)
+#define AUTO_FRQ_MASK3 (ASMUBase + 0x0860)
+#define DFS_FIFOMODE (ASMUBase + 0x0864)
+#define DFS_FIFO_REQMASK (ASMUBase + 0x0868)
+#define LCD_FIFOTHRESHOLD (ASMUBase + 0x086c)
+#define CAM_FIFOTHRESHOLD (ASMUBase + 0x0870)
+#define CAM_SAFE_RESET (ASMUBase + 0x0878)
+#define DTV_SAFE_RESET (ASMUBase + 0x0880)
+#define USB_SAFE_RESET (ASMUBase + 0x0884)
+#define CLKCTRL1 (ASMUBase + 0x088c)
+#define AB1_SDIAWAITCTRL (ASMUBase + 0x0890)
+#define AB1_SDIAREADCTRL (ASMUBase + 0x0894)
+#define MEMC_HAND_SHAKE_FAKE (ASMUBase + 0x08a0)
+#define SEL_BIGWEST (ASMUBase + 0x08b8)
+
+#define SPnBase(n) (0xc0120000 + 0x00010000 * (n))
+#define SP0 0x00
+#define SP1 0x01
+#define SPn_MODE(n) (SPnBase(n) + 0x0000)
+#define SPn_POL(n) (SPnBase(n) + 0x0004)
+#define SPn_CONTROL(n) (SPnBase(n) + 0x0008)
+#define SPn_TX_DATA(n) (SPnBase(n) + 0x0010)
+#define SPn_RX_DATA(n) (SPnBase(n) + 0x0014)
+#define SPn_STATUS(n) (SPnBase(n) + 0x0018)
+#define SPn_RAW_STATUS(n) (SPnBase(n) + 0x001c)
+#define SPn_ENSET(n) (SPnBase(n) + 0x0020)
+#define SPn_ENCLR(n) (SPnBase(n) + 0x0024)
+#define SPn_FFCLR(n) (SPnBase(n) + 0x0028)
+#define SPn_CONTROL2(n) (SPnBase(n) + 0x0034)
+#define SPn_TIECS(n) (SPnBase(n) + 0x0038)
+
+#define CHGREGBase 0xc0140000
+#define CHG_BOOT_MODE (CHGREGBase + 0x0000)
+#define CHG_L1_HOLD (CHGREGBase + 0x0004)
+#define CHG_LSI_REVISION (CHGREGBase + 0x0010)
+#define CHG_CTRL_SDINT (CHGREGBase + 0x0104)
+#define CHG_CTRL_AB0_BOOT (CHGREGBase + 0x0108)
+#define CHG_CTRL_OSC (CHGREGBase + 0x0110)
+#define CHG_PINSEL_G(n) (CHGREGBase + 0x0200 + 0x0004 * ((n) / 16))
+#define CHG_PINSEL_SP0 (CHGREGBase + 0x0280)
+#define CHG_PINSEL_DTV (CHGREGBase + 0x0284)
+#define CHG_PINSEL_SD0 (CHGREGBase + 0x0288)
+#define CHG_PINSEL_SD1 (CHGREGBase + 0x028c)
+#define CHG_PINSEL_IIC2 (CHGREGBase + 0x0290)
+#define CHG_PINSEL_REFCLKO (CHGREGBase + 0x0294)
+#define CHG_PULL_G(n) (CHGREGBase + 0x0300 + 0x0004 * ((n) / 8))
+#define CHG_PULL(n) (CHGREGBase + 0x0380 + 0x0004 * (n))
+#define CHG_DRIVE(n) (CHGREGBase + 0x0400 + 0x0004 * (n))
+
+#define IICBase(x) (0x50030000 + 0x00010000 * (x))
+#define IIC 0x01
+#define IIC2 0x00
+#define IIC_IIC(n) (IICBase(n) + 0x0000)
+#define IIC_IICC(n) (IICBase(n) + 0x0008)
+#define IIC_SVA(n) (IICBase(n) + 0x000c)
+#define IIC_IICCL(n) (IICBase(n) + 0x0010)
+#define IIC_IICSE(n) (IICBase(n) + 0x001c)
+#define IIC_IICF(n) (IICBase(n) + 0x0028)
+
+#endif /*__MONITOR_ARM_EM1D_H__*/
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-em1d/memattr.S b/tkernel_source/monitor/hwdepend/arm/mach-em1d/memattr.S
new file mode 100644
index 0000000..eb1fa2e
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-em1d/memattr.S
@@ -0,0 +1,129 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * memattr.S
+ *
+ * manipulation of page table
+ */
+#define _in_asm_source_
+
+#include <machine.h>
+#include <tk/sysdef.h>
+
+#include "setup_em1d512.h"
+
+/*
+ * memory barrier macros
+ */
+.macro _mov reg, val
+ .ifnes "\reg", "\val"
+ mov \reg, \val
+ .endif
+.endm
+.macro .ISB reg, val=#0
+ _mov \reg, \val
+ mcr p15, 0, \reg, cr7, c5, 4
+.endm
+.macro .DSB reg, val=#0
+ _mov \reg, \val
+ mcr p15, 0, \reg, cr7, c10, 4
+.endm
+.macro .DMB reg, val=#0
+ _mov \reg, \val
+ mcr p15, 0, \reg, cr7, c10, 5
+.endm
+
+/*
+ * change memory attribute
+ * void ChangeMemAttr(UW top, UW end, UW attr)
+ * change the memory attribute of memory area from `top' to `end' - 1 into `attr'
+ * The physical address where T-Monitor resides is assumed to start at 0x00000000.
+ * It must be called with disabled cache.
+ */
+ .text
+ .balign 4
+ .globl Csym(ChangeMemAttr)
+ .type Csym(ChangeMemAttr), %function
+Csym(ChangeMemAttr):
+changememattr_start:
+ stmfd sp!, {r4, r5, r7, r9, r10}
+
+ /* Map T-Monitor to 0x00000000 and up, the information before the mapping is saved. */
+ ldr ip, =PAGETBL_BASE
+ ldr r4, [ip]
+ ldr r10, =attr_prev
+ str r4, [r10]
+ ldr r4, =0x00009402 // Strongly-order, Kernel/RO
+ str r4, [ip]
+
+ .DSB r4
+ mcr p15, 0, r4, cr8, cr7, 0 // I/D TLB invalidate
+ mcr p15, 0, r4, cr7, cr5, 6 // invalidate BTC
+ .DSB r4
+ .ISB r4
+
+ /* Jump to the address into the remapped area */
+ ldr r4, =changememattr_main
+ ldr r9, =0xfff00000
+ bic r4, r4, r9 // r4 &= 0x000fffff
+ mov pc, r4
+
+ .pool
+
+changememattr_main:
+ bic r2, r2, r9 // r2 &= 0x000fffff
+ mov r4, r0, lsr #20
+ add r4, ip, r4, lsl #2 // r4 = (r2 >> 20) * 4 + PAGETBL_BASE
+
+changememattr_loop:
+ ldr r5, [r4] // *r4 = (*r4 & 0xfff00000) | r2
+ and r5, r5, r9
+ orr r5, r5, r2
+ str r5, [r4], #4
+ add r0, r0, #0x00100000
+ cmp r0, r1
+ bne changememattr_loop
+
+ /* Jump to the address in the originally mapped area */
+ .DSB r4
+ mcr p15, 0, r4, cr8, cr7, 0 // I/D TLB invalidate
+ mcr p15, 0, r4, cr7, cr5, 6 // invalidate BTC
+ .DSB r4
+ .ISB r4
+
+ ldr pc, =changememattr_finish
+
+ .pool
+
+changememattr_finish:
+ /* Unmap the T-Monitor in the area from 0x00000000 and up. */
+ ldr r4, [r10] // attr_prev
+ str r4, [ip] // PAGETBL_BASE
+
+ .DSB r4
+ mcr p15, 0, r4, cr8, cr7, 0 // I/D TLB invalidate
+ mcr p15, 0, r4, cr7, cr5, 6 // invalidate BTC
+ .DSB r4
+ .ISB r4
+
+ ldmfd sp!, {r4, r5, r7, r9, r10}
+ bx lr
+
+ .pool
+
+
+ .bss
+attr_prev:
+ .long 0
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-em1d/misc.c b/tkernel_source/monitor/hwdepend/arm/mach-em1d/misc.c
new file mode 100644
index 0000000..4486c5a
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-em1d/misc.c
@@ -0,0 +1,46 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * misc.c
+ *
+ */
+
+#include "sysdepend.h"
+
+/*
+ * obtain switch status
+ */
+EXPORT UW getDipSw( void )
+{
+ return DipSw;
+}
+
+/*
+ * Obtain boot selection information
+ */
+EXPORT W bootSelect( void )
+{
+ if ( (DipSw & (SW_MON|SW_ABT)) != 0 ) return BS_MONITOR;
+
+ return BS_AUTO;
+}
+
+/*
+ * obtain the console port number
+ */
+EXPORT W getConPort( void )
+{
+ return 0;
+}
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-em1d/setup_em1d512.h b/tkernel_source/monitor/hwdepend/arm/mach-em1d/setup_em1d512.h
new file mode 100644
index 0000000..e733589
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-em1d/setup_em1d512.h
@@ -0,0 +1,47 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * setup_em1d512.h
+ *
+ * EM1D-512 configuration information
+ *
+ * this file included from assembly source files, too.
+ */
+
+#define EITENT_BASE 0x70000000 /* address for exception branch processing */
+#define PAGETBL_BASE 0x30000000 /* address of the first level table page. */
+
+/*
+ * clock value
+ */
+#define PLL1_CLK 499712 /* 499.712MHz */
+#define PLL2_CLK 401418 /* 401.408MHz */
+#define PLL3_CLK 229376 /* 229.376MHz */
+
+#define ACPU_CLK (PLL1_CLK / 1)
+#define Txx_CLK (PLL3_CLK / 8)
+
+/*
+ * assignment to DipSw (switches)
+ */
+#define SW_ABT 0x0100 /* Abort SW */
+#define SW_MON 0x0020 /* Monitor Boot */
+#define SW_BHI 0x0000 /* fix HI_BAUD_RATE */
+
+/*
+ * LED display (two bits, 2 bits)
+ */
+#define LED_POWERUP 0x01 /* Power-on */
+#define LED_MEMCLR 0xff /* Memory clear */
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-em1d/sio.c b/tkernel_source/monitor/hwdepend/arm/mach-em1d/sio.c
new file mode 100644
index 0000000..af858b2
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-em1d/sio.c
@@ -0,0 +1,80 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * sio.c
+ *
+ * serial port I/O
+ */
+
+#include "hwdepend.h"
+
+EXPORT W ConPort; /* console port number */
+EXPORT UW ConPortBps; /* console port commnication speed (bps) */
+
+LOCAL SIOCB SIO; /* serial port control block */
+
+/*
+ * initialize serial port
+ * port console port number (0 - )
+ * when it is -1, it means there is no console.
+ * speed communication speed (bps)
+ */
+EXPORT ER initSIO( W port, W speed )
+{
+ const CFGSIO *cp;
+ ER err;
+
+ if ( port >= N_ConfigSIO ) port = 0; /* invalid value is turned into a default value. */
+
+ memset(&SIO, 0, sizeof(SIO));
+ ConPort = port;
+ ConPortBps = speed;
+
+ if ( port < 0 ) return E_OK; /* no console */
+
+ /* initialize hardware */
+ cp = &ConfigSIO[port];
+ err = (*cp->initsio)(&SIO, cp, speed);
+ if ( err < E_OK ) goto err_ret;
+
+ return E_OK;
+
+err_ret:
+ /* if there was an error, treat it as no console */
+ memset(&SIO, 0, sizeof(SIO));
+ ConPort = -1;
+ return err;
+}
+
+/*
+ * serial port I/O
+ */
+EXPORT void putSIO( UB c )
+{
+ if ( SIO.put != NULL ) (*SIO.put)(&SIO, c);
+}
+
+/*
+ * serial port input (with buffering)
+ * tmo timeout (milliseconds)
+ * You can not wait forever.
+ * return value >= 0 : character code
+ * -1 : timeout
+ * receive error is ignored
+ */
+EXPORT W getSIO( W tmo )
+{
+ return ( SIO.get != NULL )? (*SIO.get)(&SIO, tmo): -1;
+}
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-em1d/startup.c b/tkernel_source/monitor/hwdepend/arm/mach-em1d/startup.c
new file mode 100644
index 0000000..fa0feb3
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-em1d/startup.c
@@ -0,0 +1,92 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * startup.c
+ *
+ * system boot processing
+ */
+
+#include "hwdepend.h"
+
+/* No support for the progress report yet */
+#define DispProgress(n) /* nop */
+
+/*
+ * debug port speed
+ * default setting is LO:38400bps, and HI:115200bps. But
+ * if you need a different set value, then define the following macros in {cpu}/{machine}/setup_xxx.h :
+ * LO_BAUD_RATE, and HI_BAUD_RATE.
+ */
+#ifndef LO_BAUD_RATE
+# define LO_BAUD_RATE 38400
+#endif
+#ifndef HI_BAUD_RATE
+# define HI_BAUD_RATE 115200
+#endif
+
+/*
+ * initial processing after reset
+ */
+EXPORT void procReset( void )
+{
+ const MEMSEG *mp;
+ W i;
+ W speed;
+
+ DispProgress(0x01);
+
+ /* system basic set up */
+ resetSystem(0);
+ DispProgress(0x06);
+
+ /* setting up the initial count for micro-wait */
+ setupWaitUsec();
+ DispProgress(0x07);
+
+ /* initialize console serial port */
+#if SW_BHI == 0
+ speed = HI_BAUD_RATE; /* HI speed is fixed. */
+#else
+ speed = ( (DipSw & SW_BHI) != 0 )? HI_BAUD_RATE: LO_BAUD_RATE;
+#endif
+ initSIO(getConPort(), speed);
+ DispProgress(0x08);
+
+ /* initialize hardware (peripherals) */
+ initHardware();
+ DispProgress(0x0d);
+
+ /* memory clear is not done to save time when automatic reboot is under way. */
+ if ( bootSelect() == BS_MONITOR ) {
+ cpuLED(LED_MEMCLR);
+
+ /* all memory clear (save the monitor area) */
+ for ( i = 1;; ++i ) {
+ mp = MemArea(MSA_OS|MSA_ERAM, i);
+ if ( mp == NULL ) break;
+
+ memset((void*)mp->top, 0, mp->end - mp->top);
+ }
+ }
+ cpuLED(LED_POWERUP);
+ DispProgress(0x0e);
+
+ /* initialize break processing */
+ initBreak();
+
+ /* Invoking user reset initialization routine */
+ callUserResetInit();
+ DispProgress(0x0f);
+}
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-em1d/sysdepend.h b/tkernel_source/monitor/hwdepend/arm/mach-em1d/sysdepend.h
new file mode 100644
index 0000000..8003371
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-em1d/sysdepend.h
@@ -0,0 +1,43 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * sysdepend.h
+ *
+ * system-related definitions: ARM CPUs.
+ */
+
+#ifndef __MONITOR_CMDSVC_SYSDEPEND_H__
+#define __MONITOR_CMDSVC_SYSDEPEND_H__
+
+#include "hwdepend.h"
+#include <sys/sysinfo.h>
+#include <sys/rominfo.h>
+#include "setup_em1d512.h"
+
+/*
+ * cache and MMU control
+ */
+IMPORT void setCacheMMU( UW cp15r1 );
+
+/*
+ * machine-dependent interrupt processing
+ * info is defined in machine-dependent manner.
+ * return value 0 : it is not the target of processing.
+ * 1 : the object is the target of processing (the monitor should continue monitoring)
+ * 2 : the object is the target of processing (exiting interrupt handler).
+ */
+IMPORT W procHwInt( UW info );
+
+#endif /* __MONITOR_CMDSVC_SYSDEPEND_H__ */
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-em1d/system.c b/tkernel_source/monitor/hwdepend/arm/mach-em1d/system.c
new file mode 100644
index 0000000..fb541a0
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-em1d/system.c
@@ -0,0 +1,307 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by T-Engine Forum at 2011/09/08.
+ * Modified by T-Engine Forum at 2013/03/04.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * system.c
+ *
+ * system-related processing
+ *
+ * target: EM1D-512
+ */
+
+#include "sysdepend.h"
+#include <arm/em1d512.h>
+
+EXPORT UW DipSw; /* DipSw status */
+
+/* hardware dependent functions */
+IMPORT UW DipSwStatus(void);
+IMPORT void usbPower(BOOL power);
+IMPORT void powerOff(void);
+IMPORT void resetStart(void);
+
+/* interrupt entry point (eitent.S) */
+IMPORT void _gio0Hdr(void);
+IMPORT void _gio1Hdr(void);
+IMPORT void _gio2Hdr(void);
+IMPORT void _gio3Hdr(void);
+IMPORT void _gio4Hdr(void);
+IMPORT void _gio5Hdr(void);
+IMPORT void _gio6Hdr(void);
+IMPORT void _gio7Hdr(void);
+
+/* default handler (cmdsvc) */
+IMPORT void _defaultHdr(void);
+
+/* macros for manipulating cache/MMU/PMIC */
+#define EnbCacheMMU(x) setCacheMMU(ENB_CACHEMMU)
+#define DisCacheMMU(x) setCacheMMU(ENB_MMUONLY) /* MMU can't be turned off */
+
+/* ------------------------------------------------------------------------ */
+
+IMPORT char __loadaddr; /* monitor load address */
+IMPORT MEMSEG NoMemSeg[]; /* memory unused area */
+IMPORT W N_NoMemSeg;
+
+/*
+ power management controller (DA9052) handler routines
+*/
+#define SPIPol 0x0092
+
+/* initialize SPI for PMIC communication */
+LOCAL void pmicInit(void)
+{
+ out_w(SPn_MODE(SP0), 0x2700); /* 8bit, CS0, Master, CPU mode */
+ out_w(SPn_TIECS(SP0), 0x000f); /* CS0: follow the specification by SPn_POL */
+ out_w(SPn_POL(SP0), SPIPol);
+ out_w(SPn_ENCLR(SP0), ~0); /* interrupt disable */
+
+ out_w(SPn_CONTROL(SP0), 0x0100); /* start reset */
+ waitUsec(10);
+ out_w(SPn_CONTROL(SP0), 0x0000); /* release reset */
+ out_w(SPn_CONTROL2(SP0), 0x0000);
+
+ return;
+}
+
+/* wait for data of SPI for PMIC communication */
+LOCAL void pmicWait(void)
+{
+ W i;
+
+ for (i = 1000000; i > 0; i--) {
+ if (in_w(SPn_RAW_STATUS(SP0)) & 0x0004) break;
+ waitUsec(1);
+ }
+ if (!i) pmicInit();
+
+ return;
+}
+
+/* contro CS line of SPI for PMIC communication */
+LOCAL void pmicCSassert(BOOL cs)
+{
+ waitNsec(200);
+ out_w(SPn_POL(SP0), SPIPol ^ (cs ? 0x0001 : 0x0000));
+ waitNsec(200);
+
+ return;
+}
+
+/* read PMIC register */
+EXPORT W pmicRead(W reg)
+{
+ W dat;
+
+ pmicCSassert(TRUE); /* CS assert */
+
+ out_w(SPn_FFCLR(SP0), ~0); /* status flag is cleared */
+ out_w(SPn_TX_DATA(SP0), (reg << 1) | 1); /* send register number */
+ out_w(SPn_CONTROL(SP0), 0x0009); /* send start */
+ pmicWait();
+
+ out_w(SPn_FFCLR(SP0), ~0); /* status flag is cleared */
+ out_w(SPn_CONTROL(SP0), 0x0005); /* start receive */
+ pmicWait();
+ dat = in_w(SPn_RX_DATA(SP0)); /* data received */
+
+ pmicCSassert(FALSE); /* CS de-assert */
+
+ return dat;
+}
+
+/* write PMIC register */
+EXPORT void pmicWrite(W reg, W dat)
+{
+ pmicCSassert(TRUE); /* CS assert */
+
+ out_w(SPn_FFCLR(SP0), ~0); /* status flag is cleared */
+ out_w(SPn_TX_DATA(SP0), reg << 1); /* send register number */
+ out_w(SPn_CONTROL(SP0), 0x0009); /* send start */
+ pmicWait();
+
+ out_w(SPn_FFCLR(SP0), ~0); /* status flag is cleared */
+ out_w(SPn_TX_DATA(SP0), dat); /* send data */
+ out_w(SPn_CONTROL(SP0), 0x0009); /* send start */
+ pmicWait();
+
+ pmicCSassert(FALSE); /* CS de-assert */
+
+ return;
+}
+
+/* ------------------------------------------------------------------------ */
+
+/* basic system set up (performed during reset, and Disk Boot) */
+EXPORT void resetSystem(W boot)
+{
+ MEMSEG *mp;
+ UW i, va;
+
+ /* obtain DipSw status */
+ if (!boot) DipSw = DipSwStatus();
+
+ DisCacheMMU();
+
+ /* set up interrupt controller */
+ out_w(IT0_IDS0, ~0); /* CPU: all interrupts disabled */
+ out_w(IT0_IDS1, ~0);
+ out_w(IT0_IDS2, ~0);
+ out_w(IT0_IIR, ~0);
+ out_w(IT3_IPI0_CLR, 0x0000003f);
+ out_w(IT3_IDS0, ~0); /* DSP: all interrupts disabled */
+ out_w(IT3_IDS1, ~0);
+ out_w(IT3_IDS2, ~0);
+ out_w(IT3_IIR, ~0);
+ out_w(IT0_IPI3_CLR, 0x0000003f);
+ out_w(IT0_FID, 0x00000001); /* CPU: FIQ disabled */
+ out_w(GIO_IIA(GIO_L), 0); /* GPIO: interrupt disabled */
+ out_w(GIO_IIA(GIO_H), 0);
+ out_w(GIO_IIA(GIO_HH), 0);
+ out_w(GIO_IIA(GIO_HHH), 0);
+ out_w(GIO_GSW(GIO_L), 0); /* GPIO: FIQ interrupt disabled */
+ out_w(GIO_GSW(GIO_H), 0);
+ out_w(GIO_GSW(GIO_HH), 0);
+ out_w(GIO_GSW(GIO_HHH), 0);
+ out_w(IT0_LIIR, 0x0000000f); /* internal interrupt disabled */
+ out_w(IT_PINV_CLR0, ~0); /* inhibit interrupt polarity inversion */
+ out_w(IT_PINV_CLR1, ~0);
+ out_w(IT_PINV_CLR2, ~0);
+ out_w(IT0_IEN0, 0x0c000000); /* CPU: GPIO interrupt enabled */
+ out_w(IT0_IEN1, 0x003c0000);
+ out_w(IT0_IEN2, 0x00018000);
+
+ /* power on controller initialization */
+ pmicInit();
+
+ /* USB power on */
+ usbPower(TRUE);
+
+ /* clear system common area (vector table, and SysInfo) */
+ memset(&SCInfo, 0, sizeof(SysCommonInfo));
+ memset(SCArea, 0, sizeof(SysCommonArea));
+
+ /* if monitor is loaded into RAM, exclude the RAM area */
+ mp = MemArea(MSA_OS, 1);
+ va = (UW)&__loadaddr;
+ if (va >= mp->top && va < mp->end) mp->end = va;
+
+ /* exclude the area where ROM disk data is stored */
+ va = (UW)ROMInfo->userarea;
+ if (va >= mp->top && va < mp->end) mp->end = va;
+
+ /* initialize system common information (SysInfo) */
+ SCInfo.ramtop = (void*)mp->top;
+ if (va < mp->top || va > mp->end) va = mp->end;
+ SCInfo.ramend = (void*)va;
+
+ /* set up EIT vectors */
+ /* we do not need _defaultHdr absolutely, but just in case set it up */
+ SCArea->intvec[EIT_DEFAULT] = _defaultHdr; /* default handler */
+ SCArea->intvec[EIT_UNDEF] = _defaultHdr; /* undefined instruction */
+ SCArea->intvec[SWI_MONITOR] = _defaultHdr; /* SWI - monitor SVC */
+ SCArea->intvec[EIT_IRQ(26)] = _gio6Hdr; /* GPIO branch */
+ SCArea->intvec[EIT_IRQ(27)] = _gio7Hdr;
+ SCArea->intvec[EIT_IRQ(50)] = _gio0Hdr;
+ SCArea->intvec[EIT_IRQ(51)] = _gio1Hdr;
+ SCArea->intvec[EIT_IRQ(52)] = _gio2Hdr;
+ SCArea->intvec[EIT_IRQ(53)] = _gio3Hdr;
+ SCArea->intvec[EIT_IRQ(79)] = _gio4Hdr;
+ SCArea->intvec[EIT_IRQ(80)] = _gio5Hdr;
+ SCArea->intvec[EIT_GPIO(8)] = _defaultHdr; /* abort switch */
+
+ /* set up initial page table */
+ for (i = 0; i < N_MemSeg; ++i) {
+ mp = &MemSeg[i];
+ if (!mp->pa) continue;
+
+ /* FlashROM has already been mapped, and so do not touch it */
+ if (mp->attr == MSA_FROM) continue;
+
+ /* set up in unit of section (1MB) */
+ for ( va = (mp->top & 0xfff00000);
+ va != ((mp->end + 0x000fffff) & 0xfff00000);
+ va += 0x00100000 ) {
+ TopPageTable[va / 0x00100000] =
+ ((mp->pa & 0xfff00000) + va) |
+ (mp->pa & 0x000fffff);
+ }
+ }
+
+ for (i = 0; i < N_NoMemSeg; ++i) {
+ mp = &NoMemSeg[i];
+
+ /* set up in unit of section (1MB) */
+ for ( va = (mp->top & 0xfff00000);
+ va != ((mp->end + 0x000fffff) & 0xfff00000);
+ va += 0x00100000 ) {
+ TopPageTable[va / 0x00100000] = 0;
+ }
+ }
+
+ DSB();
+ Asm("mcr p15, 0, %0, cr8, c7, 0":: "r"(0)); /* I/D TLB invalidate */
+ Asm("mcr p15, 0, %0, cr7, c5, 6":: "r"(0)); /* invalidate BTC */
+ DSB();
+ ISB();
+
+ EnbCacheMMU();
+
+ return;
+}
+
+/* ------------------------------------------------------------------------ */
+
+/*
+ system termination: reset / system power off
+ reset 0 power off
+ -1 reboot
+ 0xaa55 halt boot and power off
+*/
+EXPORT void sysExit(W reset)
+{
+ DisCacheMMU();
+
+ /* after this point, delay such as waitUsec() spends more time than the number indicates // */
+
+ /* LED off */
+ cpuLED(0x00);
+
+ /* all interrupts disabled */
+ out_w(IT0_IDS0, ~0); /* CPU: all interrupts disabled */
+ out_w(IT0_IDS1, ~0);
+ out_w(IT0_IDS2, ~0);
+ out_w(IT3_IPI0_CLR, 0x0000003f);
+ out_w(IT3_IDS0, ~0); /* DSP: all interrupts disabled */
+ out_w(IT3_IDS1, ~0);
+ out_w(IT3_IDS2, ~0);
+ out_w(IT0_IPI3_CLR, 0x0000003f);
+ out_w(IT0_FID, 0x00000001); /* FIQ disabled */
+ out_w(IT0_LIIR, 0x0000000f); /* internal interrupt disabled */
+
+ /* power on controller initialization */
+ pmicInit();
+
+ /* USB power off */
+ usbPower(FALSE);
+
+ if (reset >= 0) powerOff();
+
+ /* reset start */
+ resetStart();
+}
+
+/* ------------------------------------------------------------------------ */
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-em1d/waitusec.c b/tkernel_source/monitor/hwdepend/arm/mach-em1d/waitusec.c
new file mode 100644
index 0000000..8ffac07
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/mach-em1d/waitusec.c
@@ -0,0 +1,112 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * waitusec.c
+ *
+ * EM1-D512: micro wait
+ */
+
+#include "sysdepend.h"
+#include <arm/em1d512.h>
+
+LOCAL UW delay64us; /* wait for 64 microsec */
+
+/*
+ * wait for nanoseconds
+ */
+EXPORT void waitNsec(_UW nsec)
+{
+ for (nsec = nsec * delay64us / 64000; nsec > 0; nsec--);
+
+ return;
+}
+
+/*
+ * wait for microseconds
+ */
+EXPORT void waitUsec(_UW usec)
+{
+ for (usec = usec * delay64us / 64; usec > 0; usec--);
+
+ return;
+}
+
+/*
+ * wait for milliseconds
+ */
+EXPORT void waitMsec(UW msec)
+{
+ while (msec-- > 0) waitUsec(1000);
+
+ return;
+}
+
+/* ------------------------------------------------------------------------ */
+
+/*
+ * setting up the initial count for micro-wait()
+ */
+EXPORT void setupWaitUsec(void)
+{
+ UW t0, t1, t2;
+
+#define MAX_CNT (ACPU_CLK * 64 / 10) /* 1 Clock */
+#define MIN_CNT (ACPU_CLK * 64 / 1280) /* 128 Clock */
+
+ /* use TI0 timer, and assume clock is PLL3 / 8 */
+ out_w(Txx_OP(TI0), 0); /* Timer stop, count clear */
+ while (in_w(Txx_RCR(TI0)));
+
+ out_w(Txx_SET(TI0), 0xffffffff); /* maximum count */
+ out_w(Txx_OP(TI0), 0x00000003); /* Timer start */
+
+ delay64us = 64;
+ waitUsec(1000); /* wait for a while until things settle down */
+
+ t0 = in_w(Txx_RCR(TI0));
+ waitUsec(1000);
+ t1 = in_w(Txx_RCR(TI0));
+ waitUsec(3000);
+ t2 = in_w(Txx_RCR(TI0));
+
+ out_w(Txx_OP(TI0),0); /* Timer stop, count clear */
+ while (in_w(Txx_RCR(TI0)));
+
+ t2 -= t1; /* count for 3000 times */
+ t1 -= t0; /* count for 1000 times */
+ t2 -= t1; /* count for 2000 times */
+
+ /*
+ * calculate the count for 64 microsec
+ *
+ * 2000 loops x timer clock [MHz] x 64 [microsec]
+ * delay64us = ------------------------------------------------
+ * t2
+ *
+ * * considering the representation of PLL3_CLK (1/1000MHz unit), and setting of pre scaler,
+ * it can be written down as follows.
+ *
+ * 2 loops x PLL3_CLK [1/1000MHz] x 8 [microsec]
+ * delay64us = -------------------------------------------
+ * t2
+ *
+ */
+ delay64us = (t2 == 0) ? MAX_CNT : ((2 * PLL3_CLK * 8) / t2);
+ if (delay64us > MAX_CNT) delay64us = MAX_CNT;
+ else if (delay64us < MIN_CNT) delay64us = MIN_CNT;
+
+ return;
+}
+
diff --git a/tkernel_source/monitor/hwdepend/arm/misc.c b/tkernel_source/monitor/hwdepend/arm/misc.c
new file mode 100644
index 0000000..cc58200
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/misc.c
@@ -0,0 +1,54 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * misc.c
+ *
+ */
+
+#include "../cmdsvc.h"
+#include <sys/rominfo.h>
+
+/*
+ * Invoking user reset initialization routine
+ */
+EXPORT void callUserResetInit( void )
+{
+ UW wp = (UW)ROMInfo->resetinit;
+
+ if ( invalidPC2(wp)
+ || !inMemArea(wp, wp+4, MSA_ROM|MSA_FROM)
+ || inMemArea(wp, wp+4, MSA_MON) ) return; /* invalid */
+
+ callExtProg(ROMInfo->resetinit);
+}
+
+/*
+ * Prepare ROM kernel execution
+ * It means that we don't execute ROM kernel immediately, but we prepare so that upon return from the ordinary monitor,
+ * it gets executed.
+ */
+EXPORT ER bootROM( void )
+{
+ UW wp = (UW)ROMInfo->kernel;
+
+ if ( invalidPC2(wp)
+ || !inMemArea(wp, wp+4, MSA_ROM|MSA_FROM)
+ || inMemArea(wp, wp+4, MSA_MON) ) return E_NOEXS; /* invalid */
+
+ /* set boot configuration */
+ setUpBoot(ROMInfo->kernel, NULL);
+
+ return E_OK;
+}
diff --git a/tkernel_source/monitor/hwdepend/arm/monent.c b/tkernel_source/monitor/hwdepend/arm/monent.c
new file mode 100644
index 0000000..2cba3d8
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/monent.c
@@ -0,0 +1,97 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * monent.c
+ *
+ * Entry to monitor
+ */
+
+#include "../cmdsvc.h"
+#include <sys/sysinfo.h>
+
+EXPORT W bootFlag; /* boot flag */
+
+/*
+ * monitor entry processing
+ * vec exception vector number
+ */
+EXPORT void entMonitor( UW vec )
+{
+ UW v;
+ W bpflg;
+ UB *cmd;
+ UW save_taskmode;
+
+ /* update task mode */
+ save_taskmode = SCInfo.taskmode;
+ SCInfo.taskmode <<= 16;
+
+ /* monitor entry processing (flushing cache, etc.) */
+ enterMonitor(0);
+
+ /* initialize address check data */
+ initChkAddr();
+
+ /* release breakpoint temporarily */
+ bpflg = resetBreak(vec);
+
+ bootFlag = 0;
+
+ switch ( vec ) {
+ case EIT_DEFAULT: /* reset */
+ if ( bootSelect() == BS_AUTO ) {
+ /* automatic boot */
+ if ( bootDisk(NULL) >= E_OK ) break; /* execute boot */
+ }
+ /* invoke monitor */
+ dispTitle(); /* boot message */
+ procCommand(NULL, 0); /* command processing */
+ break;
+
+ case SWI_MONITOR: /* service call */
+ /* Execute SVC: Parameters given are, r12(fn), r0, r1, r2, r3 */
+ v = procSVC(getRegister(12), getRegister(0),
+ getRegister(1), getRegister(2), getRegister(3));
+
+ /* At boot time, r0 holds the boot parameter,
+ so don't change r0 */
+ if ( bootFlag == 0 ) setRegister(0, v); /* result is set to 0 */
+ break;
+
+ case EIT_IDEBUG: /* debug abort instruction */
+ case EIT_DDEBUG: /* debug abort data */
+ if ( procBreak(bpflg, &cmd) > 0 ) {
+ procCommand(cmd, 0);
+ }
+ break;
+
+ default: /* unsupported instruction exception, interrupt, or traps */
+ if ( procEIT(vec) == 0 ) {
+ stopTrace(); /* stop tracing */
+ procCommand(NULL, 0); /* command processing */
+ }
+ }
+
+ /* set breakpoint */
+ setupBreak();
+
+ /* monitor exit processing (flushing cache, etc.) */
+ leaveMonitor(getCP15(1, 0));
+
+ /* restore task mode */
+ SCInfo.taskmode = save_taskmode;
+
+ return; /* returning leads to user program execution */
+}
diff --git a/tkernel_source/monitor/hwdepend/tef_em1d/build/Makefile b/tkernel_source/monitor/hwdepend/tef_em1d/build/Makefile
deleted file mode 100644
index 9315486..0000000
--- a/tkernel_source/monitor/hwdepend/tef_em1d/build/Makefile
+++ /dev/null
@@ -1,77 +0,0 @@
-#
-# ----------------------------------------------------------------------
-# T-Kernel 2.0 Software Package
-#
-# Copyright 2011 by Ken Sakamura.
-# This software is distributed under the latest version of T-License 2.x.
-# ----------------------------------------------------------------------
-#
-# Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
-# Modified by T-Engine Forum at 2012/11/07.
-# Modified by T-Engine Forum at 2013/02/20.
-# Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
-#
-# ----------------------------------------------------------------------
-#
-
-# T-Monitor : hwdepend (em1d)
-
-MACHINE = em1d
-TETYPE = tef
-
-SRC_SYSDEP = eitproc.c cpuctrl.c misc.c \
- eitent.S reset.S system.c waitusec.c config.c \
- cpuctrl2.S memattr.S
-
-# ----------------------------------------------------------------------------
-
-DEPS = Dependencies
-DEPENDENCIES_OUTPUT := $(DEPS)
-
-include $(BD)/etc/makerules
-
-TMONITOR_INSTALLDIR = $(BD)/monitor/bin/$(TETYPE)_$(MACHINE)
-
-HEADER = $(BD)/include $(BD)/monitor/include
-
-# ----------------------------------------------------------------------------
-
-TARGET = hwdepend
-
-S = ../src
-
-VPATH = $(S)
-HEADER += $(S)
-
-SRC = startup.c hwinfo.c sio.c diskio.c
-SRC += $(SRC_SYSDEP)
-
-OBJ = $(addsuffix .o, $(basename $(SRC)))
-
-CFLAGS += $(CFLAGS_WARNING)
-
-# ----------------------------------------------------------------------------
-
-.PHONY: all clean install
-
-ALL = $(TARGET).o
-
-all: $(ALL)
-
-$(TARGET).o: $(OBJ)
- $(LINK_R.o) $^ $(OUTPUT_OPTION)
-
-clean:
- $(RM) $(OBJ) $(ALL) $(DEPS)
-
-install: $(addprefix $(TMONITOR_INSTALLDIR)/, $(ALL))
-
-$(TMONITOR_INSTALLDIR)/%: %
- $(BD)/etc/backup_copy -t -d !OLD $< $(TMONITOR_INSTALLDIR)
-
-ifdef DEPENDENCIES_OUTPUT
- $(DEPS): ; touch $(DEPS)
-else
- $(DEPS): $(SRC) ; $(MAKEDEPS) $@ $?
-endif
--include $(DEPS)
diff --git a/tkernel_source/monitor/hwdepend/tef_em1d/src/config.c b/tkernel_source/monitor/hwdepend/tef_em1d/src/config.c
deleted file mode 100644
index d6fda24..0000000
--- a/tkernel_source/monitor/hwdepend/tef_em1d/src/config.c
+++ /dev/null
@@ -1,669 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by T-Engine Forum at 2011/09/08.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * config.c
- *
- * system-related processing / system configuration information
- *
- * target: T-Engine/EM1D-512
- */
-
-#include "sysdepend.h"
-#include <arm/em1d512.h>
-
-/* used device driver */
-IMPORT ER initSIO_ns16550(SIOCB *, const CFGSIO *, W speed);
-IMPORT ER initMemDisk(DISKCB *, const CFGDISK *);
-
-/* memory region definition */
-EXPORT MEMSEG MemSeg[] = {
- /* Bank1/2/3 */
- {0x10000000, 0x30000000, MSA_IO, PGA_RW|PGA_D |PGA_S|PGA_XN},
- /* DDR2 SDRAM, 64Mbyte */
- {0x30000000, 0x40000000, MSA_RAM, PGA_RW|PGA_C},
- /* EM1 internal device (1) */
- {0x40000000, 0x70000000, MSA_IO, PGA_RW|PGA_D |PGA_S|PGA_XN},
- /* Bank0 */
- {0x70000000, 0x72000000, MSA_FROM, PGA_RO|PGA_C |0x90000000},
- /* EM1 internal SRAM */
- {0xa0000000, 0xb0000000, MSA_SRAM, PGA_RW|PGA_NC},
- /* EM1 internal device (2) */
- {0xb0000000, 0xd0000000, MSA_IO, PGA_RW|PGA_D |PGA_S|PGA_XN},
- /* EM1 internal Boot ROM */
- {0xf0000000, 0xffffffff, MSA_ROM, PGA_RO|PGA_NC},
-
- {0x70000000, 0x70020000, MSA_MON, 0},
- {0x70030000, 0x72000000, MSA_RDA, 0},
- {0x30006000, 0x34000000, MSA_OS, 0},
-};
-
-EXPORT W N_MemSeg = sizeof(MemSeg) / sizeof(MEMSEG);
-
-/* unused memory region definition */
-EXPORT MEMSEG NoMemSeg[] = {
- {0x00000000, 0x10000000, 0, 0},
- {0x72000000, 0xa0000000, 0, 0},
- {0xd0000000, 0xf0000000, 0, 0},
-};
-
-EXPORT W N_NoMemSeg = sizeof(NoMemSeg) / sizeof(MEMSEG);
-
-/*
- * serial port configuration definition
- * list in the order of port number
- */
-EXPORT const CFGSIO ConfigSIO[] = {
- {initSIO_ns16550, 0},
-};
-
-EXPORT const W N_ConfigSIO = sizeof(ConfigSIO) / sizeof(CFGSIO);
-
-
-/*
- * disk drive configuration definition
- * list in the order of port number
- */
-EXPORT const CFGDISK ConfigDisk[] = {
- {"rda", DA_RONLY, initMemDisk, 0}, /* FlashROM */
-};
-
-EXPORT const W N_ConfigDisk = sizeof(ConfigDisk) / sizeof(CFGDISK);
-
-/* boot information */
-EXPORT const UH BootSignature = 0xe382; /* signature */
-EXPORT UB * const PBootAddr = (UB *)0x30200000; /* primary boot loader address */
-
-/* ------------------------------------------------------------------------ */
-
-#define IICC_IICE (1 << 7)
-#define IICC_WREL (1 << 5)
-#define IICC_WTIM (1 << 3)
-#define IICC_ACKE (1 << 2)
-#define IICC_STT (1 << 1)
-#define IICC_SPT (1 << 0)
-
-#define IICCL_SMC (1 << 3)
-#define IICCL_DFC (1 << 2)
-
-#define IICSE_MSTS (1 << 15)
-#define IICSE_ALD (1 << 14)
-#define IICSE_ACKD (1 << 10)
-#define IICSE_SPD (1 << 8)
-
-#define IICF_IICBSY (1 << 6)
-#define IICF_STCEN (1 << 1)
-#define IICF_IICRSV (1 << 0)
-
-#define IIC_TOPDATA (1 << 11)
-#define IIC_LASTDATA (1 << 10)
-
-#define TIMEOUT 1000000 /* microsec */
-
-#define IIC2_IRQ 39
-#define IRQbit(x) (1 << ((x) % 32))
-
-/* wait for register state information */
-LOCAL ER wait_state(UW addr, UW mask, UW value)
-{
- W i;
-
- for (i = TIMEOUT; i > 0; i--) {
- waitUsec(1);
- if ((in_w(addr) & mask) == value) break;
- }
-
- return i ? E_OK : E_TMOUT;
-}
-
-/* interrupt Raw status / clear */
-LOCAL void clear_int(void)
-{
- out_w(IT0_IIR, IRQbit(IIC2_IRQ)); /* IRQ39 clear */
- return;
-}
-
-/* interrupt Raw status / useable */
-LOCAL void setup_int(void)
-{
- out_w(IT_PINV_CLR1, IRQbit(IIC2_IRQ));
- out_w(IT0_IENS1, IRQbit(IIC2_IRQ));
- clear_int();
- return;
-}
-
-/* wait for interrupt Raw status */
-LOCAL ER wait_int(void)
-{
- ER er;
-
- er = wait_state(IT0_RAW1, IRQbit(IIC2_IRQ), IRQbit(IIC2_IRQ));
- clear_int();
-
- return er;
-}
-
-/* start / restart */
-LOCAL ER send_start(UB addr)
-{
- ER er;
- UW sts;
-
- /* generate start condition */
- out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) & ~IICC_ACKE);
- out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_STT);
-
- /* wait for reserving a master */
- er = wait_state(IIC_IICSE(IIC2), IICSE_MSTS, IICSE_MSTS);
- if (er < E_OK) goto fin0;
-
- /* slave address / communication mode transmission */
- out_w(IIC_IIC(IIC2), addr);
- er = wait_int();
- if (er < E_OK) goto fin0;
-
- /* error check */
- sts = in_w(IIC_IICSE(IIC2));
- if ((sts & IICSE_ALD) || !(sts & IICSE_ACKD)) {
- er = E_IO;
- goto fin0;
- }
-
- er = E_OK;
-fin0:
- return er;
-}
-
-/* stop */
-LOCAL ER send_stop(void)
-{
- ER er;
-
- /* generate stop condition */
- out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_SPT);
-
- /* wait for sending STOP bit(s) */
- er = wait_state(IIC_IICSE(IIC2), IICSE_SPD, IICSE_SPD);
-
- return er;
-}
-
-/* data transmission */
-LOCAL ER send_data(UB data)
-{
- ER er;
- UW sts;
-
- /* data transmission */
- out_w(IIC_IIC(IIC2), data);
- er = wait_int();
- if (er < E_OK) goto fin0;
-
- /* NAK check */
- sts = in_w(IIC_IICSE(IIC2));
- if (!(sts & IICSE_ACKD)) {
- er = E_IO;
- goto fin0;
- }
-
- er = E_OK;
-fin0:
- return er;
-}
-
-/* data receive */
-LOCAL W recv_data(W attr)
-{
- W er;
-
- /* when the first data is received, switch to receive mode */
- if (attr & IIC_TOPDATA) {
- out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) & ~IICC_WTIM);
- out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_ACKE);
- }
-
- /* instruct the reception of data */
- out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_WREL);
- er = wait_int();
- if (er < E_OK) goto fin0;
-
- /* read data */
- er = in_w(IIC_IIC(IIC2)) & 0xff;
-fin0:
- /* when an error occurs, or the last byte is seen, then perform the post processing */
- if ((attr & IIC_LASTDATA) || er < E_OK) {
- out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_WTIM);
- out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) & ~IICC_ACKE);
- out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_WREL);
- wait_int();
- }
-
- return er;
-}
-
-/* start IIC send/receive */
-LOCAL ER iic_start(void)
-{
- ER er;
-
- /* initialization default */
- out_w(IIC_IICC(IIC2), 0); /* stop completely */
- out_w(IIC_IICCL(IIC2), IICCL_SMC | IICCL_DFC); /* fast mode + filter */
- out_w(IIC_IICF(IIC2), IICF_STCEN | IICF_IICRSV);/* forcibly start transmission */
- out_w(IIC_IICC(IIC2), IICC_IICE | IICC_WTIM); /* IIC mode, 9bit mode */
- clear_int();
-
- /* wait for bus to become available (since there is only one master, the bus is supposed to be unoccupied) */
- er = wait_state(IIC_IICF(IIC2), IICF_IICBSY, 0);
-
- return er;
-}
-
-/* stop IIC send/receive */
-LOCAL void iic_finish(void)
-{
- out_w(IIC_IICC(IIC2), 0); /* stop completely */
- return;
-}
-
-/* read IIC-GPIO */
-LOCAL W IICGPIORead(W addr)
-{
- W dat;
-
- setup_int();
-
- iic_start();
- send_start(addr);
- dat = recv_data(IIC_TOPDATA | IIC_LASTDATA);
- send_stop();
- iic_finish();
-
- clear_int();
-
- return dat;
-}
-
-/* IIC-GPIO write */
-LOCAL void IICGPIOWrite(W addr, W dat)
-{
- setup_int();
-
- iic_start();
- send_start(addr);
- send_data(dat);
- send_stop();
- iic_finish();
-
- clear_int();
-
- return;
-}
-
-/* ------------------------------------------------------------------------ */
-
-IMPORT W pmicRead(W reg);
-IMPORT W pmicWrite(W reg, W dat);
-#define pmicDelay(x) waitUsec(4) /* about 16msec */
-#define USBPowerOn 0xe0 /* GPIO13(OD), High * power is supplied to A connector only */
-#define USBPowerOff 0xe0 /* GPIO13(OD), High */
-
-/* obtain DipSw status */
-EXPORT UW DipSwStatus(void)
-{
- UW d;
-
- /* read data from read port */
- d = IICGPIORead(0xd9);
-
- /* unnecessary bits are masked and then invert logic. */
- d = (d ^ SW_MON) & SW_MON;
-
- /* check abort switch */
- if (in_w(GIO_I(GIO_L)) & 0x00000100) d |= SW_ABT;
-
- return d;
-}
-
-/* USB power control */
-EXPORT void usbPower(BOOL power)
-{
- pmicWrite(27, (pmicRead(27) & 0x0f) |
- (power ? USBPowerOn : USBPowerOff));
- pmicDelay();
-}
-
-/* power off */
-EXPORT void powerOff(void)
-{
- W i;
-
- for (i = 10; i < 14; i++) pmicWrite(i, 0xff); /* IRQ_MASK_A-D (mask) */
- pmicDelay();
-
- for (i = 5 ; i < 9; i++) pmicWrite(i, 0xff); /* EVENT_A-D (clear) */
- pmicDelay();
-
- while (1) {
- pmicWrite(15, 0x60); /* DEEP_SLEEP */
- pmicDelay();
- }
-}
-
-/* reset start*/
-EXPORT void resetStart(void)
-{
- while (1) {
- /* reset */
- pmicWrite(15, 0xac); /* SHUTDOWN */
- pmicDelay();
- }
-}
-
-/* initialize hardware peripherals (executed only during reset) */
-EXPORT void initHardware(void)
-{
- /* enable abort switch interrupt */
- out_w(GIO_IDT1(GIO_L), 0x00000008); /* asynchronous leading-edge high interrupt */
- out_w(GIO_IIR(GIO_L), 0x00000100);
- out_w(GIO_IIA(GIO_L), 0x00000100);
- out_w(GIO_IEN(GIO_L), 0x00000100);
-
- return;
-}
-
-/* LED on/off */
-EXPORT void cpuLED(UW v)
-{
- UB m, d, r, c;
-
- m = ~((v >> 16) | 0xf0); /* mask (0:unmodified 1:modify) */
- d = ~((v >> 0) | 0xf0); /* set value (0:on 1:off) */
- r = IICGPIORead(0xb9);
- c = (r ^ d) & m; /* modify flag (0:unmodified 1:modify) */
- IICGPIOWrite(0xb8, r ^ c);
-}
-
-/*
- * machine-dependent interrupt processing
- * vec interrupt vector number
- * return value 0: unsupported target
- * 1: for the supported target, processing was performed. (monitor still continues)
- * 2: for the supported target, proceesing was performed (interrupt handler is exited)
- */
-EXPORT W procHwInt(UW vec)
-{
- /* only abort switch (GPIO(P8)) is supported */
- if (vec != EIT_GPIO(8)) return 0;
-
- /* clear interrupt */
- out_w(GIO_IIR(GIO_L), 0x00000100);
-
- DSP_S("Abort Switch (SW1) Pressed");
- return 1;
-}
-
-/* ------------------------------------------------------------------------ */
-
-/*
- configure GPIO pin multiplexer
-
- * : used functions
-
- pin name function 0(00) function1(01) function2(10) function3(11)
- GIO_P0 GIO_P0*
- GIO_P1 GIO_P1* USB_WAKEUP USB_PWR_FAULT
- GIO_P2 GIO_P2*
- GIO_P3 GIO_P3*
- GIO_P4 GIO_P4* NAND_RB1
- GIO_P5 GIO_P5 NAND_RB2 CAM_SCLK*
- GIO_P6 GIO_P6* NAND_RB3
- GIO_P7 GIO_P7* NAND_CE0
- GIO_P8 GIO_P8* NAND_CE1
- GIO_P9 GIO_P9* NAND_CE2
- GIO_P10 GIO_P10* NAND_CE3
- AB0_CLK GIO_P11 AB0_CLK* NTS_CLK
- AB0_AD0 GIO_P12 AB0_AD0*
- AB0_AD1 GIO_P13 AB0_AD1*
- AB0_AD2 GIO_P14 AB0_AD2*
- AB0_AD3 GIO_P15 AB0_AD3*
-
- pin name function 0(00) function1(01) function2(10) function3(11)
- AB0_AD4 GIO_P16 AB0_AD4*
- AB0_AD5 GIO_P17 AB0_AD5*
- AB0_AD6 GIO_P18 AB0_AD6*
- AB0_AD7 GIO_P19 AB0_AD7*
- AB0_AD8 GIO_P20 AB0_AD8*
- AB0_AD9 GIO_P21 AB0_AD9*
- AB0_AD10 GIO_P22 AB0_AD10*
- AB0_AD11 GIO_P23 AB0_AD11*
- AB0_AD12 GIO_P24 AB0_AD12*
- AB0_AD13 GIO_P25 AB0_AD13*
- AB0_AD14 GIO_P26 AB0_AD14*
- AB0_AD15 GIO_P27 AB0_AD15*
- AB0_A17 GIO_P28 AB0_A17*
- AB0_A18 GIO_P29 AB0_A18*
- AB0_A19 GIO_P30 AB0_A19*
- AB0_A20 GIO_P31 AB0_A20*
-
- pin name function 0(00) function1(01) function2(10) function3(11)
- AB0_A21 GIO_P32 AB0_A21*
- AB0_A22 GIO_P33 AB0_A22*
- AB0_A23 GIO_P34 AB0_A23*
- AB0_A24 GIO_P35 AB0_A24*
- AB0_A25 GIO_P36* AB0_A25
- AB0_A26 GIO_P37* AB0_A26
- AB0_ADV GIO_P38 AB0_ADV*
- AB0_RDB GIO_P39 AB0_RDB* NTS_DATA3
- AB0_WRB GIO_P40 AB0_WRB* NTS_DATA4
- AB0_WAIT GIO_P41 AB0_WAIT* NTS_DATA5
- AB0_CSB0 GIO_P42 AB0_CSB0* NTS_DATA6
- AB0_CSB1 GIO_P43 AB0_CSB1* NTS_DATA7
- AB0_CSB2 GIO_P44* AB0_CSB2 NTS_VS
- AB0_CSB3 GIO_P45 AB0_CSB3* NTS_HS
- AB0_BEN0 GIO_P46 AB0_BEN0*
- AB0_BEN1 GIO_P47 AB0_BEN1*
-
- pin name function 0(00) function1(01) function2(10) function3(11)
- SP0_CS1 GIO_P48 SP0_CS1*
- SP0_CS2 GIO_P49 SP0_CS2*
- LCD_PXCLK GIO_P50 LCD_PXCLK*
- LCD_R0 GIO_P51 LCD_R0*
- LCD_R1 GIO_P52 LCD_R1*
- LCD_R2 GIO_P53 LCD_R2*
- LCD_R3 GIO_P54 LCD_R3*
- LCD_R4 GIO_P55 LCD_R4*
- LCD_R5 GIO_P56 LCD_R5*
- LCD_G0 GIO_P57 LCD_G0*
- LCD_G1 GIO_P58 LCD_G1*
- LCD_G2 GIO_P59 LCD_G2*
- LCD_G3 GIO_P60 LCD_G3*
- LCD_G4 GIO_P61 LCD_G4*
- LCD_G5 GIO_P62 LCD_G5*
- LCD_B0 GIO_P63 LCD_B0*
-
- pin name function 0(00) function1(01) function2(10) function3(11)
- LCD_B1 GIO_P64 LCD_B1*
- LCD_B2 GIO_P65 LCD_B2*
- LCD_B3 GIO_P66 LCD_B3*
- LCD_B4 GIO_P67 LCD_B4*
- LCD_B5 GIO_P68 LCD_B5*
- LCD_HSYNC GIO_P69 LCD_HSYNC*
- LCD_VSYNC GIO_P70 LCD_VSYNC*
- LCD_ENABLE GIO_P71 LCD_ENABLE*
- NTS_CLK GIO_P72* NTS_CLK PM1_CLK
- NTS_VS GIO_P73* NTS_VS SP1_CLK
- NTS_HS GIO_P74* NTS_HS SP1_SI
- NTS_DATA0 GIO_P75 NTS_DATA0 SP1_SO CAM_YUV0*
- NTS_DATA1 GIO_P76 NTS_DATA1 SP1_CS0 CAM_YUV1*
- NTS_DATA2 GIO_P77 NTS_DATA2 SP1_CS1 CAM_YUV2*
- NTS_DATA3 GIO_P78 NTS_DATA3 SP1_CS2 CAM_YUV3*
- NTS_DATA4 GIO_P79 NTS_DATA4 SP1_CS3 CAM_YUV4*
-
- pin name function 0(00) function1(01) function2(10) function3(11)
- NTS_DATA5 GIO_P80* NTS_DATA5 SP1_CS4 PM1_SEN
- NTS_DATA6 GIO_P81* NTS_DATA6 SP1_CS5 PM1_SI
- NTS_DATA7 GIO_P82* NTS_DATA7 PM1_SO
- IIC_SCL GIO_P83 IIC_SCL*
- IIC_SDA GIO_P84 IIC_SDA*
- URT0_CTSB GIO_P85 URT0_CTSB URT1_SRIN*
- URT0_RTSB GIO_P86 URT0_RTSB URT1_SOUT*
- PM0_SI GIO_P87 PM0_SI*
- SD0_DATA1 GIO_P88 SD0_DATA1*
- SD0_DATA2 GIO_P89 SD0_DATA2*
- SD0_DATA3 GIO_P90 SD0_DATA3*
- SD0_CKI GIO_P91 SD0_CKI*
- SD1_CKI GIO_P92 SD1_CKI CAM_CLKI*
- SD2_CKI GIO_P93 SD2_CKI* NAND_OE
- PWM0 GIO_P94* PWM0
- PWM1 GIO_P95* PWM1
-
- pin name function 0(00) function1(01) function2(10) function3(11)
- USB_CLK GIO_P96 USB_CLK*
- USB_DATA0 GIO_P97 USB_DATA0*
- USB_DATA1 GIO_P98 USB_DATA1*
- USB_DATA2 GIO_P99 USB_DATA2*
- USB_DATA3 GIO_P100 USB_DATA3*
- USB_DATA4 GIO_P101 USB_DATA4*
- USB_DATA5 GIO_P102 USB_DATA5*
- USB_DATA6 GIO_P103 USB_DATA6*
- USB_DATA7 GIO_P104 USB_DATA7*
- USB_DIR GIO_P105 USB_DIR*
- USB_STP GIO_P106 USB_STP*
- USB_NXT GIO_P107 USB_NXT*
- URT2_SRIN GIO_P108 URT2_SRIN*
- URT2_SOUT GIO_P109 URT2_SOUT*
- URT2_CTSB GIO_P110 URT2_CTSB*
- URT2_RTSB GIO_P111 URT2_RTSB*
-
- pin name function 0(00) function1(01) function2(10) function3(11)
- SD2_CKO GIO_P112 SD2_CKO* NAND_D2
- SD2_CMD GIO_P113 SD2_CMD* NAND_D3
- SD2_DATA0 GIO_P114 SD2_DATA0* NAND_D4
- SD2_DATA1 GIO_P115 SD2_DATA1* NAND_D5
- SD2_DATA2 GIO_P116 SD2_DATA2* NAND_D6
- SD2_DATA3 GIO_P117 SD2_DATA3* NAND_D7
-*/
-EXPORT const UW GPIOConfig[] __attribute__((section(".startup"))) = {
- CHG_PINSEL_G(0),
- 0x55400C00, /* AB0_CLK,AB0_AD3-0,CAM_SCLK */
- CHG_PINSEL_G(16),
- 0x55555555, /* AB0_AD15-4,AB0_A20-17 */
- CHG_PINSEL_G(32),
- 0x54555055, /* AB0_BEN1-0,AB0_CSB3,AB0_CSB1-0, */
- /* AB0_WAIT,AB0_WRB,AB0_RDB,AB0_ADV, */
- /* AB0_A24-21 */
-
- CHG_CTRL_AB0_BOOT, /* AB0(AsyncBus0) pin: */
- 0x00000001, /* configured by PINSEL */
-
- CHG_PINSEL_G(48),
- 0x55555555, /* LCD,SP0_CS2-1 */
- CHG_PINSEL_G(64),
- 0xffc05555, /* CAM_YUV4-0,LCD */
- CHG_PINSEL_G(80),
- 0x06556940, /* SD2_CKI,CAM_CLKI,SD0_CKI,SD0_DATA3-1, */
- /* PM0,URT1,IIC */
- CHG_PINSEL_G(96),
- 0x55555555, /* URT2,USB */
- CHG_PINSEL_G(112),
- 0x00000555, /* SD2 */
- CHG_PINSEL_SP0,
- 0x00000000,
- CHG_PINSEL_DTV,
- 0x00000001,
- CHG_PINSEL_SD0,
- 0x00000000,
- CHG_PINSEL_SD1,
- 0x00000002,
- CHG_PINSEL_IIC2,
- 0x00000000,
- CHG_PULL_G(0),
- 0x55055005, /* P7,P6,P4,P3,P0: IN, pull-up/down dis */
- CHG_PULL_G(8),
- 0x00000005, /* P8: IN, pull-up/down dis */
- CHG_PULL_G(16),
- 0x00000000, /* (default) */
- CHG_PULL_G(24),
- 0x00000000, /* (default) */
- CHG_PULL_G(32),
- 0x00550000, /* P37,36: IN, pull-up/down dis */
- CHG_PULL_G(40),
- 0x00050000, /* P44: IN, pull-up/down dis */
- CHG_PULL_G(48),
- 0x11111111, /* (default) */
- CHG_PULL_G(56),
- 0x11111111, /* (default) */
- CHG_PULL_G(64),
- 0x11111111, /* (default) */
- CHG_PULL_G(72),
- 0x00000005, /* P72: IN, pull-up/down dis */
- CHG_PULL_G(80),
- 0x00400050, /* P81: IN, pull-up/down dis */
- /* URT1_SRIN: IN, pull-down */
- CHG_PULL_G(88),
- 0x55000444, /* P95,94: IN, pull-up/down dis */
- /* SD0_DATA3-1: IN, pull-down */
- CHG_PULL_G(96),
- 0x44444444, /* USB signals: IN, pull-down */
- CHG_PULL_G(104),
- 0x04044444, /* USB signals: IN, pull-down */
- /* URT2_CTSB,URT2_SRIN: IN, pull-down */
- CHG_PULL_G(112),
- 0x00000000, /* (default) */
- CHG_PULL_G(120),
- 0x00000000, /* (default) */
-
- CHG_PULL(0),
- 0x50000004, /* URT0_SRIN: IN, pull-up/down dis */
- /* DEBUG_EN: IN, pull-down */
- CHG_PULL(1),
- 0x15110600, /* SP0_SO: OUT, pull-up/down dis */
- /* SP0_SI: IN, pull-up/down dis */
- /* SP0_CS: OUT, pull-up/down dis */
- /* SP0_CK: OUT, pull-up/down dis */
- /* JT0C: IN, pull-up */
- /* JT0B: OUT, pull-down */
- /* JT0A: OUT, pull-down */
- CHG_PULL(2),
- 0x60000661, /* PM0_SEN: IN, pull-up */
- /* SD0_DAT: IN, pull-up */
- /* SD1_CMD: IN, pull-up */
- /* SD0_CLK: OUT, pull-up/down dis */
- CHG_PULL(3),
- 0x00000000, /* (default) */
-
- GIO_E0(GIO_L),
- 0x000001d9, /* P8,P7,P6,P4,P3,P0: IN */
- GIO_E1(GIO_L),
- 0x00000604, /* P10,P9,P2: OUT */
- GIO_E0(GIO_H),
- 0x00001030, /* P44,P37,P36: IN */
- GIO_E1(GIO_H),
- 0x00000000, /* (default) */
- GIO_E0(GIO_HH),
- 0xc0020100, /* P95,P94,P81,P72:IN */
- GIO_E1(GIO_HH),
- 0x00040200, /* P82,P73: OUT */
- GIO_OL(GIO_L),
- 0x06040000, /* P10,P9,P2=0 */
- GIO_OL(GIO_HH),
- 0x02000000, /* P73=0 */
- GIO_OH(GIO_HH),
- 0x00040000, /* P82=0 */
-
- 0x00000000, /* (terminate) */
- 0x00000000,
-};
diff --git a/tkernel_source/monitor/hwdepend/tef_em1d/src/cpuctrl.c b/tkernel_source/monitor/hwdepend/tef_em1d/src/cpuctrl.c
deleted file mode 100644
index 2580cef..0000000
--- a/tkernel_source/monitor/hwdepend/tef_em1d/src/cpuctrl.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * cpuctrl.c
- *
- * ARM CPU control
- */
-
-#include "sysdepend.h"
-
-/*
- * Location of the 1st level page table
- */
-EXPORT UW* const TopPageTable = (UW*)PAGETBL_BASE;
-
-/* ------------------------------------------------------------------------ */
-/*
- * cache control
- * acts on the whole address space.
- */
-
-/*
- * turn on cache
- */
-EXPORT void EnableCache( void )
-{
- setCacheMMU(ENB_CACHEMMU);
-}
-
-/*
- * turn off cache
- */
-EXPORT void DisableCache( void )
-{
- /* MMU can NOT be turned off with this CPU. */
- setCacheMMU(DIS_CACHEONLY);
-}
-
-/* ------------------------------------------------------------------------ */
-/*
- * processing on monitor entry
- */
-
-/*
- * entry
- * info, return value is meaningless
- */
-EXPORT W enterMonitor( UW info )
-{
- /* cache and MMU is flushed */
- setCacheMMU(ENB_CACHEMMU);
-
- return 0;
-}
-
-/*
- * exit
- * only in the case of system control processor (CP15)
- * info is the cache and MMU mode
- * return value is meaningless
- */
-EXPORT W leaveMonitor( UW info )
-{
- /* restore cache && MMU to the original state. */
- setCacheMMU(info);
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------ */
diff --git a/tkernel_source/monitor/hwdepend/tef_em1d/src/cpuctrl2.S b/tkernel_source/monitor/hwdepend/tef_em1d/src/cpuctrl2.S
deleted file mode 100644
index 15745de..0000000
--- a/tkernel_source/monitor/hwdepend/tef_em1d/src/cpuctrl2.S
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * cpuctrl2.S
- *
- * ARM CPU control
- *
- * Assume that system control processor (CP15) exists.
- */
-#define _in_asm_source_
-
-#include <machine.h>
-#include <tk/sysdef.h>
-
-#define DCACHE_NWAY 4 /* N as in the number of N-way data cache */
-#define DCACHE_NWAY_SHIFT 30
-#define DCACHE_NSEG 256 /* number of segments of data cache */
-#define DCACHE_NSEG_SHIFT 5
-
-/*
- * flush the entire cache (write back and then invalidate)
- * void FlushCache( void )
- */
- .text
- .balign 4
- .globl Csym(FlushCache)
- .type Csym(FlushCache), %function
-Csym(FlushCache):
- ldr r2, =DCACHE_NWAY-1
- l_flush_dcache1:
- ldr r3, =DCACHE_NSEG-1
- l_flush_dcache2:
- mov ip, r2, lsl #DCACHE_NWAY_SHIFT
- orr ip, ip, r3, lsl #DCACHE_NSEG_SHIFT
- mcr p15, 0, ip, cr7, c14, 2 // data cache is written back,
- subs r3, r3, #1 // and is invalidated
- bpl l_flush_dcache2
- subs r2, r2, #1
- bpl l_flush_dcache1
-
- ldr ip, =0
- mcr p15, 0, ip, cr7, c7, 0 // Invalidate I/D-Cache
- mcr p15, 0, ip, cr7, c10, 4 // Drain Write Buffer
-
- bx lr
-
-/*
- * cache and MMU control
- * void setCacheMMU( UW cp15r1 )
- */
- .text
- .balign 4
- .globl Csym(setCacheMMU)
- .type Csym(setCacheMMU), %function
-Csym(setCacheMMU):
- stmfd sp!, {r4, lr} // save registers
- mov r4, r0 // save argument
-
- /* flush cache */
- bl Csym(FlushCache)
-
- /* TLB flush */
- ldr ip, =0
- mcr p15, 0, ip, cr8, c7, 0 // Invalidate I/D-TLB
-
- /* set new r1 for CP15 */
- mrc p15, 0, r2, cr1, cr0, 0
- ldr r3, =0x3307 // V,I,R,S,C,A,M (B = 0)
- and r0, r4, r3
- mvn r3, r3 // clear old V,I,R,S,C,A,M
- and r2, r2, r3
- orr r0, r0, r2
- mcr p15, 0, r0, cr1, cr0, 0
- nop
- nop
-
- ldmfd sp!, {r4, lr} // restore registers
- bx lr
diff --git a/tkernel_source/monitor/hwdepend/tef_em1d/src/diskio.c b/tkernel_source/monitor/hwdepend/tef_em1d/src/diskio.c
deleted file mode 100644
index aa730c4..0000000
--- a/tkernel_source/monitor/hwdepend/tef_em1d/src/diskio.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * diskio.c
- *
- * Disk I/O
- */
-
-#include "hwdepend.h"
-#include <device/disk.h>
-
-/*
- * misaligned data is read as a little-endian data
- */
-#define GMW(vp) ( (UW)((UB*)vp)[0] \
- | (UW)((UB*)vp)[1] << 8 \
- | (UW)((UB*)vp)[2] << 16 \
- | (UW)((UB*)vp)[3] << 24 )
-#define GMH(vp) ( (UH)((UB*)vp)[0] \
- | (UH)((UB*)vp)[1] << 8 )
-
-/*
- * control block for a disk drive
- * When their number is smaller than the number of disks,
- * already used block is re-used in place of missing block after it is cleared
- */
-#define N_DISKCB 3
-LOCAL struct dcblist {
- const CFGDISK *cfg; /* target device */
- DISKCB dcb;
-} dcbList[N_DISKCB];
-
-LOCAL W last_dcb = 0; /* the last allocated number from dcbList */
-
-/*
- * allocating a disk control block
- */
-LOCAL DISKCB* getDISKCB( const CFGDISK *cfg )
-{
- W i, n;
- DISKCB *dcb;
-
- /* searching for disk drive control block */
- n = last_dcb;
- do {
- i = n;
- if ( dcbList[i].cfg == cfg ) break;
- if ( ++n >= N_DISKCB ) n = 0;
- } while ( n != last_dcb );
- dcb = &dcbList[i].dcb;
- last_dcb = i;
- if ( dcbList[i].cfg != cfg ) {
- /* re-use after clear */
- memset(dcb, 0, sizeof(DISKCB));
- dcbList[i].cfg = cfg;
- }
-
- return dcb;
-}
-
-/*
- * search for a device
- * return the configuration information of device (indicated by devnm) to cfg_p.
- * return value is a partition number or error.
- */
-LOCAL W searchDevice( const UB *devnm, const CFGDISK **cfg_p )
-{
- UB name[L_DEVNM + 1];
- W i, pno, c;
-
- /* checking device name */
- strncpy(name, devnm, L_DEVNM + 1);
- if ( name[L_DEVNM] != '\0' ) return E_PAR;
- i = strlen(name);
- if ( i <= 0 ) return E_PAR;
-
- /* check for logical device (partition: 0-3) */
- pno = 0;
- c = name[i - 1];
- if ( c >= '0' && c <='3' ) {
- if ( --i <= 0 ) return E_PAR;
- name[i] = '\0'; /* partition number is removed */
- pno = c - '0' + 1; /* partition number (1 - ) */
- }
-
- /* search for a device */
- for ( i = 0; i < N_ConfigDisk; i++ ) {
- if ( strncmp(name, ConfigDisk[i].name, L_DEVNM) == 0 ) break;
- }
- if ( i >= N_ConfigDisk ) return E_NOEXS;
-
- *cfg_p = &ConfigDisk[i];
- return pno;
-}
-
-/*
- * obtain partition information
- */
-LOCAL ER readPart( DISKCB *dcb )
-{
- DiskBlock0 buf;
- W i, pno;
- ER err;
-
- dcb->boot = 0;
-
- /* if an unexpected disk block size is seen, raise an error */
- if ( dcb->blksz != sizeof(buf) ) return E_NOSPT;
-
- /* read master boot record */
- err = (*dcb->rwdisk)(dcb, 0, 1, &buf, FALSE);
- if ( err < E_OK ) return err;
-
- /* check the signature in the boot block */
- if ( GMH(&buf.signature) != 0xaa55 ) return E_OK; /* no partition */
-
- /* obtain partition information */
- for ( i = 0; i < MAX_PARTITION; i++ ) {
- pno = i + 1;
- dcb->part[pno].sblk = GMW(buf.part[i].StartBlock);
- dcb->part[pno].nblk = GMW(buf.part[i].BlockCnt);
-
- if ( buf.part[i].BootInd == 0x80
- && dcb->part[pno].nblk > 0
- && dcb->boot == 0 ) dcb->boot = pno;
- }
-
- return E_OK;
-}
-
-/*
- * open disk (obtain disk drive control block)
- * open a device indicated by `devnm', and return the disk information in `dcb'.
- * devnm can specify a device name with partition number.
- * return the partition number specified by devnm.
- * return value 0 : entire disks
- * 1 - : partition number
- * < 0 : error
- */
-EXPORT W openDisk( const UB *devnm, DISKCB **dcb_p )
-{
- const CFGDISK *cfg;
- DISKCB *dcb;
- W pno;
- ER err;
-
- /* search for a device */
- pno = searchDevice(devnm, &cfg);
- if ( pno < E_OK ) return pno;
-
- /* allocating a disk control block */
- dcb = getDISKCB(cfg);
-
- /* initialize disk */
- err = (*cfg->initdisk)(dcb, cfg);
- if ( err < E_OK ) return err;
- if ( dcb->blksz == 0 ) return E_NOMDA;
-
- if ( dcb->boot == 0xff ) {
- /* read the partition information */
- err = readPart(dcb);
- if ( err < E_OK ) return err;
- }
-
- *dcb_p = dcb;
- return pno;
-}
-
-/*
- * disk access
- * devnm device name (possibly with the partition number)
- * blk start block number
- * if device name has a partition number, then the block number in that partition
- * if there is no partition number in the disk anme, the block number in the entire disk
- * nblk number of blocks
- * buf buffer (* )
- * wrt FALSE : read
- * TRUE : write
- * return value error code
- * argument marked with (* ) may be an address specified from external sources.
- */
-EXPORT ER rwDisk( const UB *devnm, W blk, W nblk, void *buf, BOOL wrt )
-{
- DISKCB *dcb;
- W pno, nb;
- ER err;
-
- /* initialize disk */
- pno = openDisk(devnm, &dcb);
- if ( pno < E_OK ) return pno;
-
- nb = dcb->part[pno].nblk;
-
- /* range check of the block number */
- if ( blk < 0 || blk >= nb
- || nblk <= 0 || nblk > nb - blk ) return E_PAR;
-
- /* convert the relative block number in a partiton to a block number in the entire disk */
- blk += dcb->part[pno].sblk;
-
- /* read from, or write to disk */
- err = (*dcb->rwdisk)(dcb, blk, nblk, buf, wrt);
- if ( err < E_OK ) return err;
-
- return E_OK;
-}
-
-/*
- * obtain disk information
- * devnm device name (possibly with the partition number)
- * blksz return block size (* )
- * tblks return the number of all blocks (* )
- * return value error code
- * if there is a partition number to the device name, return the specific information to that partition.
- * argument marked with (* ) may be an address specified from external sources.
- */
-EXPORT ER infoDisk( const UB *devnm, W *blksz, W *tblks )
-{
- DISKCB *dcb;
- W pno, buf, n;
-
- /* initialize disk */
- pno = openDisk(devnm, &dcb);
- if ( pno < E_OK ) return pno;
-
- /* obtain disk information
- * since there are addresses specified from external source, use writeMem()
- */
- buf = dcb->part[pno].nblk;
- n = writeMem((UW)tblks, &buf, sizeof(W), sizeof(W));
- if ( n < sizeof(W) ) return E_MACV;
-
- buf = dcb->blksz;
- n = writeMem((UW)blksz, &buf, sizeof(W), sizeof(W));
- if ( n < sizeof(W) ) return E_MACV;
-
- return E_OK;
-}
diff --git a/tkernel_source/monitor/hwdepend/tef_em1d/src/eitent.S b/tkernel_source/monitor/hwdepend/tef_em1d/src/eitent.S
deleted file mode 100644
index c37c818..0000000
--- a/tkernel_source/monitor/hwdepend/tef_em1d/src/eitent.S
+++ /dev/null
@@ -1,313 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * eitentry.S
- *
- * EM1D512 (ARM1176JZF-S) exception branch handling
- */
-
-#define _in_asm_source_
-
-#include <machine.h>
-#include <tk/sysdef.h>
-#include <arm/em1d512.h>
-#include <sys/sysinfo.h>
-
-#define base(n) ( (n) & 0xfffff000 )
-#define offs(n) ( (n) & 0x00000fff )
-
-// see <sys/sysdepend/tef_em1d/sysinfo_depend.h>
-#define N_INTVEC 256
-
-/*
- * EIT entry
- */
-
- .section EITBRA, "ax"
- .arm
- .org 0x00000000
- b startup_entry // 00 : reset
- b undef_entry // 04 : undefined instruction exception
- b svc_entry // 08 : supervisor call (SVC)
- b iabort_entry // 0C : prefetch abort
- b dabort_entry // 10 : data abort
- nop // 14 : (reserved)
- b irq_entry // 18 : interrupt
- .org 0x0000001c // 1C : fast interrupt
-
-/*
- * fast interrupt
- * calls the handler defined at FIQ interrupt vector unconditionally.
- * no saving of registers to stack is performed.
- * the content of R12_fiq(ip) register is overwritten.
- */
-fiq_entry:
- ldr ip, =base(EIT_VECTBL)
- ldr ip, [ip, #offs(EITVEC(EIT_FIQ))]
- bx ip
-
-/*
- * interrupt
- * ACPU interrupt mask status register of Interrupt controller (AINT)
- * Judge the priority of interrupts using (IT0_MST0,1,2),
- * the highest interrupt's handler is called by jumping into it.
- * Interrupt priority is descending order of interrupt factor (INT 0-95) , and INT 95 (IRQ 95) is highest.
- * INT 0 (IRQ 0) has the lowest priority.
- * If there is no cause of the interrupt, the handler of INT 95 (IRQ95) is called.
- * +---------------+
- * sp -> |R3 |
- * |R12=ip |
- * |R14=lr | <- return address from interrupt
- * |SPSR |
- * +---------------+
- * registers upon handler invocation
- * ip = vector table address
- * lr = indeterminate
- */
-irq_entry:
- sub lr, lr, #4 // return address adjustment
- srsdb sp!, #PSR_IRQ // save registers
- stmfd sp!, {r3, ip}
-
- ldr lr, =base(AINTBase)
- ldr ip, =EITVEC(EIT_IRQ(95))
-
- ldr r3, [lr, #offs(IT0_MST2)]
- cmp r3, #0
- bne l_irq_br
-
- sub ip, ip, #32*4
- ldr r3, [lr, #offs(IT0_MST1)]
- cmp r3, #0
- bne l_irq_br
-
- sub ip, ip, #32*4
- ldr r3, [lr, #offs(IT0_MST0)]
- cmp r3, #0
- bne l_irq_br
-
- ldr ip, =EITVEC(EIT_IRQ(95))
-
- l_irq_br:
- clzne r3, r3
- ldr lr, [ip, -r3, lsl #2]!
- cmp lr, #0
- bxne lr
- b default_entry
-
-/*
- * GPIO interrupt
- * Interrupt obtained by means of input port interrupt maskable status register (GIO_MST)
- * is analyzed to check the interrupt priority, and if appropriate, the highest priority interrupt handler is entered.
- * branch and call handler.
- * interrupt priority is descending order of input port NUMBER (port 0 - port 127). port 127 has the highest priority, and
- * port 0 has the lowest priority GPIO interrupts are grouped : each group has 16 interrupts, and
- * their priorities are considered only within the context of each group.
- * if there is no cause of interupt, the handler of IRQ95 is called.
- * +---------------+
- * sp -> |R3 |
- * |R12=ip |
- * |R14=lr | <- return address from interrupt
- * |SPSR |
- * +---------------+
- * registers upon handler invocation
- * ip = vector table address
- * lr = indeterminate
- */
- .macro gio_e reg, vec
- ldr lr, =base(\reg)
- ldr r3, [lr, #offs(\reg)]
- lsls r3, r3, #16
- beq l_gio_spurious
-
- ldr ip, =\vec
- clz r3, r3
- ldr lr, [ip, -r3, lsl #2]!
- cmp lr, #0
- bxne lr
- b default_entry
- .endm
- .macro gio_o reg, vec
- ldr lr, =base(\reg)
- ldr r3, [lr, #offs(\reg)]
- lsrs ip, r3, #16
- beq l_gio_spurious
-
- ldr ip, =\vec
- clz r3, r3
- ldr lr, [ip, -r3, lsl #2]!
- cmp lr, #0
- bxne lr
- b default_entry
- .endm
-
- .globl Csym(_gio0Hdr)
- .type Csym(_gio0Hdr), %function
- .globl Csym(_gio1Hdr)
- .type Csym(_gio1Hdr), %function
- .globl Csym(_gio2Hdr)
- .type Csym(_gio2Hdr), %function
- .globl Csym(_gio3Hdr)
- .type Csym(_gio3Hdr), %function
- .globl Csym(_gio4Hdr)
- .type Csym(_gio4Hdr), %function
- .globl Csym(_gio5Hdr)
- .type Csym(_gio5Hdr), %function
- .globl Csym(_gio6Hdr)
- .type Csym(_gio6Hdr), %function
- .globl Csym(_gio7Hdr)
- .type Csym(_gio7Hdr), %function
-Csym(_gio0Hdr): gio_e GIO_MST(GIO_L), EITVEC(EIT_GPIO( 15))
-Csym(_gio1Hdr): gio_o GIO_MST(GIO_L), EITVEC(EIT_GPIO( 31))
-Csym(_gio2Hdr): gio_e GIO_MST(GIO_H), EITVEC(EIT_GPIO( 47))
-Csym(_gio3Hdr): gio_o GIO_MST(GIO_H), EITVEC(EIT_GPIO( 63))
-Csym(_gio4Hdr): gio_e GIO_MST(GIO_HH), EITVEC(EIT_GPIO( 79))
-Csym(_gio5Hdr): gio_o GIO_MST(GIO_HH), EITVEC(EIT_GPIO( 95))
-Csym(_gio6Hdr): gio_e GIO_MST(GIO_HHH), EITVEC(EIT_GPIO(111))
-Csym(_gio7Hdr): gio_o GIO_MST(GIO_HHH), EITVEC(EIT_GPIO(127))
-
- l_gio_spurious:
- ldr ip, =base(EITVEC(EIT_IRQ(95)))
- ldr lr, [ip, #offs(EITVEC(EIT_IRQ(95)))]!
- cmp lr, #0
- bxne lr
- b default_entry
-
-/*
- * undefined instruction
- * +---------------+
- * sp -> |R12=ip |
- * |R14=lr | <- the return address, i.e., the next address that follows the undefined instruction
- * |SPSR |
- * +---------------+
- * registers upon handler invocation
- * ip = vector table address
- * lr = indeterminate
- */
-undef_entry:
- srsdb sp!, #PSR_UND // save registers
- stmfd sp!, {ip}
-
- ldr ip, =base(EITVEC(EIT_UNDEF))
- ldr lr, [ip, #offs(EITVEC(EIT_UNDEF))]!
- cmp lr, #0
- bxne lr
- b default_entry
-
-/*
- * supervisor call(SVC)
- * the valid range of supervisor call number is 0-255 (N_INTVEC - 1).
- * if an out of range value is given, treat it as SVC 0, and invokes the default handler.
- * +---------------+
- * sp -> |R12=ip |
- * |R14=lr | <- return address: the address that follows the SVC instruction
- * |SPSR |
- * +---------------+
- * registers upon handler invocation
- * ip = vector table address
- * lr = indeterminate
- */
-svc_entry:
- srsdb sp!, #PSR_SVC // save registers
- stmfd sp!, {ip}
-
- mrs ip, spsr
- tst ip, #PSR_T
- ldrneh ip, [lr, #-2] // Thumb instruction
- ldreq ip, [lr, #-4] // ARM instruction
- bicne lr, ip, #0xff00
- biceq lr, ip, #0xff000000
- cmp lr, #N_INTVEC // lr = software interrupt number
- movge lr, #0
-
- ldr ip, =EIT_VECTBL
- ldr lr, [ip, lr, lsl #2]!
- cmp lr, #0
- bxne lr
- b default_entry
-
-/*
- * prefetch abort
- * in the case of debug event, debug abort (instruction) handler is called.
- * Otherwise, prefetch abort handler is called.
- * +---------------+
- * sp -> |R12=ip |
- * |R14=lr | <- return address: the address of aborted instruction
- * |SPSR |
- * +---------------+
- * registers upon handler invocation
- * ip = vector table address
- * lr = indeterminate
- */
-iabort_entry:
- sub lr, lr, #4 // return address adjustment
- srsdb sp!, #PSR_ABT // save registers
- stmfd sp!, {ip}
-
- mrc p15, 0, ip, c5, c0, 1 // IFSR
- tst ip, #0x400 // FS[4]
- and ip, ip, #0x00f // FS[3:0]
- cmpeq ip, #FSR_DebugEvent
-
- ldr ip, =base(EITVEC(EIT_IABORT))
- ldrne lr, [ip, #offs(EITVEC(EIT_IABORT))]!
- ldreq lr, [ip, #offs(EITVEC(EIT_IDEBUG))]!
- cmp lr, #0
- bxne lr
- b default_entry
-
-/*
- * data abort
- * in the case of debug event, debug abort (data) handler is called.
- * Otherwise, data abort handler is called.
- * +---------------+
- * sp -> |R12=ip |
- * |R14=lr | <- return address: the address of aborted instruction
- * |SPSR |
- * +---------------+
- * registers upon handler invocation
- * ip = vector table address
- * lr = indeterminate
- */
-dabort_entry:
- sub lr, lr, #8 // return address adjustment
- srsdb sp!, #PSR_ABT // save registers
- stmfd sp!, {ip}
-
- mrc p15, 0, ip, c5, c0, 0 // DFSR
- tst ip, #0x400 // FS[4]
- and ip, ip, #0x00f // FS[3:0]
- cmpeq ip, #FSR_DebugEvent
-
- ldr ip, =base(EITVEC(EIT_DABORT))
- ldrne lr, [ip, #offs(EITVEC(EIT_DABORT))]!
- ldreq lr, [ip, #offs(EITVEC(EIT_DDEBUG))]!
- cmp lr, #0
- bxne lr
- b default_entry
-
-/*
- * default handler
- * stack contains the details of the generated exception.
- * registers upon handler invocation
- * ip = address of the vector table for the raised exception
- * lr = indeterminate
- */
-default_entry:
- ldr lr, =base(EITVEC(EIT_DEFAULT))
- ldr lr, [lr, #offs(EITVEC(EIT_DEFAULT))]
- bx lr
-
- .pool
diff --git a/tkernel_source/monitor/hwdepend/tef_em1d/src/eitproc.c b/tkernel_source/monitor/hwdepend/tef_em1d/src/eitproc.c
deleted file mode 100644
index b109c95..0000000
--- a/tkernel_source/monitor/hwdepend/tef_em1d/src/eitproc.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * eitproc.c
- *
- * EIT processing
- */
-
-#include "sysdepend.h"
-#include <tk/sysdef.h>
-
-/*
- * vector information
- */
-typedef struct vecinfo VECINFO;
-struct vecinfo {
- UW vec; /* initial vector numer */
- B *msg; /* message */
-
- /* processing function
- * return value 1 : adjust PC by decrementing it by one instruction worth
- * 0 : PC needs no adjustment
- */
- W (*func)( const VECINFO*, UW vec, UW pc, UW cpsr );
-};
-
-/* display message */
-LOCAL W vf_msg( const VECINFO *vi, UW vec, UW pc, UW cpsr )
-{
- B *msg = vi->msg;
- B opt;
-
- if ( msg == NULL ) return 0;
-
- /* if the first byte of the message is not a letter, treat it as option.
- * opt = 0 - 037 (the code prior to ' ' )
- * \020 PC is adjusted to the previous instruction's address
- */
- opt = 0;
- if ( *msg < ' ' ) opt = *msg++;
-
- DSP_F5(S,"Exception ", D,vec, S," (", S,msg, CH,')');
-
- return ( opt & 020 )? 1: 0;
-}
-
-/* undefined instruction */
-LOCAL W vf_undef( const VECINFO *vi, UW vec, UW pc, UW cpsr )
-{
- if (cpsr & PSR_T) {
- DSP_F3(S,vi->msg, CH,' ', 04X,*((UH*)(pc - 2)));
- } else {
- DSP_F3(S,vi->msg, CH,' ', 08X,*((UW*)(pc - 4)));
- }
- return 1;
-}
-
-/* data abort */
-LOCAL W vf_dabort( const VECINFO *vi, UW vec, UW pc, UW cpsr )
-{
- DSP_F1(S,vi->msg);
- DSP_F4(S," ADDR: ", 08X,getCP15(6, 0), S," STAT: ", 08X,getCP15(5, 0));
- return 0;
-}
-
-/*
- * vector information table
- * this has to be filled in the ascending order of the vector number
- */
-LOCAL const VECINFO VecInfoTable[] = {
- { 0, "\020" "Undefined SWI", vf_msg },
- { EIT_UNDEF, "Undefined Instruction", vf_undef },
- { EIT_IABORT, "Prefetch Abort", vf_msg },
- { EIT_DABORT, "Data Abort", vf_dabort },
- { EIT_DABORT+1, "\020" "Undefined SWI", vf_msg },
-
- { EIT_FIQ, "Undefined FIQ", vf_msg },
- { EIT_IRQ(0), "Undefined IRQ", vf_msg },
- { EIT_GPIO(0), "Undefined GPIO-INT", vf_msg },
- { EIT_GPIO(127)+1,"\020" "Undefined SWI", vf_msg },
-
- { N_INTVEC, NULL, vf_msg } /* terminating mark (the last vector number + 1) */
-};
-#define N_VECINFO ( sizeof(VecInfoTable) / sizeof(VECINFO) )
-
-/*
- * EIT processing
- * * return value 0 : monitor should keep on running
- * 1 : return from the interrupt handler
- */
-EXPORT W procEIT( UW vec )
-{
- const VECINFO *vp;
- UW pc, cpsr;
- W i;
-
- pc = getCurPCX();
- cpsr = getCurCPSR();
-
- /* machine-dependent interrupt processing */
- i = procHwInt(vec);
- if ( i == 2 ) return 1; /* exit from the interrupt handler immediately */
-
- if ( i == 0 ) {
- /* other EIT processing */
- for ( i = 1; i < N_VECINFO; ++i ) {
- if ( vec < VecInfoTable[i].vec ) break;
- }
- vp = &VecInfoTable[i-1];
- i = (*vp->func)(vp, vec, pc, cpsr);
- if ( i > 0 ) {
- /* PC is adjusted to the previous instruction's address */
- pc -= ( (cpsr & PSR_T) != 0 )? 2: 4;
- }
- }
-
- DSP_F5(S,"\nPC: ", 08X,pc, S," CPSR: ", 08X,cpsr, CH,'\n');
-
- return 0;
-}
diff --git a/tkernel_source/monitor/hwdepend/tef_em1d/src/hwdepend.h b/tkernel_source/monitor/hwdepend/tef_em1d/src/hwdepend.h
deleted file mode 100644
index 0e98fe0..0000000
--- a/tkernel_source/monitor/hwdepend/tef_em1d/src/hwdepend.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * hwdepend.h
- *
- * T-Monitor hardware-dependent processing
- */
-
-#ifndef __MONITOR_CMDSVC_HWDEPEND_H__
-#define __MONITOR_CMDSVC_HWDEPEND_H__
-
-#include <tmonitor.h>
-#include "sysdepend.h"
-
-IMPORT UW DipSw; /* dip switch status */
-
-/*
- * system configuration information
- */
-IMPORT MEMSEG MemSeg[]; /* memory area definition */
-IMPORT W N_MemSeg; /* number of memory areas */
-
-IMPORT const CFGSIO ConfigSIO[]; /* serial port configuration definition */
-IMPORT const W N_ConfigSIO; /* serial port number */
-
-IMPORT const CFGDISK ConfigDisk[]; /* disk drive configuration definition */
-IMPORT const W N_ConfigDisk; /* nuber of disk drives */
-
-/*
- * initial processing after reset
- */
-IMPORT void procReset( void );
-
-/*
- * initialize hardware (peripherals)
- */
-IMPORT void initHardware( void );
-
-/*
- * setting up the initial count for micro-wait()
- */
-IMPORT void setupWaitUsec( void );
-
-/*
- * obtain the console port number
- * console port number (0 - )
- * if there is no console port, return -1.
- */
-IMPORT W getConPort( void );
-
-#endif /* __MONITOR_CMDSVC_HWDEPEND_H__ */
diff --git a/tkernel_source/monitor/hwdepend/tef_em1d/src/hwinfo.c b/tkernel_source/monitor/hwdepend/tef_em1d/src/hwinfo.c
deleted file mode 100644
index 3ef3db8..0000000
--- a/tkernel_source/monitor/hwdepend/tef_em1d/src/hwinfo.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * hwinfo.c
- *
- * hardware configuration information
- */
-
-#include "hwdepend.h"
-
-/* ------------------------------------------------------------------------ */
-/*
- * memory region definition
- */
-
-/*
- * obtaining memory region information
- * no = 1 - (and up)
- * 'no'-th information in the region specified by the attr is returned.
- * if attr = 0, no matter what the attribute is, 'no'-th information is returned unconditionally.
- * If there was no such information, return NULL.
- */
-EXPORT MEMSEG* MemArea( UW attr, W no )
-{
- MEMSEG *mp;
- W i;
-
- if ( attr == 0 ) {
- i = no - 1;
- return ( i >= 0 && i < N_MemSeg )? &MemSeg[i]: NULL;
- }
-
- for ( i = 0; i < N_MemSeg; ++i ) {
- mp = &MemSeg[i];
- if ( (mp->attr & attr) != 0 ) {
- if ( --no <= 0 ) return mp;
- }
- }
-
- return NULL;
-}
-
-/*
- * obtaining memory region information (specify address)
- * within the region specified by `attr', return the information that surrounds the position specified by `addr'.
- *
- * if no such information is found, return NULL.
- */
-EXPORT MEMSEG* AddrMatchMemArea( UW addr, UW attr )
-{
- MEMSEG *mp;
- W i;
-
- for ( i = 0; i < N_MemSeg; ++i ) {
- mp = &MemSeg[i];
- if ( (mp->attr & attr) == 0 ) continue;
-
- if ( addr >= mp->top && addr <= mp->end-1 ) return mp;
- }
-
- return NULL;
-}
-
-/*
- * Decide whether two memory regions are included in another.
- * if the region, from `top' to `end', is completely included in the region specified by `attr',
- * TRUE
- * the location of end is NOT included in the region (end - top) is the region size
- * end = 0x00000000, by the way, means 0x100000000.
- */
-EXPORT BOOL inMemArea( UW top, UW end, UW attr )
-{
- const MEMSEG *mp;
- W i;
-
- for ( i = 0; i < N_MemSeg; ++i ) {
- mp = &MemSeg[i];
- if ( (mp->attr & attr) == 0 ) continue;
-
- if ( top >= mp->top && end-1 <= mp->end-1 ) return TRUE;
- }
- return FALSE;
-}
-
-/*
- * Decide whether two memory regions overlap with each other
- * if the area, from top to end, is included even partially in the region specified by `attr' - 'end',
- * it is TRUE
- * the location of end is NOT included in the region (end - top) is the region size
- * end = 0x00000000, by the way, means 0x100000000.
- */
-EXPORT BOOL isOverlapMemArea( UW top, UW end, UW attr )
-{
- const MEMSEG *mp;
- W i;
-
- for ( i = 0; i < N_MemSeg; ++i ) {
- mp = &MemSeg[i];
- if ( (mp->attr & attr) == 0 ) continue;
-
- if ( top <= mp->end-1 && end-1 >= mp->top ) return TRUE;
- }
- return FALSE;
-}
-
-/* ------------------------------------------------------------------------ */
-/*
- * boot device following the standard boot order
- * return the device name that is the 'no'-th device in the standard boot order.
- *
- * if no such device name exists (when 'no' is given as a value larger or equal to the last number), it is NULL.
- */
-EXPORT const UB* bootDevice( W no )
-{
- if ( no < 0 || no >= N_ConfigDisk ) return NULL;
-
- return ConfigDisk[no].name;
-}
-
-/*
- * list of disk drives
- * returns the disk drive device name, indicated by 'no' ( 0 - : a consecutive number )
- * if no such device name exists (when 'no' is given as a value larger or equal to the last number), it is NULL.
- * if attr is not NULL, disk driver attribute returns in `attr' )
- */
-EXPORT const UB* diskList( W no, UW *attr )
-{
- if ( no < 0 || no >= N_ConfigDisk ) return NULL;
-
- if ( attr != NULL ) *attr = ConfigDisk[no].attr;
-
- return ConfigDisk[no].name;
-}
-
-/* ------------------------------------------------------------------------ */
diff --git a/tkernel_source/monitor/hwdepend/tef_em1d/src/memattr.S b/tkernel_source/monitor/hwdepend/tef_em1d/src/memattr.S
deleted file mode 100644
index eb1fa2e..0000000
--- a/tkernel_source/monitor/hwdepend/tef_em1d/src/memattr.S
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * memattr.S
- *
- * manipulation of page table
- */
-#define _in_asm_source_
-
-#include <machine.h>
-#include <tk/sysdef.h>
-
-#include "setup_em1d512.h"
-
-/*
- * memory barrier macros
- */
-.macro _mov reg, val
- .ifnes "\reg", "\val"
- mov \reg, \val
- .endif
-.endm
-.macro .ISB reg, val=#0
- _mov \reg, \val
- mcr p15, 0, \reg, cr7, c5, 4
-.endm
-.macro .DSB reg, val=#0
- _mov \reg, \val
- mcr p15, 0, \reg, cr7, c10, 4
-.endm
-.macro .DMB reg, val=#0
- _mov \reg, \val
- mcr p15, 0, \reg, cr7, c10, 5
-.endm
-
-/*
- * change memory attribute
- * void ChangeMemAttr(UW top, UW end, UW attr)
- * change the memory attribute of memory area from `top' to `end' - 1 into `attr'
- * The physical address where T-Monitor resides is assumed to start at 0x00000000.
- * It must be called with disabled cache.
- */
- .text
- .balign 4
- .globl Csym(ChangeMemAttr)
- .type Csym(ChangeMemAttr), %function
-Csym(ChangeMemAttr):
-changememattr_start:
- stmfd sp!, {r4, r5, r7, r9, r10}
-
- /* Map T-Monitor to 0x00000000 and up, the information before the mapping is saved. */
- ldr ip, =PAGETBL_BASE
- ldr r4, [ip]
- ldr r10, =attr_prev
- str r4, [r10]
- ldr r4, =0x00009402 // Strongly-order, Kernel/RO
- str r4, [ip]
-
- .DSB r4
- mcr p15, 0, r4, cr8, cr7, 0 // I/D TLB invalidate
- mcr p15, 0, r4, cr7, cr5, 6 // invalidate BTC
- .DSB r4
- .ISB r4
-
- /* Jump to the address into the remapped area */
- ldr r4, =changememattr_main
- ldr r9, =0xfff00000
- bic r4, r4, r9 // r4 &= 0x000fffff
- mov pc, r4
-
- .pool
-
-changememattr_main:
- bic r2, r2, r9 // r2 &= 0x000fffff
- mov r4, r0, lsr #20
- add r4, ip, r4, lsl #2 // r4 = (r2 >> 20) * 4 + PAGETBL_BASE
-
-changememattr_loop:
- ldr r5, [r4] // *r4 = (*r4 & 0xfff00000) | r2
- and r5, r5, r9
- orr r5, r5, r2
- str r5, [r4], #4
- add r0, r0, #0x00100000
- cmp r0, r1
- bne changememattr_loop
-
- /* Jump to the address in the originally mapped area */
- .DSB r4
- mcr p15, 0, r4, cr8, cr7, 0 // I/D TLB invalidate
- mcr p15, 0, r4, cr7, cr5, 6 // invalidate BTC
- .DSB r4
- .ISB r4
-
- ldr pc, =changememattr_finish
-
- .pool
-
-changememattr_finish:
- /* Unmap the T-Monitor in the area from 0x00000000 and up. */
- ldr r4, [r10] // attr_prev
- str r4, [ip] // PAGETBL_BASE
-
- .DSB r4
- mcr p15, 0, r4, cr8, cr7, 0 // I/D TLB invalidate
- mcr p15, 0, r4, cr7, cr5, 6 // invalidate BTC
- .DSB r4
- .ISB r4
-
- ldmfd sp!, {r4, r5, r7, r9, r10}
- bx lr
-
- .pool
-
-
- .bss
-attr_prev:
- .long 0
diff --git a/tkernel_source/monitor/hwdepend/tef_em1d/src/misc.c b/tkernel_source/monitor/hwdepend/tef_em1d/src/misc.c
deleted file mode 100644
index 4486c5a..0000000
--- a/tkernel_source/monitor/hwdepend/tef_em1d/src/misc.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * misc.c
- *
- */
-
-#include "sysdepend.h"
-
-/*
- * obtain switch status
- */
-EXPORT UW getDipSw( void )
-{
- return DipSw;
-}
-
-/*
- * Obtain boot selection information
- */
-EXPORT W bootSelect( void )
-{
- if ( (DipSw & (SW_MON|SW_ABT)) != 0 ) return BS_MONITOR;
-
- return BS_AUTO;
-}
-
-/*
- * obtain the console port number
- */
-EXPORT W getConPort( void )
-{
- return 0;
-}
diff --git a/tkernel_source/monitor/hwdepend/tef_em1d/src/reset.S b/tkernel_source/monitor/hwdepend/tef_em1d/src/reset.S
deleted file mode 100644
index 50e90ee..0000000
--- a/tkernel_source/monitor/hwdepend/tef_em1d/src/reset.S
+++ /dev/null
@@ -1,639 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * reset.S
- *
- * EM1-D512: initial setting after a reset.
- */
-
-#define _in_asm_source_
-
-#include <machine.h>
-#include <tk/sysdef.h>
-#include <arm/em1d512.h>
-#include <sys/sysinfo.h>
-
-#include "setup_em1d512.h"
-
-/*
- * macro for setting up registers
- */
-.macro out_w reg, val
- .ifnes "\val", "" // when val is empty, do nothing.
- ldr r0, =\reg
- ldr r1, =\val
- str r1, [r0]
- .endif
-.endm
-
-.macro setup_param // r0: address of parameter string.
-0: // * r0, r2, and r3 are going to be clobbered.
- ldmia r0!, {r2, r3}
- cmp r2, #0
- strne r3, [r2]
- bne 0b
-.endm
-
-.macro wait_nsec // r0: wait time (nsec)
- // * Assume one step is 4 ns @ (500MHz)
- lsr r0, r0, #2
-0:
- subs r0, r0, #1
- bne 0b
-.endm
-
-/*
- * memory barrier macros
- */
-.macro _mov reg, val
- .ifnes "\reg", "\val"
- mov \reg, \val
- .endif
-.endm
-.macro .ISB reg, val=#0
- _mov \reg, \val
- mcr p15, 0, \reg, cr7, c5, 4
-.endm
-.macro .DSB reg, val=#0
- _mov \reg, \val
- mcr p15, 0, \reg, cr7, c10, 4
-.endm
-.macro .DMB reg, val=#0
- _mov \reg, \val
- mcr p15, 0, \reg, cr7, c10, 5
-.endm
-
-/*----------------------------------------------------------------------
- T-Monitor boot processing
-----------------------------------------------------------------------*/
- .section .startup, "ax"
- .balign 4
- .globl startup_entry
- .type startup_entry, %function
- .org 0x00000000
-startup_entry:
-// SVC mode, FIQ/IRQ interrupt disabled
- mov r0, #(PSR_SVC | PSR_I | PSR_F)
- msr cpsr_fsxc, r0
-
-// use On-Chip SRAM as stack area
- ldr sp, =0xa0020000
-
-// not in effect: MMU, cache (D/I), program-flow prediction, High-Vector, VIC
-// in effect: Force AP, TEX remap, Subpage AP
- .DSB r0
- mrc p15, 0, r0, cr1, cr0, 0
- ldr r1, =~0x01003f85
- and r0, r0, r1
- ldr r1, =0x30800000
- orr r0, r0, r1
- mcr p15, 0, r0, cr1, cr0, 0
-
-// Setup clock divider
- mov r0, #0
- ldr r2, =CHG_L1_HOLD
- str r0, [r2] // release data hold when L1 is off
- mov r0, #0x30000000
- ldr r2, =AUTO_FRQ_CHANGE
- str r0, [r2] // automatic frequency change function is off
-
-setup_clock_divider:
- adr r0, param_table0
- setup_param
-
-// Setup PLL1 (PLL3 is operating)
-setup_pll1:
- // We assume Power ON mode: In other mode setting, we simply take it for granted that PLL has been configured already
- ldr r2, =CLK_MODE_SEL
- ldr r0, [r2]
- ands r0, r0, #0x00000f00
- bne setup_power_mode
-
- mov r0, #0x79 // (default) PLL1=499.712MHz
- ldr r2, =PLL1CTRL0
- str r0, [r2]
- mov r0, #0
- ldr r2, =PLL1CTRL1
- str r0, [r2] // PLL starts to operate
- ldr r2, =PLL_STATUS
-wait_pll1:
- ldr r0, [r2] // Wait for PLL1 operation completion
- ands r0, r0, #0x00000001
- beq wait_pll1
-
-// Setup power mode
-setup_power_mode:
- // Transition from Power ON to Normal Mode A
- mov r0, #1
- ldr r2, =CLK_MODE_SEL
- str r0, [r2]
-wait_power_mode_change:
- ldr r0, [r2]
- and r0, r0, #0x00000f00
- cmp r0, #0x00000100
- bne wait_power_mode_change
-
-// Setup PLL2 (needs to be configured in Normal Mode)
-setup_pll2:
- mov r0, #0xff // PLL2 ceases to operate
- ldr r2, =PLL2CTRL1
- str r0, [r2]
- ldr r2, =PLL_STATUS
-wait_pll2_0:
- ldr r0, [r2] // Wait for PLL1 operation
- ands r0, r0, #0x00000100
- bne wait_pll2_0
-
- mov r0, #0x61 // PLL2=401.408MHz
- ldr r2, =PLL2CTRL0
- str r0, [r2]
- mov r0, #0 // PLL2 starts to operate
- ldr r2, =PLL2CTRL1
- str r0, [r2]
- ldr r2, =PLL_STATUS
-wait_pll2_1:
- ldr r0, [r2] // wait for PLL2 to stop operation.
- ands r0, r0, #0x00000100
- beq wait_pll2_1
-
-// Setup pin multiplexer
-setup_pin_mux:
- mov r1, #0xff000000 // since 'adr' cannot be used, we manually make sure
- ldr r0, =Csym(GPIOConfig) // that the code is relocatable at 16MB units boundary.
- bic r0, r0, r1
- and r1, pc, r1
- orr r0, r0, r1
- setup_param
-
-// release reset of the internal modules
-setup_module:
- adr r0, param_table1
- setup_param
- ldr r0, =100000
- wait_nsec
-
-// supplying clock to modules.
-setup_clock_distribution:
- adr r0, param_table2
- setup_param
-
-// Setup Bus controller
-setup_bcr:
- adr r0, param_table3
- setup_param
-
-// initialization of DDR memory
- bl setup_ddr
-
-// creation of temporary page table
- ldr r0, =PAGETBL_BASE
- ldr r1, =0x00000000
- ldr r2, =0x00000402 // Kernel/RW, Strongly-order
-tmptable_loop:
- orr r3, r1, r2
- str r3, [r0], #4
- adds r1, r1, #0x00100000
- bne tmptable_loop
-
-// Mapping of FlashROM area (0x70000000 - 0x72000000 --> 0x00000000 -)
- ldr r0, =(PAGETBL_BASE + (0x700 << 2))
- ldr r1, =0x00000000
- ldr r2, =0x0000940e // Kernel/RO, Normal WB/WA
-flashtable_loop:
- orr r3, r1, r2
- str r3, [r0], #4
- adds r1, r1, #0x00100000
- cmp r1, #0x02000000
- bne flashtable_loop
-
-// initialization of CP15
- ldr r0, =0x00000004
- mcr p15, 0, r0, cr2, cr0, 2 // TTBCR
- ldr r0, =(PAGETBL_BASE + 0x09) // WB/WA, no-shared, cachable
- mcr p15, 0, r0, cr2, cr0, 1 // TTBR1
- mcr p15, 0, r0, cr2, cr0, 0 // TTBR0
- ldr r0, =EITENT_BASE
- mcr p15, 0, r0, cr12, cr0, 0 // VBAR
- ldr r0, =0x000a8aa4
- mcr p15, 0, r0, cr10, cr2, 0 // PRRR
- ldr r0, =0x44e048e0
- mcr p15, 0, r0, cr10, cr2, 1 // NMRR
- ldr r0, =0x55555555 // All client
- mcr p15, 0, r0, cr3, cr0, 0 // Domain access
-
-// MMU enable
- .DSB r0
- mcr p15, 0, r0, cr8, cr7, 0 // I/D TLB invalidate
- mcr p15, 0, r0, cr7, cr5, 6 // invalidate BTC
- .DSB r0
- .ISB r0
- mrc p15, 0, r0, cr1, cr0, 0
- orr r0, r0, #0x00000001
- mcr p15, 0, r0, cr1, cr0, 0
- .ISB r0
-
-// perform reset processing
- ldr pc, =reset_entry
-
-// initialization of DDR memory
-setup_ddr:
- ldr r0, =MEMCCLK270_SEL
- ldr r1, =0x00000001 // MEMCCLK270 no phase delay
- str r1, [r0]
-
- ldr r0, =MEMC_DDR_CONFIGT1
- ldr r1, =0x00000006 // start auto-calibration
- str r1, [r0]
-calibrate_loop:
- ldr r1, [r0]
- ands r1, r1, #0x00000002 // wait for complete
- beq calibrate_loop
-
- ldr r0, =MEMC_DDR_CONFIGT3
- ldr r1, [r0] // get calibration result
- ldr r0, =MEMC_DDR_CONFIGT2
- str r1, [r0] // apply calibrated value
-
- ldr r0, =MEMCCLK270_SEL
- ldr r1, =0x00000000 // MEMCCLK270 270degree delay
- str r1, [r0]
-
- ldr r0, =MEMC_DDR_CONFIGT1
- ldr r1, =0x000d0803
- str r1, [r0]
-
- ldr r0, =MEMC_DDR_CONFIGF
- ldr r1, =0x00000015
- str r1, [r0]
-
- ldr r0, =MEMC_DDR_CONFIGA1
- ldr r1, =0x53443203
- str r1, [r0]
-
- ldr r0, =MEMC_DDR_CONFIGA2
- ldr r1, =0x28da1042
- str r1, [r0]
-
- ldr r0, =MEMC_DDR_CONFIGC2
- ldr r1, =0x0000001d
- str r1, [r0]
-
- ldr r0, =200000
- wait_nsec
-
- ldr r0, =MEMC_DDR_CONFIGC1
- ldr r1, =0x80200033
- str r1, [r0]
-
- ldr r0, =MEMC_DDR_CONFIGC2
- ldr r1, =0x00000018 // CS0: memory initialize sequence
- str r1, [r0]
-ddr_init_loop:
- ldr r1, [r0]
- ands r1, r1, #0x00000100
- beq ddr_init_loop
-
- ldr r0, =MEMC_REQSCH
- ldr r1, =0x0000001f // memory request schedule
- str r1, [r0]
-
- ldr r0, =MEMC_DDR_CONFIGC2
- ldr r1, =0x00000090 // CS0: CMD_REQ release
- str r1, [r0]
-
- ldr r0, =MEMC_DDR_CONFIGR1
- ldr r1, =0x00690069 // refresh counter
- str r1, [r0]
-
- ldr r0, =MEMC_DDR_CONFIGR2
- ldr r1, =0x3777011f
- str r1, [r0]
-
- ldr r0, =MEMC_DDR_CONFIGR3
- ldr r1, =0x00001415
- str r1, [r0]
-
- bx lr
-
- .pool
-
-param_table0:
- .long NORMALA_DIV // ACPU =PLL1/1 (499.712MHz)
- .long 0x00244200 // ADSP =PLL1/1 (499.712MHz)
- // HBUS =PLL1/3 (166.571MHz)
- // LBUS =PLL1/6 ( 83.285MHz)
- // FLASH=PLL1/6 ( 83.285MHz)
- // MEMC =PLL1/3 (166.571MHz)
- .long DIVU70SCLK
- .long 0x00000000 // U70_SCLK=PLL3/1 (229.376MHz)
- .long DIVU71SCLK
- .long 0x00000000 // U71_SCLK=PLL3/1 (229.376MHz)
- .long DIVU72SCLK
- .long 0x00000000 // U72_SCLK=PLL3/1 (229.376MHz)
- .long DIVLCDLCLK
- .long 0x00000004 // LCD_LCLK=PLL2/16 (25.088MHz)
- .long DIVIICSCLK
- .long 0x00530053 // IIC_SCLK=PLL3/48 (4.779MHz)
- .long DIVTIMTIN
- .long 0x00000003 // Txx_TIN=PLL3/8 (28.672MHz)
- .long DIVSP0SCLK
- .long 0x00000074 // SP0_SCLK=PLL3/128 (1.792MHz)
- .long TI0TIN_SEL
- .long 0x00000000
- .long TI1TIN_SEL
- .long 0x00000000
- .long TI2TIN_SEL
- .long 0x00000000
- .long TI3TIN_SEL
- .long 0x00000000
- .long TIGnTIN_SEL
- .long 0x00000000
-
- .long 0x00000000 // (terminate)
- .long 0x00000000
-
-param_table1:
- .long RESETREQ0ENA
- .long 0xffffffff
- .long RESETREQ0
- .long 0xffffffe7 // Reset everything, but DSP
- .long RESETREQ0ENA
- .long 0x00000000
- .long RESETREQ1ENA
- .long 0xffffffff
- .long RESETREQ1
- .long 0xffffffff // Reset everything
- .long RESETREQ1ENA
- .long 0x00000000
- .long RESETREQ2ENA
- .long 0xffffffff
- .long RESETREQ2
- .long 0xffffffff // Reset everything
- .long RESETREQ2ENA
- .long 0x00000000
- .long RESETREQ3ENA
- .long 0xffffffff
- .long RESETREQ3
- .long 0xffffffff // Reset everything
- .long RESETREQ3ENA
- .long 0x00000000
-
- .long 0x00000000 // (terminate)
- .long 0x00000000
-
-param_table2:
- .long GCLKCTRL0ENA
- .long 0xffffffff
- .long GCLKCTRL0
- .long 0xffffffff // (default) module clock on
- .long GCLKCTRL0ENA
- .long 0x00000000
- .long GCLKCTRL1ENA
- .long 0xffffffff
- .long GCLKCTRL1
- .long 0xffffffff // (default) module clock on
- .long GCLKCTRL1ENA
- .long 0x00000000
- .long GCLKCTRL2ENA
- .long 0xffffffff
- .long GCLKCTRL2
- .long 0xffffffff // (default) module clock on
- .long GCLKCTRL2ENA
- .long 0x00000000
- .long GCLKCTRL3ENA
- .long 0xffffffff
- .long GCLKCTRL3
- .long 0xffffffff // (default) module clock on
- .long GCLKCTRL3ENA
- .long 0x00000000
- .long GCLKCTRL4ENA
- .long 0xffffffff
- .long GCLKCTRL4
- .long 0xffffffff // (default) module clock on
- .long GCLKCTRL4ENA
- .long 0x00000000
- .long AHBCLKCTRL0
- .long 0x00000000 // (default) prohibit automatic control
- .long AHBCLKCTRL1
- .long 0x00000000 // (default) prohibit automatic control
- .long APBCLKCTRL0
- .long 0x00000000 // (default) prohibit automatic control
- .long APBCLKCTRL1
- .long 0x00000000 // (default) prohibit automatic control
- .long CLKCTRL
- .long 0x00000000 // (default) prohibit automatic control
- .long CLKCTRL1
- .long 0x00000000
-
- .long 0x00000000 // (terminate)
- .long 0x00000000
-
-param_table3:
- .long AB1_U70WAITCTRL
- .long 0x00010200 // recommended value for 83MHz operation
- .long AB1_U71WAITCTRL
- .long 0x00010200 // recommended value for 83MHz operation
- .long AB1_U72WAITCTRL
- .long 0x00010200 // recommended value for 83MHz operation
- .long AB1_IIC2WAITCTRL
- .long 0x00010300 // recommended value for 83MHz operation
- .long AB1_IICWAITCTRL
- .long 0x00010300 // recommended value for 83MHz operation
- .long AB1_SDIAWAITCTRL
- .long 0x00010300
- .long AB1_SDIBWAITCTRL
- .long 0x00010300
- .long AB1_SDICWAITCTRL
- .long 0x00010300
- .long AB1_U70READCTRL
- .long 0x00000000 // (default)
- .long AB1_U71READCTRL
- .long 0x00000000 // (default)
- .long AB1_U72READCTRL
- .long 0x00000000 // (default)
- .long AB1_IIC2READCTRL
- .long 0x00000000 // (default)
- .long AB1_IICREADCTRL
- .long 0x00000000 // (default)
- .long AB1_SDIAREADCTRL
- .long 0x00000000 // (default)
- .long AB1_SDIBREADCTRL
- .long 0x00000000 // (default)
- .long AB1_SDICREADCTRL
- .long 0x00000000 // (default)
-
- // memory map setup (CS0-3)
- //
- // 0x00000000 +----------------------------+
- // | Bank0/CS0 (not used) |
- // 0x10000000 +----------------------------+
- // | Bank1/CS1 (not used) |
- // 0x20000000 +----------------------------+
- // | Bank2/CS2 (not used) |
- // 0x28000000 +----------------------------+
- // | Bank2/CS3 (LAN controller) |
- // 0x30000000 +----------------------------+
- .long AB0_CSnBASEADD(0)
- .long 0x00000000
- .long AB0_CSnBITCOMP(0)
- .long 0xf0000000
- .long AB0_CSnBASEADD(1)
- .long 0x10000000
- .long AB0_CSnBITCOMP(1)
- .long 0xf0000000
- .long AB0_CSnBASEADD(2)
- .long 0x20000000
- .long AB0_CSnBITCOMP(2)
- .long 0xf8000000
- .long AB0_CSnBASEADD(3)
- .long 0x28000000
- .long AB0_CSnBITCOMP(3)
- .long 0xf8000000
- .long AB0_FLASHCLKCTRL
- .long 0x00000001 // AB0:Flash=1:2
-
- // set up LAN controller
- // Assuming the use of 83.333 MHz (12ns/1clk), we set the following values.
- // CSint=1clk (Read+1clk=24ns, Write+2clk=36ns)
- // T0=0clk (0ns), T1=3clk(36ns), T2=2clk(24ns)
- .long AB0_CSnWAITCTRL(3)
- .long 0x01020300
- .long AB0_CSnWAITCTRL_W(3)
- .long 0x00020300
- .long AB0_CSnREADCTRL(3)
- .long 0x00000000 // (default)
- .long AB0_CSnWAIT_MASK(3)
- .long 0x00000000 // (default)
- .long AB0_CSnCONTROL(3)
- .long 0x00010100 // (default)
- .long AB0_FLASHCOMSET
- .long 0x00000008 // CS3 value above is reflected.
-
- .long 0x00000000 // (terminate)
- .long 0x00000000
-
-/*----------------------------------------------------------------------
- Reset processing
-----------------------------------------------------------------------*/
- .text
- .balign 4
- .globl reset_entry
- .type reset_entry, %function
-reset_entry:
-
-// SVC mode, FIQ/IRQ interrupt disabled
- mov r0, #(PSR_SVC | PSR_I | PSR_F)
- msr cpsr_fsxc, r0
-
-// Switch to T-Monitor stack
- ldr sp, =__stack_bottom
-
-// not in effect: cache (D/I), program-flow prediction, High-Vector, VIC
-// in effect: Force AP, TEX remap, Subpage AP
- .DSB r0
- mrc p15, 0, r0, cr1, cr0, 0
- ldr r1, =~0x01003f84
- and r0, r0, r1
- ldr r1, =0x30800000
- orr r0, r0, r1
- mcr p15, 0, r0, cr1, cr0, 0
-
- .ISB r0
- mcr p15, 0, r0, cr8, cr7, 0 // I/D TLB invalidate
- .DSB r0
- bl Csym(FlushCache) // Clean/invalidate I/D cache
-
-// Turn on VFP
- mrc p15, 0, r0, cr1, cr0, 2
- orr r0, r0, #0x00f00000 // VFP(CP11,CP10) enable
- bic r0, r0, #0xc0000000 // Should be Zero
- mcr p15, 0, r0, cr1, cr0, 2
- .ISB r0 // Flush Prefetch buffer
-
-// initialize data area
- ldr r1, =__data_org
- ldr r2, =__data_start
- ldr r3, =_edata
-data_loop:
- ldmia r1!, {r4-r7} // copy in unit of 16 bytes
- stmia r2!, {r4-r7}
- cmp r2, r3
- blo data_loop
-
-// clear bss and stack area
- ldr r2, =__bss_start
- ldr r3, =__stack_bottom
- ldr r4, =0
- ldr r5, =0
- ldr r6, =0
- ldr r7, =0
-bss_loop:
- stmia r2!, {r4-r7} // clear in units of 16 bytes
- cmp r2, r3
- blo bss_loop
-
-// reset processing
- bl procReset
-
-// clear registers & initialize stack pointer
- ldr r7, =__stack_top // since it is 0-cleared, why not use it.
-
- ldmia r7, {r8-r12,sp,lr}^ // usr: r8-r12, sp, lr
-
- mov r0, #(PSR_FIQ | PSR_I | PSR_F)
- msr cpsr_fsxc, r0
- ldmia r7, {r8-r12,sp,lr} // fiq: r8-r12, sp, lr, spsr
- msr spsr_fsxc, lr
- ldr sp, =__stack_top + 32
-
- mov r0, #(PSR_IRQ | PSR_I | PSR_F)
- msr cpsr_fsxc, r0
- ldr sp, =__stack_top + 16 // irq: sp, lr, spsr
- mov lr, #0
- msr spsr_fsxc, lr
-
- mov r0, #(PSR_ABT | PSR_I | PSR_F)
- msr cpsr_fsxc, r0
- ldr sp, =__stack_top + 64 // abt: sp, lr, spsr
- mov lr, #0
- msr spsr_fsxc, lr
-
- mov r0, #(PSR_UND | PSR_I | PSR_F)
- msr cpsr_fsxc, R0
- ldr sp, =__stack_top + 48 // und: sp, lr, spsr
- mov lr, #0
- msr spsr_fsxc, lr
-
- // clear VFP
- mov r0, #0x40000000 // EX=0,EN=1,SBZ/other flags = 0
- fmxr fpexc, r0
-
- mov r1, #0x00000000 // SBZ/other flags = 0
- fmxr fpscr, r1
-
- fldmiad r7, {d0-d15} // zero clear
-
- // return to SVC mode
- mov r0, #(PSR_SVC | PSR_I | PSR_F)
- msr cpsr_fsxc, r0
-
- ldmia r7, {r0-r7} // r0-r7
-
-// enter monitor by means of SVC #0 instruction (SVC mode)
- resetLoop:
- svc #0
- b resetLoop // return will cause another reset
-
- .pool
diff --git a/tkernel_source/monitor/hwdepend/tef_em1d/src/setup_em1d512.h b/tkernel_source/monitor/hwdepend/tef_em1d/src/setup_em1d512.h
deleted file mode 100644
index e733589..0000000
--- a/tkernel_source/monitor/hwdepend/tef_em1d/src/setup_em1d512.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * setup_em1d512.h
- *
- * EM1D-512 configuration information
- *
- * this file included from assembly source files, too.
- */
-
-#define EITENT_BASE 0x70000000 /* address for exception branch processing */
-#define PAGETBL_BASE 0x30000000 /* address of the first level table page. */
-
-/*
- * clock value
- */
-#define PLL1_CLK 499712 /* 499.712MHz */
-#define PLL2_CLK 401418 /* 401.408MHz */
-#define PLL3_CLK 229376 /* 229.376MHz */
-
-#define ACPU_CLK (PLL1_CLK / 1)
-#define Txx_CLK (PLL3_CLK / 8)
-
-/*
- * assignment to DipSw (switches)
- */
-#define SW_ABT 0x0100 /* Abort SW */
-#define SW_MON 0x0020 /* Monitor Boot */
-#define SW_BHI 0x0000 /* fix HI_BAUD_RATE */
-
-/*
- * LED display (two bits, 2 bits)
- */
-#define LED_POWERUP 0x01 /* Power-on */
-#define LED_MEMCLR 0xff /* Memory clear */
diff --git a/tkernel_source/monitor/hwdepend/tef_em1d/src/sio.c b/tkernel_source/monitor/hwdepend/tef_em1d/src/sio.c
deleted file mode 100644
index af858b2..0000000
--- a/tkernel_source/monitor/hwdepend/tef_em1d/src/sio.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * sio.c
- *
- * serial port I/O
- */
-
-#include "hwdepend.h"
-
-EXPORT W ConPort; /* console port number */
-EXPORT UW ConPortBps; /* console port commnication speed (bps) */
-
-LOCAL SIOCB SIO; /* serial port control block */
-
-/*
- * initialize serial port
- * port console port number (0 - )
- * when it is -1, it means there is no console.
- * speed communication speed (bps)
- */
-EXPORT ER initSIO( W port, W speed )
-{
- const CFGSIO *cp;
- ER err;
-
- if ( port >= N_ConfigSIO ) port = 0; /* invalid value is turned into a default value. */
-
- memset(&SIO, 0, sizeof(SIO));
- ConPort = port;
- ConPortBps = speed;
-
- if ( port < 0 ) return E_OK; /* no console */
-
- /* initialize hardware */
- cp = &ConfigSIO[port];
- err = (*cp->initsio)(&SIO, cp, speed);
- if ( err < E_OK ) goto err_ret;
-
- return E_OK;
-
-err_ret:
- /* if there was an error, treat it as no console */
- memset(&SIO, 0, sizeof(SIO));
- ConPort = -1;
- return err;
-}
-
-/*
- * serial port I/O
- */
-EXPORT void putSIO( UB c )
-{
- if ( SIO.put != NULL ) (*SIO.put)(&SIO, c);
-}
-
-/*
- * serial port input (with buffering)
- * tmo timeout (milliseconds)
- * You can not wait forever.
- * return value >= 0 : character code
- * -1 : timeout
- * receive error is ignored
- */
-EXPORT W getSIO( W tmo )
-{
- return ( SIO.get != NULL )? (*SIO.get)(&SIO, tmo): -1;
-}
diff --git a/tkernel_source/monitor/hwdepend/tef_em1d/src/startup.c b/tkernel_source/monitor/hwdepend/tef_em1d/src/startup.c
deleted file mode 100644
index fa0feb3..0000000
--- a/tkernel_source/monitor/hwdepend/tef_em1d/src/startup.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * startup.c
- *
- * system boot processing
- */
-
-#include "hwdepend.h"
-
-/* No support for the progress report yet */
-#define DispProgress(n) /* nop */
-
-/*
- * debug port speed
- * default setting is LO:38400bps, and HI:115200bps. But
- * if you need a different set value, then define the following macros in {cpu}/{machine}/setup_xxx.h :
- * LO_BAUD_RATE, and HI_BAUD_RATE.
- */
-#ifndef LO_BAUD_RATE
-# define LO_BAUD_RATE 38400
-#endif
-#ifndef HI_BAUD_RATE
-# define HI_BAUD_RATE 115200
-#endif
-
-/*
- * initial processing after reset
- */
-EXPORT void procReset( void )
-{
- const MEMSEG *mp;
- W i;
- W speed;
-
- DispProgress(0x01);
-
- /* system basic set up */
- resetSystem(0);
- DispProgress(0x06);
-
- /* setting up the initial count for micro-wait */
- setupWaitUsec();
- DispProgress(0x07);
-
- /* initialize console serial port */
-#if SW_BHI == 0
- speed = HI_BAUD_RATE; /* HI speed is fixed. */
-#else
- speed = ( (DipSw & SW_BHI) != 0 )? HI_BAUD_RATE: LO_BAUD_RATE;
-#endif
- initSIO(getConPort(), speed);
- DispProgress(0x08);
-
- /* initialize hardware (peripherals) */
- initHardware();
- DispProgress(0x0d);
-
- /* memory clear is not done to save time when automatic reboot is under way. */
- if ( bootSelect() == BS_MONITOR ) {
- cpuLED(LED_MEMCLR);
-
- /* all memory clear (save the monitor area) */
- for ( i = 1;; ++i ) {
- mp = MemArea(MSA_OS|MSA_ERAM, i);
- if ( mp == NULL ) break;
-
- memset((void*)mp->top, 0, mp->end - mp->top);
- }
- }
- cpuLED(LED_POWERUP);
- DispProgress(0x0e);
-
- /* initialize break processing */
- initBreak();
-
- /* Invoking user reset initialization routine */
- callUserResetInit();
- DispProgress(0x0f);
-}
diff --git a/tkernel_source/monitor/hwdepend/tef_em1d/src/sysdepend.h b/tkernel_source/monitor/hwdepend/tef_em1d/src/sysdepend.h
deleted file mode 100644
index 8003371..0000000
--- a/tkernel_source/monitor/hwdepend/tef_em1d/src/sysdepend.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * sysdepend.h
- *
- * system-related definitions: ARM CPUs.
- */
-
-#ifndef __MONITOR_CMDSVC_SYSDEPEND_H__
-#define __MONITOR_CMDSVC_SYSDEPEND_H__
-
-#include "hwdepend.h"
-#include <sys/sysinfo.h>
-#include <sys/rominfo.h>
-#include "setup_em1d512.h"
-
-/*
- * cache and MMU control
- */
-IMPORT void setCacheMMU( UW cp15r1 );
-
-/*
- * machine-dependent interrupt processing
- * info is defined in machine-dependent manner.
- * return value 0 : it is not the target of processing.
- * 1 : the object is the target of processing (the monitor should continue monitoring)
- * 2 : the object is the target of processing (exiting interrupt handler).
- */
-IMPORT W procHwInt( UW info );
-
-#endif /* __MONITOR_CMDSVC_SYSDEPEND_H__ */
diff --git a/tkernel_source/monitor/hwdepend/tef_em1d/src/system.c b/tkernel_source/monitor/hwdepend/tef_em1d/src/system.c
deleted file mode 100644
index fb541a0..0000000
--- a/tkernel_source/monitor/hwdepend/tef_em1d/src/system.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by T-Engine Forum at 2011/09/08.
- * Modified by T-Engine Forum at 2013/03/04.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * system.c
- *
- * system-related processing
- *
- * target: EM1D-512
- */
-
-#include "sysdepend.h"
-#include <arm/em1d512.h>
-
-EXPORT UW DipSw; /* DipSw status */
-
-/* hardware dependent functions */
-IMPORT UW DipSwStatus(void);
-IMPORT void usbPower(BOOL power);
-IMPORT void powerOff(void);
-IMPORT void resetStart(void);
-
-/* interrupt entry point (eitent.S) */
-IMPORT void _gio0Hdr(void);
-IMPORT void _gio1Hdr(void);
-IMPORT void _gio2Hdr(void);
-IMPORT void _gio3Hdr(void);
-IMPORT void _gio4Hdr(void);
-IMPORT void _gio5Hdr(void);
-IMPORT void _gio6Hdr(void);
-IMPORT void _gio7Hdr(void);
-
-/* default handler (cmdsvc) */
-IMPORT void _defaultHdr(void);
-
-/* macros for manipulating cache/MMU/PMIC */
-#define EnbCacheMMU(x) setCacheMMU(ENB_CACHEMMU)
-#define DisCacheMMU(x) setCacheMMU(ENB_MMUONLY) /* MMU can't be turned off */
-
-/* ------------------------------------------------------------------------ */
-
-IMPORT char __loadaddr; /* monitor load address */
-IMPORT MEMSEG NoMemSeg[]; /* memory unused area */
-IMPORT W N_NoMemSeg;
-
-/*
- power management controller (DA9052) handler routines
-*/
-#define SPIPol 0x0092
-
-/* initialize SPI for PMIC communication */
-LOCAL void pmicInit(void)
-{
- out_w(SPn_MODE(SP0), 0x2700); /* 8bit, CS0, Master, CPU mode */
- out_w(SPn_TIECS(SP0), 0x000f); /* CS0: follow the specification by SPn_POL */
- out_w(SPn_POL(SP0), SPIPol);
- out_w(SPn_ENCLR(SP0), ~0); /* interrupt disable */
-
- out_w(SPn_CONTROL(SP0), 0x0100); /* start reset */
- waitUsec(10);
- out_w(SPn_CONTROL(SP0), 0x0000); /* release reset */
- out_w(SPn_CONTROL2(SP0), 0x0000);
-
- return;
-}
-
-/* wait for data of SPI for PMIC communication */
-LOCAL void pmicWait(void)
-{
- W i;
-
- for (i = 1000000; i > 0; i--) {
- if (in_w(SPn_RAW_STATUS(SP0)) & 0x0004) break;
- waitUsec(1);
- }
- if (!i) pmicInit();
-
- return;
-}
-
-/* contro CS line of SPI for PMIC communication */
-LOCAL void pmicCSassert(BOOL cs)
-{
- waitNsec(200);
- out_w(SPn_POL(SP0), SPIPol ^ (cs ? 0x0001 : 0x0000));
- waitNsec(200);
-
- return;
-}
-
-/* read PMIC register */
-EXPORT W pmicRead(W reg)
-{
- W dat;
-
- pmicCSassert(TRUE); /* CS assert */
-
- out_w(SPn_FFCLR(SP0), ~0); /* status flag is cleared */
- out_w(SPn_TX_DATA(SP0), (reg << 1) | 1); /* send register number */
- out_w(SPn_CONTROL(SP0), 0x0009); /* send start */
- pmicWait();
-
- out_w(SPn_FFCLR(SP0), ~0); /* status flag is cleared */
- out_w(SPn_CONTROL(SP0), 0x0005); /* start receive */
- pmicWait();
- dat = in_w(SPn_RX_DATA(SP0)); /* data received */
-
- pmicCSassert(FALSE); /* CS de-assert */
-
- return dat;
-}
-
-/* write PMIC register */
-EXPORT void pmicWrite(W reg, W dat)
-{
- pmicCSassert(TRUE); /* CS assert */
-
- out_w(SPn_FFCLR(SP0), ~0); /* status flag is cleared */
- out_w(SPn_TX_DATA(SP0), reg << 1); /* send register number */
- out_w(SPn_CONTROL(SP0), 0x0009); /* send start */
- pmicWait();
-
- out_w(SPn_FFCLR(SP0), ~0); /* status flag is cleared */
- out_w(SPn_TX_DATA(SP0), dat); /* send data */
- out_w(SPn_CONTROL(SP0), 0x0009); /* send start */
- pmicWait();
-
- pmicCSassert(FALSE); /* CS de-assert */
-
- return;
-}
-
-/* ------------------------------------------------------------------------ */
-
-/* basic system set up (performed during reset, and Disk Boot) */
-EXPORT void resetSystem(W boot)
-{
- MEMSEG *mp;
- UW i, va;
-
- /* obtain DipSw status */
- if (!boot) DipSw = DipSwStatus();
-
- DisCacheMMU();
-
- /* set up interrupt controller */
- out_w(IT0_IDS0, ~0); /* CPU: all interrupts disabled */
- out_w(IT0_IDS1, ~0);
- out_w(IT0_IDS2, ~0);
- out_w(IT0_IIR, ~0);
- out_w(IT3_IPI0_CLR, 0x0000003f);
- out_w(IT3_IDS0, ~0); /* DSP: all interrupts disabled */
- out_w(IT3_IDS1, ~0);
- out_w(IT3_IDS2, ~0);
- out_w(IT3_IIR, ~0);
- out_w(IT0_IPI3_CLR, 0x0000003f);
- out_w(IT0_FID, 0x00000001); /* CPU: FIQ disabled */
- out_w(GIO_IIA(GIO_L), 0); /* GPIO: interrupt disabled */
- out_w(GIO_IIA(GIO_H), 0);
- out_w(GIO_IIA(GIO_HH), 0);
- out_w(GIO_IIA(GIO_HHH), 0);
- out_w(GIO_GSW(GIO_L), 0); /* GPIO: FIQ interrupt disabled */
- out_w(GIO_GSW(GIO_H), 0);
- out_w(GIO_GSW(GIO_HH), 0);
- out_w(GIO_GSW(GIO_HHH), 0);
- out_w(IT0_LIIR, 0x0000000f); /* internal interrupt disabled */
- out_w(IT_PINV_CLR0, ~0); /* inhibit interrupt polarity inversion */
- out_w(IT_PINV_CLR1, ~0);
- out_w(IT_PINV_CLR2, ~0);
- out_w(IT0_IEN0, 0x0c000000); /* CPU: GPIO interrupt enabled */
- out_w(IT0_IEN1, 0x003c0000);
- out_w(IT0_IEN2, 0x00018000);
-
- /* power on controller initialization */
- pmicInit();
-
- /* USB power on */
- usbPower(TRUE);
-
- /* clear system common area (vector table, and SysInfo) */
- memset(&SCInfo, 0, sizeof(SysCommonInfo));
- memset(SCArea, 0, sizeof(SysCommonArea));
-
- /* if monitor is loaded into RAM, exclude the RAM area */
- mp = MemArea(MSA_OS, 1);
- va = (UW)&__loadaddr;
- if (va >= mp->top && va < mp->end) mp->end = va;
-
- /* exclude the area where ROM disk data is stored */
- va = (UW)ROMInfo->userarea;
- if (va >= mp->top && va < mp->end) mp->end = va;
-
- /* initialize system common information (SysInfo) */
- SCInfo.ramtop = (void*)mp->top;
- if (va < mp->top || va > mp->end) va = mp->end;
- SCInfo.ramend = (void*)va;
-
- /* set up EIT vectors */
- /* we do not need _defaultHdr absolutely, but just in case set it up */
- SCArea->intvec[EIT_DEFAULT] = _defaultHdr; /* default handler */
- SCArea->intvec[EIT_UNDEF] = _defaultHdr; /* undefined instruction */
- SCArea->intvec[SWI_MONITOR] = _defaultHdr; /* SWI - monitor SVC */
- SCArea->intvec[EIT_IRQ(26)] = _gio6Hdr; /* GPIO branch */
- SCArea->intvec[EIT_IRQ(27)] = _gio7Hdr;
- SCArea->intvec[EIT_IRQ(50)] = _gio0Hdr;
- SCArea->intvec[EIT_IRQ(51)] = _gio1Hdr;
- SCArea->intvec[EIT_IRQ(52)] = _gio2Hdr;
- SCArea->intvec[EIT_IRQ(53)] = _gio3Hdr;
- SCArea->intvec[EIT_IRQ(79)] = _gio4Hdr;
- SCArea->intvec[EIT_IRQ(80)] = _gio5Hdr;
- SCArea->intvec[EIT_GPIO(8)] = _defaultHdr; /* abort switch */
-
- /* set up initial page table */
- for (i = 0; i < N_MemSeg; ++i) {
- mp = &MemSeg[i];
- if (!mp->pa) continue;
-
- /* FlashROM has already been mapped, and so do not touch it */
- if (mp->attr == MSA_FROM) continue;
-
- /* set up in unit of section (1MB) */
- for ( va = (mp->top & 0xfff00000);
- va != ((mp->end + 0x000fffff) & 0xfff00000);
- va += 0x00100000 ) {
- TopPageTable[va / 0x00100000] =
- ((mp->pa & 0xfff00000) + va) |
- (mp->pa & 0x000fffff);
- }
- }
-
- for (i = 0; i < N_NoMemSeg; ++i) {
- mp = &NoMemSeg[i];
-
- /* set up in unit of section (1MB) */
- for ( va = (mp->top & 0xfff00000);
- va != ((mp->end + 0x000fffff) & 0xfff00000);
- va += 0x00100000 ) {
- TopPageTable[va / 0x00100000] = 0;
- }
- }
-
- DSB();
- Asm("mcr p15, 0, %0, cr8, c7, 0":: "r"(0)); /* I/D TLB invalidate */
- Asm("mcr p15, 0, %0, cr7, c5, 6":: "r"(0)); /* invalidate BTC */
- DSB();
- ISB();
-
- EnbCacheMMU();
-
- return;
-}
-
-/* ------------------------------------------------------------------------ */
-
-/*
- system termination: reset / system power off
- reset 0 power off
- -1 reboot
- 0xaa55 halt boot and power off
-*/
-EXPORT void sysExit(W reset)
-{
- DisCacheMMU();
-
- /* after this point, delay such as waitUsec() spends more time than the number indicates // */
-
- /* LED off */
- cpuLED(0x00);
-
- /* all interrupts disabled */
- out_w(IT0_IDS0, ~0); /* CPU: all interrupts disabled */
- out_w(IT0_IDS1, ~0);
- out_w(IT0_IDS2, ~0);
- out_w(IT3_IPI0_CLR, 0x0000003f);
- out_w(IT3_IDS0, ~0); /* DSP: all interrupts disabled */
- out_w(IT3_IDS1, ~0);
- out_w(IT3_IDS2, ~0);
- out_w(IT0_IPI3_CLR, 0x0000003f);
- out_w(IT0_FID, 0x00000001); /* FIQ disabled */
- out_w(IT0_LIIR, 0x0000000f); /* internal interrupt disabled */
-
- /* power on controller initialization */
- pmicInit();
-
- /* USB power off */
- usbPower(FALSE);
-
- if (reset >= 0) powerOff();
-
- /* reset start */
- resetStart();
-}
-
-/* ------------------------------------------------------------------------ */
diff --git a/tkernel_source/monitor/hwdepend/tef_em1d/src/waitusec.c b/tkernel_source/monitor/hwdepend/tef_em1d/src/waitusec.c
deleted file mode 100644
index 8ffac07..0000000
--- a/tkernel_source/monitor/hwdepend/tef_em1d/src/waitusec.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * waitusec.c
- *
- * EM1-D512: micro wait
- */
-
-#include "sysdepend.h"
-#include <arm/em1d512.h>
-
-LOCAL UW delay64us; /* wait for 64 microsec */
-
-/*
- * wait for nanoseconds
- */
-EXPORT void waitNsec(_UW nsec)
-{
- for (nsec = nsec * delay64us / 64000; nsec > 0; nsec--);
-
- return;
-}
-
-/*
- * wait for microseconds
- */
-EXPORT void waitUsec(_UW usec)
-{
- for (usec = usec * delay64us / 64; usec > 0; usec--);
-
- return;
-}
-
-/*
- * wait for milliseconds
- */
-EXPORT void waitMsec(UW msec)
-{
- while (msec-- > 0) waitUsec(1000);
-
- return;
-}
-
-/* ------------------------------------------------------------------------ */
-
-/*
- * setting up the initial count for micro-wait()
- */
-EXPORT void setupWaitUsec(void)
-{
- UW t0, t1, t2;
-
-#define MAX_CNT (ACPU_CLK * 64 / 10) /* 1 Clock */
-#define MIN_CNT (ACPU_CLK * 64 / 1280) /* 128 Clock */
-
- /* use TI0 timer, and assume clock is PLL3 / 8 */
- out_w(Txx_OP(TI0), 0); /* Timer stop, count clear */
- while (in_w(Txx_RCR(TI0)));
-
- out_w(Txx_SET(TI0), 0xffffffff); /* maximum count */
- out_w(Txx_OP(TI0), 0x00000003); /* Timer start */
-
- delay64us = 64;
- waitUsec(1000); /* wait for a while until things settle down */
-
- t0 = in_w(Txx_RCR(TI0));
- waitUsec(1000);
- t1 = in_w(Txx_RCR(TI0));
- waitUsec(3000);
- t2 = in_w(Txx_RCR(TI0));
-
- out_w(Txx_OP(TI0),0); /* Timer stop, count clear */
- while (in_w(Txx_RCR(TI0)));
-
- t2 -= t1; /* count for 3000 times */
- t1 -= t0; /* count for 1000 times */
- t2 -= t1; /* count for 2000 times */
-
- /*
- * calculate the count for 64 microsec
- *
- * 2000 loops x timer clock [MHz] x 64 [microsec]
- * delay64us = ------------------------------------------------
- * t2
- *
- * * considering the representation of PLL3_CLK (1/1000MHz unit), and setting of pre scaler,
- * it can be written down as follows.
- *
- * 2 loops x PLL3_CLK [1/1000MHz] x 8 [microsec]
- * delay64us = -------------------------------------------
- * t2
- *
- */
- delay64us = (t2 == 0) ? MAX_CNT : ((2 * PLL3_CLK * 8) / t2);
- if (delay64us > MAX_CNT) delay64us = MAX_CNT;
- else if (delay64us < MIN_CNT) delay64us = MIN_CNT;
-
- return;
-}
-
diff --git a/tkernel_source/monitor/include/arm/cpudepend.h b/tkernel_source/monitor/include/arm/cpudepend.h
deleted file mode 100644
index 4cbb714..0000000
--- a/tkernel_source/monitor/include/arm/cpudepend.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * cpudepend.h
- *
- * ARM-related definitions
- */
-
-#ifndef __MONITOR_ARM_CPUDEPEND_H__
-#define __MONITOR_ARM_CPUDEPEND_H__
-
-#include <machine.h>
-
-/*
- * monitor stack area
- * stack area is from &__stack_top to &__stack_bottom
- * initial stack pointer = &__stack_bottom
- */
-IMPORT UB __stack_top, __stack_bottom;
-
-/*
- * first level page table
- */
-IMPORT UW* const TopPageTable; /* location of page table */
-#define N_PageTableEntry 0x1000 /* number of entries */
-
-/*
- * address conversion to non-cached and cached area
- * in the case of ARM, all address have the same cache mode, and hence
- * return as it is.
- */
-#define NOCACHE_ADDR(p) (p)
-#define CACHE_ADDR(p) (p)
-
-/*
- * I/O port access functions
- */
-Inline void out_w( INT port, UW data )
-{
- *(_UW*)port = data;
-}
-Inline void out_h( INT port, UH data )
-{
- *(_UH*)port = data;
-}
-Inline void out_b( INT port, UB data )
-{
- *(_UB*)port = data;
-}
-
-Inline UW in_w( INT port )
-{
- return *(_UW*)port;
-}
-Inline UH in_h( INT port )
-{
- return *(_UH*)port;
-}
-Inline UB in_b( INT port )
-{
- return *(_UB*)port;
-}
-
-/*
- * value of control register (r1) of system control coprocessor cp15
- */
-#if CPU_ARM1176
-#define MASK_CACHEMMU (0xFFFFCC78) /* V,I,R,S,C,A,M (B = 0) */
-#define VALID_CACHEMMU (0x3307) /* B = 0 */
-#define DIS_CACHEMMU (0x0000) /* I=0,R=0,S=0,C=0,A=0,M=0 */
-#define DIS_CACHEONLY (0x0001) /* I=0,R=0,S=0,C=0,A=0,M=1 */
-#define ENB_CACHEMMU (0x1007) /* I=1,R=0,S=0,C=1,A=1,M=1 */
-#define ENB_MMUONLY (0x0003) /* I=0,R=0,S=0,C=0,A=1,M=1 */
-#endif
-
-/*
- * references registers under monitor control
- * references the value of registers at the time of monitor entry.
- */
-IMPORT UW getCP15( W reg, W opcd ); /* CP15 register CRn: reg, Op2: opcd */
-IMPORT UW getCurPCX( void ); /* PC register (raw value) */
-IMPORT UW getCurCPSR( void ); /* CPSR register */
-
-#endif /* __MONITOR_ARM_CPUDEPEND_H__ */
diff --git a/tkernel_source/monitor/include/arm/em1d512.h b/tkernel_source/monitor/include/arm/em1d512.h
deleted file mode 100644
index b1eb46f..0000000
--- a/tkernel_source/monitor/include/arm/em1d512.h
+++ /dev/null
@@ -1,464 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * em1d.h
- *
- * EMMA Mobile(TM)1-D register definitions (excerpt)
- *
- * * this is included from assembler program source files
- */
-
-#ifndef __MONITOR_ARM_EM1D_H__
-#define __MONITOR_ARM_EM1D_H__
-
-#include <tk/sysdef.h>
-
-#define AB0Base 0x2fff0000
-#define AB0_FLASHCOMSET (AB0Base + 0x0000)
-#define AB0_FLASHCOMLATCH (AB0Base + 0x0004)
-#define AB0_FLASHCOMADD0 (AB0Base + 0x0010)
-#define AB0_FLASHCOMDATA0 (AB0Base + 0x0014)
-#define AB0_FLASHCOMADD1 (AB0Base + 0x0018)
-#define AB0_FLASHCOMDATA1 (AB0Base + 0x001c)
-#define AB0_FLASHCLKCTRL (AB0Base + 0x0080)
-#define AB0_FLA_RCLK_DLY (AB0Base + 0x0084)
-#define AB0_WAIT_STATUS (AB0Base + 0x0090)
-#define AB0_CSnBASEADD(n) (AB0Base + 0x0100 + 0x0010 * (n))
-#define AB0_CSnBITCOMP(n) (AB0Base + 0x0104 + 0x0010 * (n))
-#define AB0_CSnWAITCTRL(n) (AB0Base + 0x0200 + 0x0020 * (n))
-#define AB0_CSnWAITCTRL_W(n) (AB0Base + 0x0204 + 0x0020 * (n))
-#define AB0_CSnREADCTRL(n) (AB0Base + 0x0208 + 0x0020 * (n))
-#define AB0_CSnWAIT_MASK(n) (AB0Base + 0x020c + 0x0020 * (n))
-#define AB0_CSnCONTROL(n) (AB0Base + 0x0210 + 0x0020 * (n))
-#define AB0_CSnFLASHRCR(n) (AB0Base + 0x0214 + 0x0020 * (n))
-#define AB0_CSnFLASHWCR(n) (AB0Base + 0x0218 + 0x0020 * (n))
-#define AB0_CSnWAITCTRL2(n) (AB0Base + 0x0300 + 0x0020 * (n))
-#define AB0_CSnWAITCTRL_W2(n) (AB0Base + 0x0304 + 0x0020 * (n))
-#define AB0_CSnREADCTRL2(n) (AB0Base + 0x0308 + 0x0020 * (n))
-#define AB0_CSnWAIT_MASK2(n) (AB0Base + 0x030c + 0x0020 * (n))
-#define AB0_CSnCONTROL2(n) (AB0Base + 0x0310 + 0x0020 * (n))
-#define AB0_CSnFLASHRCR2(n) (AB0Base + 0x0314 + 0x0020 * (n))
-#define AB0_CSnFLASHWCR2(n) (AB0Base + 0x0318 + 0x0020 * (n))
-
-#define LCDBase 0x40270000
-#define LCD_CONTROL (LCDBase + 0x0000)
-#define LCD_QOS (LCDBase + 0x0004)
-#define LCD_DATAREQ (LCDBase + 0x0008)
-#define LCD_LCDOUT (LCDBase + 0x0010)
-#define LCD_BUSSEL (LCDBase + 0x0014)
-#define LCD_STATUS (LCDBase + 0x0018)
-#define LCD_BACKCOLOR (LCDBase + 0x001c)
-#define LCD_AREAADR (LCDBase + 0x0020)
-#define LCD_HOFFSET (LCDBase + 0x0024)
-#define LCD_IFORMAT (LCDBase + 0x0028)
-#define LCD_RESIZE (LCDBase + 0x002c)
-#define LCD_HTOTAL (LCDBase + 0x0030)
-#define LCD_HAREA (LCDBase + 0x0034)
-#define LCD_HEDGE1 (LCDBase + 0x0038)
-#define LCD_HEDGE2 (LCDBase + 0x003c)
-#define LCD_VTOTAL (LCDBase + 0x0040)
-#define LCD_VAREA (LCDBase + 0x0044)
-#define LCD_VEDGE1 (LCDBase + 0x0048)
-#define LCD_VEDGE2 (LCDBase + 0x004c)
-#define LCD_INTSTATUS (LCDBase + 0x0060)
-#define LCD_INTRAWSTATUS (LCDBase + 0x0064)
-#define LCD_INTENSET (LCDBase + 0x0068)
-#define LCD_INTENCLR (LCDBase + 0x006c)
-#define LCD_INTFFCLR (LCDBase + 0x0070)
-#define LCD_FRAMECNT (LCDBase + 0x0074)
-
-#define UARTnBase(n) (0x50000000 + 0x00010000 * (n))
-#define UART0 0x00
-#define UART1 0x01
-#define UART2 0x02
-/* omitted */
-
-#define SDIxBase(x) (0x50050000 + 0x00010000 * (x))
-#define SDIA 0x00
-#define SDIB 0x01
-#define SDIC 0x04
-#define SDIx_CMD(x) (SDIxBase(x) + 0x0000)
-#define SDIx_PORT(x) (SDIxBase(x) + 0x0004)
-#define SDIx_ARG0(x) (SDIxBase(x) + 0x0008)
-#define SDIx_ARG1(x) (SDIxBase(x) + 0x000c)
-#define SDIx_STOP(x) (SDIxBase(x) + 0x0010)
-#define SDIx_SECCNT(x) (SDIxBase(x) + 0x0014)
-#define SDIx_RSP0(x) (SDIxBase(x) + 0x0018)
-#define SDIx_RSP1(x) (SDIxBase(x) + 0x001c)
-#define SDIx_RSP2(x) (SDIxBase(x) + 0x0020)
-#define SDIx_RSP3(x) (SDIxBase(x) + 0x0024)
-#define SDIx_RSP4(x) (SDIxBase(x) + 0x0028)
-#define SDIx_RSP5(x) (SDIxBase(x) + 0x002c)
-#define SDIx_RSP6(x) (SDIxBase(x) + 0x0030)
-#define SDIx_RSP7(x) (SDIxBase(x) + 0x0034)
-#define SDIx_INFO1(x) (SDIxBase(x) + 0x0038)
-#define SDIx_INFO2(x) (SDIxBase(x) + 0x003c)
-#define SDIx_INFO1_MASK(x) (SDIxBase(x) + 0x0040)
-#define SDIx_INFO2_MASK(x) (SDIxBase(x) + 0x0044)
-#define SDIx_CLK_CTRL(x) (SDIxBase(x) + 0x0048)
-#define SDIx_SIZE(x) (SDIxBase(x) + 0x004c)
-#define SDIx_OPTION(x) (SDIxBase(x) + 0x0050)
-#define SDIx_ERR_STS1(x) (SDIxBase(x) + 0x0058)
-#define SDIx_ERR_STS2(x) (SDIxBase(x) + 0x005c)
-#define SDIx_BUF0(x) (SDIxBase(x) + 0x0060)
-#define SDIx_SDIO_MODE(x) (SDIxBase(x) + 0x0068)
-#define SDIx_SDIO_INFO1(x) (SDIxBase(x) + 0x006c)
-#define SDIx_SDIO_INFO1_MASK(x) (SDIxBase(x) + 0x0070)
-#define SDIx_CC_EXT_MODE(x) (SDIxBase(x) + 0x01b0)
-#define SDIx_SOFT_RST(x) (SDIxBase(x) + 0x01c0)
-#define SDIx_VERSION(x) (SDIxBase(x) + 0x01c4)
-#define SDIx_USER(x) (SDIxBase(x) + 0x0200)
-#define SDIx_USER2(x) (SDIxBase(x) + 0x0204)
-#define SDIx_DMA(x) (SDIxBase(x) + 0x0300)
-
-#define AB1Base 0x50070000
-#define AB1_ERROR (AB1Base + 0x0000)
-#define AB1_GENERAL (AB1Base + 0x0004)
-#define AB1_DEBUG0 (AB1Base + 0x0008)
-
-#define USBBase 0x60000000
-/* omitted */
-
-#define TimerBase(x) (0xc0000000 + 0x00000100 * (x))
-#define TI0 0x00
-#define TI1 0x01
-#define TI2 0x02
-#define TI3 0x03
-#define TW0 0x10
-#define TW1 0x11
-#define TW2 0x12
-#define TW3 0x13
-#define TG0 0x20
-#define TG1 0x21
-#define TG2 0x22
-#define TG3 0x23
-#define TG4 0x24
-#define TG5 0x25
-#define Txx_OP(x) (TimerBase(x) + 0x0000)
-#define Txx_CLR(x) (TimerBase(x) + 0x0004)
-#define Txx_SET(x) (TimerBase(x) + 0x0008)
-#define Txx_RCR(x) (TimerBase(x) + 0x000c)
-#define Txx_SCLR(x) (TimerBase(x) + 0x0014)
-
-#define AINTBase 0xc0020000
-#define IT0_IEN0 (AINTBase + 0x0000)
-#define IT0_IEN1 (AINTBase + 0x0004)
-#define IT0_IDS0 (AINTBase + 0x0008)
-#define IT0_IDS1 (AINTBase + 0x000c)
-#define IT0_RAW0 (AINTBase + 0x0010)
-#define IT0_RAW1 (AINTBase + 0x0014)
-#define IT0_MST0 (AINTBase + 0x0018)
-#define IT0_MST1 (AINTBase + 0x001c)
-#define IT0_IIR (AINTBase + 0x0024)
-#define IT0_IPI3_SET (AINTBase + 0x003c)
-#define IT3_IPI0_CLR (AINTBase + 0x005c)
-#define IT0_FIE (AINTBase + 0x0080)
-#define IT0_FID (AINTBase + 0x0084)
-#define IT0_IEN2 (AINTBase + 0x0100)
-#define IT0_IDS2 (AINTBase + 0x0104)
-#define IT0_RAW2 (AINTBase + 0x0108)
-#define IT0_MST2 (AINTBase + 0x010c)
-#define IT_PINV_SET0 (AINTBase + 0x0300)
-#define IT_PINV_SET1 (AINTBase + 0x0304)
-#define IT_PINV_SET2 (AINTBase + 0x0308)
-#define IT_PINV_CLR0 (AINTBase + 0x0310)
-#define IT_PINV_CLR1 (AINTBase + 0x0314)
-#define IT_PINV_CLR2 (AINTBase + 0x0318)
-#define IT0_LIIS (AINTBase + 0x0320)
-#define IT0_LIIR (AINTBase + 0x0324)
-#define IT3_IEN0 (AINTBase + 0xc000)
-#define IT3_IEN1 (AINTBase + 0xc004)
-#define IT3_IDS0 (AINTBase + 0xc008)
-#define IT3_IDS1 (AINTBase + 0xc00c)
-#define IT3_RAW0 (AINTBase + 0xc010)
-#define IT3_RAW1 (AINTBase + 0xc014)
-#define IT3_MST0 (AINTBase + 0xc018)
-#define IT3_MST1 (AINTBase + 0xc01c)
-#define IT3_IIR (AINTBase + 0xc024)
-#define IT3_IPI0_SET (AINTBase + 0xc030)
-#define IT0_IPI3_CLR (AINTBase + 0xc050)
-#define ID_VBS (AINTBase + 0xc090)
-#define ID_CLR (AINTBase + 0xc094)
-#define IT3_IEN2 (AINTBase + 0xc100)
-#define IT3_IDS2 (AINTBase + 0xc104)
-#define IT3_RAW2 (AINTBase + 0xc108)
-#define IT3_MST2 (AINTBase + 0xc10c)
-
-#define ASINTBase 0xcc010000
-#define IT0_IENS0 (ASINTBase + 0xe200)
-#define IT0_IENS1 (ASINTBase + 0xe204)
-#define IT0_IENS2 (ASINTBase + 0xe208)
-#define IT0_IDSS0 (ASINTBase + 0xe20c)
-#define IT0_IDSS1 (ASINTBase + 0xe210)
-#define IT0_IDSS2 (ASINTBase + 0xe214)
-
-#define GIOBase(x) (0xc0050000 + 0x00000040 * (x))
-#define GIO_L 0x00
-#define GIO_H 0x01
-#define GIO_HH 0x02
-#define GIO_HHH 0x08
-#define GIO_E1(x) (GIOBase(x) + 0x0000)
-#define GIO_E0(x) (GIOBase(x) + 0x0004)
-#define GIO_EM(x) (GIOBase(x) + 0x0004)
-#define GIO_OL(x) (GIOBase(x) + 0x0008)
-#define GIO_OH(x) (GIOBase(x) + 0x000c)
-#define GIO_I(x) (GIOBase(x) + 0x0010)
-#define GIO_IIA(x) (GIOBase(x) + 0x0014)
-#define GIO_IEN(x) (GIOBase(x) + 0x0018)
-#define GIO_IDS(x) (GIOBase(x) + 0x001c)
-#define GIO_IIM(x) (GIOBase(x) + 0x001c)
-#define GIO_RAW(x) (GIOBase(x) + 0x0020)
-#define GIO_MST(x) (GIOBase(x) + 0x0024)
-#define GIO_IIR(x) (GIOBase(x) + 0x0028)
-#define GIO_GSW(x) (GIOBase(x) + 0x003c)
-#define GIO_IDT0(x) (GIOBase(x) + 0x0100)
-#define GIO_IDT1(x) (GIOBase(x) + 0x0104)
-#define GIO_IDT2(x) (GIOBase(x) + 0x0108)
-#define GIO_IDT3(x) (GIOBase(x) + 0x010c)
-#define GIO_RAWBL(x) (GIOBase(x) + 0x0110)
-#define GIO_RAWBH(x) (GIOBase(x) + 0x0114)
-#define GIO_IRBL(x) (GIOBase(x) + 0x0118)
-#define GIO_IRBH(x) (GIOBase(x) + 0x011c)
-
-#define MEMCBase 0xc00a0000
-#define MEMC_CACHE_MODE (MEMCBase + 0x0000)
-#define MEMC_DEGFUN (MEMCBase + 0x0008)
-#define MEMC_INTSTATUS_A (MEMCBase + 0x0014)
-#define MEMC_INTRAWSTATUS_A (MEMCBase + 0x0018)
-#define MEMC_INTENSET_A (MEMCBase + 0x001c)
-#define MEMC_INTENCLR_A (MEMCBase + 0x0020)
-#define MEMC_INTFFCLR_A (MEMCBase + 0x0024)
-#define MEMC_ERRMID (MEMCBase + 0x0068)
-#define MEMC_ERRADR (MEMCBase + 0x006c)
-#define MEMC_REQSCH (MEMCBase + 0x1000)
-#define MEMC_DDR_CONFIGF (MEMCBase + 0x2000)
-#define MEMC_DDR_CONFIGA1 (MEMCBase + 0x2004)
-#define MEMC_DDR_CONFIGA2 (MEMCBase + 0x2008)
-#define MEMC_DDR_CONFIGC1 (MEMCBase + 0x200c)
-#define MEMC_DDR_CONFIGC2 (MEMCBase + 0x2010)
-#define MEMC_DDR_CONFIGR1 (MEMCBase + 0x2014)
-#define MEMC_DDR_CONFIGR2 (MEMCBase + 0x2018)
-#define MEMC_DDR_CONFIGR3 (MEMCBase + 0x201c)
-#define MEMC_DDR_CONFIGT1 (MEMCBase + 0x2020)
-#define MEMC_DDR_CONFIGT2 (MEMCBase + 0x2024)
-#define MEMC_DDR_CONFIGT3 (MEMCBase + 0x2028)
-#define MEMC_DDR_STATE8 (MEMCBase + 0x202c)
-
-#define PMUBase 0xc0100000
-#define PMU_PC (PMUBase + 0x0004)
-#define PMU_START (PMUBase + 0x0008)
-#define PMU_POWER_ON_PC (PMUBase + 0x0030)
-#define PMU_WDT_COUNT_EN (PMUBase + 0x0060)
-#define PMU_WDT_COUNT_LMT (PMUBase + 0x0064)
-#define PMU_INT_HANDLER_PC (PMUBase + 0x0068)
-#define PMU_PSR (PMUBase + 0x0070)
-#define PMU_TRIG_STATUS (PMUBase + 0x0074)
-#define PMU_REGA (PMUBase + 0x0078)
-#define PMU_REGB (PMUBase + 0x007c)
-#define PMU_INTSTATUS_A (PMUBase + 0x0080)
-#define PMU_INTRAWSTATUS_A (PMUBase + 0x0084)
-#define PMU_INTENSET_A (PMUBase + 0x0088)
-#define PMU_INTENCLR_A (PMUBase + 0x008c)
-#define PMU_INTFFCLR_A (PMUBase + 0x0090)
-#define PMU_PCERR (PMUBase + 0x00a8)
-#define PMU_CMD_BUF_RAM (PMUBase + 0x1000)
-#define PMU_CMD_BUF_FF (PMUBase + 0x2000)
-
-#define ASMUBase 0xc0110000
-#define RESETCTRL0 (ASMUBase + 0x0000)
-#define RESETREQ0 (ASMUBase + 0x0004)
-#define RESETREQ0ENA (ASMUBase + 0x0008)
-#define RESETREQ1 (ASMUBase + 0x000c)
-#define RESETREQ1ENA (ASMUBase + 0x0010)
-#define RESETREQ2 (ASMUBase + 0x0018)
-#define RESETREQ2ENA (ASMUBase + 0x001c)
-#define WDT_INT_RESET (ASMUBase + 0x0020)
-#define RESET_PCLK_COUNT (ASMUBase + 0x0024)
-#define AUTO_MODE_EN (ASMUBase + 0x007c)
-#define CLK_MODE_SEL (ASMUBase + 0x0080)
-#define PLL1CTRL0 (ASMUBase + 0x0084)
-#define PLL1CTRL1 (ASMUBase + 0x0088)
-#define PLL2CTRL0 (ASMUBase + 0x008c)
-#define PLL2CTRL1 (ASMUBase + 0x0090)
-#define PLL3CTRL0 (ASMUBase + 0x0094)
-#define PLL3CTRL1 (ASMUBase + 0x0098)
-#define PLLLOCKTIME (ASMUBase + 0x009c)
-#define AUTO_PLL_STANDBY (ASMUBase + 0x00a8)
-#define PLLVDDWAIT (ASMUBase + 0x00b4)
-#define CLKSTOPSIG_ST (ASMUBase + 0x00c4)
-#define CLK32_STATUS (ASMUBase + 0x00c8)
-#define POWER_RECORD (ASMUBase + 0x00cc)
-#define ASMU_INT_STATUS (ASMUBase + 0x00d0)
-#define ASMU_INT_RAW_STATUS (ASMUBase + 0x00d4)
-#define ASMU_INT_ENSET (ASMUBase + 0x00d8)
-#define ASMU_INT_ENCLR (ASMUBase + 0x00dc)
-#define ASMU_INT_ENMON (ASMUBase + 0x00e0)
-#define ASMU_INT_CLEAR (ASMUBase + 0x00e4)
-#define NORMALA_DIV (ASMUBase + 0x00f0)
-#define NORMALB_DIV (ASMUBase + 0x00f4)
-#define NORMALC_DIV (ASMUBase + 0x00f8)
-#define NORMALD_DIV (ASMUBase + 0x00fc)
-#define ECONOMY_DIV (ASMUBase + 0x0100)
-#define STANDBY_DIV (ASMUBase + 0x0104)
-#define POWERON_DIV (ASMUBase + 0x0108)
-#define DIVSP0SCLK (ASMUBase + 0x0118)
-#define DIVSP1SCLK (ASMUBase + 0x011c)
-#define DIVSP2SCLK (ASMUBase + 0x0120)
-#define DIVMEMCRCLK (ASMUBase + 0x0128)
-#define DIVCAMSCLK (ASMUBase + 0x012c)
-#define DIVLCDLCLK (ASMUBase + 0x0130)
-#define DIVIICSCLK (ASMUBase + 0x0134)
-#define TI0TIN_SEL (ASMUBase + 0x0138)
-#define TI1TIN_SEL (ASMUBase + 0x013c)
-#define TI2TIN_SEL (ASMUBase + 0x0140)
-#define TI3TIN_SEL (ASMUBase + 0x0144)
-#define TIGnTIN_SEL (ASMUBase + 0x0148)
-#define DIVTIMTIN (ASMUBase + 0x014c)
-#define DIVMWISCLK (ASMUBase + 0x0150)
-#define DIVDMATCLK (ASMUBase + 0x0154)
-#define DIVU70SCLK (ASMUBase + 0x0158)
-#define DIVU71SCLK (ASMUBase + 0x015c)
-#define DIVU72SCLK (ASMUBase + 0x0160)
-#define DIVPM0SCLK (ASMUBase + 0x016c)
-#define DIVPM1SCLK (ASMUBase + 0x0170)
-#define DIVREFCLK (ASMUBase + 0x0178)
-#define DIVPWMPWCLK (ASMUBase + 0x0184)
-#define AHBCLKCTRL0 (ASMUBase + 0x01a0)
-#define AHBCLKCTRL1 (ASMUBase + 0x01a4)
-#define APBCLKCTRL0 (ASMUBase + 0x01a8)
-#define APBCLKCTRL1 (ASMUBase + 0x01ac)
-#define CLKCTRL (ASMUBase + 0x01b0)
-#define GCLKCTRL0 (ASMUBase + 0x01b4)
-#define GCLKCTRL0ENA (ASMUBase + 0x01b8)
-#define GCLKCTRL1 (ASMUBase + 0x01bc)
-#define GCLKCTRL1ENA (ASMUBase + 0x01c0)
-#define GCLKCTRL2 (ASMUBase + 0x01c4)
-#define GCLKCTRL2ENA (ASMUBase + 0x01c8)
-#define GCLKCTRL3 (ASMUBase + 0x01cc)
-#define GCLKCTRL3ENA (ASMUBase + 0x01d0)
-#define AUTO_FRQ_CHANGE (ASMUBase + 0x01dc)
-#define AUTO_FRQ_MASK0 (ASMUBase + 0x01e0)
-#define AUTO_FRQ_MASK1 (ASMUBase + 0x01e4)
-#define DFS_HALFMODE (ASMUBase + 0x01e8)
-#define FLA_CLK_DLY (ASMUBase + 0x01f0)
-#define MEMCCLK270_SEL (ASMUBase + 0x01fc)
-#define ASMU_BGCTRL (ASMUBase + 0x0208)
-#define QR_ENA (ASMUBase + 0x0220)
-#define QR_CLKDIV (ASMUBase + 0x0224)
-#define FAKE_MODE (ASMUBase + 0x0238)
-#define POWERSW_STATUS (ASMUBase + 0x023c)
-#define POWERSW_ENA (ASMUBase + 0x0240)
-#define L1_POWERSW (ASMUBase + 0x0244)
-#define ACPU_POWERSW (ASMUBase + 0x0248)
-#define ADSP_POWERSW (ASMUBase + 0x024c)
-#define ACPU_BUB (ASMUBase + 0x0254)
-#define ADSP_BUB (ASMUBase + 0x0258)
-#define POWERSW_ACTRL_EN (ASMUBase + 0x025c)
-#define LOG1SW_ACTRL (ASMUBase + 0x0260)
-#define ADSPSW_ACTRL (ASMUBase + 0x0264)
-#define L1_BUZ (ASMUBase + 0x0268)
-#define L1_BUZ2 (ASMUBase + 0x026c)
-#define ACPUBUFTYPE (ASMUBase + 0x0288)
-#define ADSPUBUFTYPE (ASMUBase + 0x028c)
-#define HXBBUFTYPE (ASMUBase + 0x0290)
-#define STATUS_RECORD(n) (ASMUBase + 0x0320 + 0x004 *(n))
-#define ACPU_INIT (ASMUBase + 0x0360)
-#define AB1_U70WAITCTRL (ASMUBase + 0x03c0)
-#define AB1_U71WAITCTRL (ASMUBase + 0x03c4)
-#define AB1_U72WAITCTRL (ASMUBase + 0x03c8)
-#define AB1_IIC2WAITCTRL (ASMUBase + 0x03cc)
-#define AB1_IICWAITCTRL (ASMUBase + 0x03d0)
-#define AB1_U70READCTRL (ASMUBase + 0x03d4)
-#define AB1_U71READCTRL (ASMUBase + 0x03d8)
-#define AB1_U72READCTRL (ASMUBase + 0x03dc)
-#define AB1_IIC2READCTRL (ASMUBase + 0x03e0)
-#define AB1_IICREADCTRL (ASMUBase + 0x03e4)
-#define AB1_SDIBWAITCTRL (ASMUBase + 0x03e8)
-#define AB1_SDIBREADCTRL (ASMUBase + 0x03ec)
-#define AB1_SDICWAITCTRL (ASMUBase + 0x03f0)
-#define AB1_SDICREADCTRL (ASMUBase + 0x03f4)
-#define FLASHCLK_CTRL (ASMUBase + 0x0494)
-#define L2_POWERSW_BUZ (ASMUBase + 0x0500)
-#define LOG2SW_ACTRLEN (ASMUBase + 0x0504)
-#define LOG2SW_ACTRL (ASMUBase + 0x0508)
-#define L3_POWERSW_BUZ (ASMUBase + 0x050c)
-#define LOG3SW_ACTRLEN (ASMUBase + 0x0510)
-#define LOG3SW_ACTRL (ASMUBase + 0x0514)
-#define PLL_STATUS (ASMUBase + 0x0520)
-#define IO_L0_LM_BUZ (ASMUBase + 0x0814)
-#define RESETREQ3 (ASMUBase + 0x083c)
-#define RESETREQ3ENA (ASMUBase + 0x0840)
-#define APBCLKCTRL2 (ASMUBase + 0x0848)
-#define GCLKCTRL4 (ASMUBase + 0x084c)
-#define GCLKCTRL4ENA (ASMUBase + 0x0850)
-#define AUTO_FRQ_MASK3 (ASMUBase + 0x0860)
-#define DFS_FIFOMODE (ASMUBase + 0x0864)
-#define DFS_FIFO_REQMASK (ASMUBase + 0x0868)
-#define LCD_FIFOTHRESHOLD (ASMUBase + 0x086c)
-#define CAM_FIFOTHRESHOLD (ASMUBase + 0x0870)
-#define CAM_SAFE_RESET (ASMUBase + 0x0878)
-#define DTV_SAFE_RESET (ASMUBase + 0x0880)
-#define USB_SAFE_RESET (ASMUBase + 0x0884)
-#define CLKCTRL1 (ASMUBase + 0x088c)
-#define AB1_SDIAWAITCTRL (ASMUBase + 0x0890)
-#define AB1_SDIAREADCTRL (ASMUBase + 0x0894)
-#define MEMC_HAND_SHAKE_FAKE (ASMUBase + 0x08a0)
-#define SEL_BIGWEST (ASMUBase + 0x08b8)
-
-#define SPnBase(n) (0xc0120000 + 0x00010000 * (n))
-#define SP0 0x00
-#define SP1 0x01
-#define SPn_MODE(n) (SPnBase(n) + 0x0000)
-#define SPn_POL(n) (SPnBase(n) + 0x0004)
-#define SPn_CONTROL(n) (SPnBase(n) + 0x0008)
-#define SPn_TX_DATA(n) (SPnBase(n) + 0x0010)
-#define SPn_RX_DATA(n) (SPnBase(n) + 0x0014)
-#define SPn_STATUS(n) (SPnBase(n) + 0x0018)
-#define SPn_RAW_STATUS(n) (SPnBase(n) + 0x001c)
-#define SPn_ENSET(n) (SPnBase(n) + 0x0020)
-#define SPn_ENCLR(n) (SPnBase(n) + 0x0024)
-#define SPn_FFCLR(n) (SPnBase(n) + 0x0028)
-#define SPn_CONTROL2(n) (SPnBase(n) + 0x0034)
-#define SPn_TIECS(n) (SPnBase(n) + 0x0038)
-
-#define CHGREGBase 0xc0140000
-#define CHG_BOOT_MODE (CHGREGBase + 0x0000)
-#define CHG_L1_HOLD (CHGREGBase + 0x0004)
-#define CHG_LSI_REVISION (CHGREGBase + 0x0010)
-#define CHG_CTRL_SDINT (CHGREGBase + 0x0104)
-#define CHG_CTRL_AB0_BOOT (CHGREGBase + 0x0108)
-#define CHG_CTRL_OSC (CHGREGBase + 0x0110)
-#define CHG_PINSEL_G(n) (CHGREGBase + 0x0200 + 0x0004 * ((n) / 16))
-#define CHG_PINSEL_SP0 (CHGREGBase + 0x0280)
-#define CHG_PINSEL_DTV (CHGREGBase + 0x0284)
-#define CHG_PINSEL_SD0 (CHGREGBase + 0x0288)
-#define CHG_PINSEL_SD1 (CHGREGBase + 0x028c)
-#define CHG_PINSEL_IIC2 (CHGREGBase + 0x0290)
-#define CHG_PINSEL_REFCLKO (CHGREGBase + 0x0294)
-#define CHG_PULL_G(n) (CHGREGBase + 0x0300 + 0x0004 * ((n) / 8))
-#define CHG_PULL(n) (CHGREGBase + 0x0380 + 0x0004 * (n))
-#define CHG_DRIVE(n) (CHGREGBase + 0x0400 + 0x0004 * (n))
-
-#define IICBase(x) (0x50030000 + 0x00010000 * (x))
-#define IIC 0x01
-#define IIC2 0x00
-#define IIC_IIC(n) (IICBase(n) + 0x0000)
-#define IIC_IICC(n) (IICBase(n) + 0x0008)
-#define IIC_SVA(n) (IICBase(n) + 0x000c)
-#define IIC_IICCL(n) (IICBase(n) + 0x0010)
-#define IIC_IICSE(n) (IICBase(n) + 0x001c)
-#define IIC_IICF(n) (IICBase(n) + 0x0028)
-
-#endif /*__MONITOR_ARM_EM1D_H__*/
diff --git a/tkernel_source/monitor/lib/string.c b/tkernel_source/monitor/lib/string.c
new file mode 100644
index 0000000..57841bd
--- /dev/null
+++ b/tkernel_source/monitor/lib/string.c
@@ -0,0 +1,262 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Added by T-Engine Forum at 2013/03/11.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * string.c
+ * Standard string / memory operations used for t-monitor
+ */
+
+#include <tmonitor.h>
+
+/* memory access size */
+#define MASZ (sizeof(unsigned long))
+#define MAMSK (MASZ - 1)
+
+/* memory access pointer */
+typedef union {
+ unsigned char *cp;
+ unsigned long *lp;
+ unsigned long lv;
+} MPTR;
+
+/*
+ * memset : fill memory area
+ */
+void* memset( void *s, int c, size_t n )
+{
+ MPTR m;
+ size_t cnt;
+ unsigned long val;
+
+ m.cp = (unsigned char *)s;
+ val = (unsigned char)c;
+
+ cnt = m.lv & MAMSK;
+ if ( cnt > 0 ) {
+ /* Not aligned in WASZ bytes */
+ if ( n < MASZ * 2) {
+ cnt = n;
+ } else {
+ cnt = MASZ - cnt;
+ }
+ /* Fill preceding bytes to align */
+ n -= cnt;
+ do {
+ *m.cp++ = (unsigned char)val;
+ } while ( --cnt > 0 );
+ }
+
+ /* Fill in WASZ bytes unit */
+ if ( n >= MASZ ) {
+ cnt = n / MASZ;
+ n &= MAMSK;
+ val |= val << 8;
+ val |= val << 16;
+ do {
+ *m.lp++ = val;
+ } while ( --cnt > 0 );
+ }
+
+ /* Fill trailing bytes */
+ while ( n-- > 0 ) {
+ *m.cp++ = (unsigned char)val;
+ }
+ return s;
+}
+
+/*
+ * memcmp : perform memory comparison
+ */
+int memcmp( const void *s1, const void *s2, size_t n )
+{
+ int result;
+ const unsigned char *p1 = s1;
+ const unsigned char *p2 = s2;
+
+ while ( n-- > 0 ) {
+ result = *p1++ - *p2++;
+ if ( result != 0 ) return result;
+ }
+ return 0;
+}
+
+/*
+ * memcpy : copy memory
+ */
+void* memcpy( void *dst, const void *src, size_t n )
+{
+ MPTR s, d;
+ size_t cnt;
+
+ d.cp = (unsigned char *)dst;
+ s.cp = (unsigned char *)src;
+
+ if ( ( (s.lv | d.lv) & MAMSK ) != 0 ) {
+ /* Not aligned in WASZ bytes */
+ if ( ( (s.lv ^ d.lv) & MAMSK ) != 0 || n < MASZ * 2) {
+ /* Full copy in a byte unit */
+ cnt = n;
+ } else {
+ /* Copy preceding bytes to align */
+ cnt = MASZ - (s.lv & MAMSK);
+ }
+ /* Copy in a byte unit */
+ n -= cnt;
+ do {
+ *d.cp++ = *s.cp++;
+ } while ( --cnt > 0 );
+ }
+
+ /* Copy in WASZ bytes unit */
+ if ( n >= MASZ ) {
+ cnt = n / MASZ;
+ n &= MAMSK;
+ do {
+ *d.lp++ = *s.lp++;
+ } while ( --cnt > 0 );
+ }
+
+ /* Copy trailing bytes */
+ while ( n-- > 0 ) {
+ *d.cp++ = *s.cp++;
+ }
+ return dst;
+}
+
+/*
+ * memmove : move memory
+ */
+void* memmove( void *dst, const void *src, size_t n )
+{
+ MPTR s, d;
+ size_t cnt;
+
+ d.cp = (unsigned char *)dst;
+ s.cp = (unsigned char *)src;
+
+ if ( d.cp < s.cp ) { /* Copy forward */
+ if ( ( (s.lv | d.lv) & MAMSK ) != 0 ) {
+ if ( ( (s.lv ^ d.lv) & MAMSK ) != 0 || n < MASZ * 2 ) {
+ cnt = n;
+ } else {
+ cnt = MASZ - (s.lv & MAMSK);
+ }
+ n -= cnt;
+ do {
+ *d.cp++ = *s.cp++;
+ } while ( --cnt > 0 );
+ }
+ if ( n >= MASZ ) {
+ cnt = n / MASZ;
+ n &= MAMSK;
+ do {
+ *d.lp++ = *s.lp++;
+ } while ( --cnt > 0 );
+ }
+ while ( n-- > 0 ) {
+ *d.cp++ = *s.cp++;
+ }
+ } else { /* Copy backward */
+ s.cp += n;
+ d.cp += n;
+ if ( ( (s.lv | d.lv) & MAMSK ) != 0 ) {
+ if ( ( (s.lv ^ d.lv) & MAMSK ) != 0 || n < MASZ * 2 ) {
+ cnt = n;
+ } else {
+ cnt = s.lv & MAMSK;
+ }
+ n -= cnt;
+ do {
+ *--d.cp = *--s.cp;
+ } while ( --cnt > 0 );
+ }
+ if ( n >= MASZ ) {
+ cnt = n / MASZ;
+ n &= MAMSK;
+ do {
+ *--d.lp = *--s.lp;
+ } while ( --cnt > 0 );
+ }
+ while ( n-- > 0 ) {
+ *--d.cp = *--s.cp;
+ }
+ }
+ return dst;
+}
+
+/*
+ * strlen : get text string length
+ */
+size_t strlen( const char *s )
+{
+ char *cp = (char *)s;
+
+ while ( *cp != '\0' ) cp++;
+ return (size_t)(cp - s);
+}
+
+/*
+ * strcmp : perform text string comparison
+ */
+int strcmp( const char *s1, const char *s2 )
+{
+ for ( ; *s1 == *s2; s1++, s2++ ) {
+ if ( *s1 == '\0' ) return 0;
+ }
+ return (unsigned char)*s1 - (unsigned char)*s2;
+}
+
+/*
+ * strncmp : perform text string comparison of specified length
+ */
+int strncmp( const char *s1, const char *s2, size_t n )
+{
+ int result;
+
+ while ( n-- > 0 ) {
+ result = (unsigned char)*s1 - (unsigned char)*s2++;
+ if ( result != 0 ) return result;
+ if ( *s1++ == '\0' ) break;
+ }
+ return 0;
+}
+
+/*
+ * strcpy : copy text string
+ */
+char* strcpy( char *dst, const char *src )
+{
+ char *dp = dst;
+
+ while ( (*dp++ = *src++) != '\0' );
+ return dst;
+}
+
+/*
+ * strncpy : copy text string of specified length
+ */
+char* strncpy( char *dst, const char *src, size_t n )
+{
+ char *dp = dst;
+
+ while ( n-- > 0 ) {
+ if ( (*dp++ = *src++) == '\0' ) {
+ while ( n-- > 0 ) *dp++ = '\0';
+ break;
+ }
+ }
+ return dst;
+}
+
diff --git a/tkernel_source/monitor/tmmain/build/tef_em1d/Makefile b/tkernel_source/monitor/tmmain/build/tef_em1d/Makefile
deleted file mode 100644
index 7cd7eac..0000000
--- a/tkernel_source/monitor/tmmain/build/tef_em1d/Makefile
+++ /dev/null
@@ -1,144 +0,0 @@
-#
-# ----------------------------------------------------------------------
-# T-Kernel 2.0 Software Package
-#
-# Copyright 2011 by Ken Sakamura.
-# This software is distributed under the latest version of T-License 2.x.
-# ----------------------------------------------------------------------
-#
-# Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
-# Modified by T-Engine Forum at 2011/09/08.
-# Modified by T-Engine Forum at 2012/11/07.
-# Modified by T-Engine Forum at 2013/03/01.
-# Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
-#
-# ----------------------------------------------------------------------
-#
-
-# T-Monitor : tmmain (em1d)
-
-MACHINE = em1d
-TETYPE = tef
-
-SRC_SYSDEP =
-
-# ----------------------------------------------------------------------------
-
-DEPS = Dependencies
-DEPENDENCIES_OUTPUT := $(DEPS)
-
-include $(BD)/etc/makerules
-
-# install directory
-TMONITOR_INSTALLDIR = $(BD)/monitor/bin/$(TETYPE)_$(MACHINE)
-
-# h/w depend module path
-HWDEPEND_PATH = $(BD)/monitor/hwdepend/$(TETYPE)_$(MACHINE)/build
-
-# command/svc module path
-CMDSVC_PATH = $(BD)/monitor/cmdsvc/build/$(TETYPE)_$(MACHINE)
-
-# each driver module path
-DRV_SIO_PATH = $(BD)/monitor/driver/sio/build/$(TETYPE)_$(MACHINE)
-DRV_FLASH_PATH = $(BD)/monitor/driver/flash/build/$(TETYPE)_$(MACHINE)
-DRV_MEMDISK_PATH = $(BD)/monitor/driver/memdisk/build/$(TETYPE)_$(MACHINE)
-
-# header paths
-HEADER = $(BD)/include $(BD)/monitor/include
-
-# ----------------------------------------------------------------------------
-
-# version
-VER := 2.01.00
-
-# T-Monitor boot message
-define VERSION
-char const Version[] = "$(VER)";
-char const * const Title[] = {
- "T-Monitor/$(TETYPE)_$(MACHINE) Version $(VER)",
- 0,
- "@(#)$(shell LC_TIME=C date)"
-};
-endef
-
-# ----------------------------------------------------------------------------
-
-TARGET = tmonitor
-
-S = ../../src
-
-VPATH = $(S)
-HEADER += $(S)
-
-SRC = $(SRC_SYSDEP)
-
-OBJ = $(addsuffix .o, $(basename $(SRC)))
-
-CFLAGS += $(CFLAGS_WARNING)
-
-# ----------------------------------------------------------------------------
-
-M_OBJ = $(TMONITOR_INSTALLDIR)/hwdepend.o \
- $(TMONITOR_INSTALLDIR)/cmdsvc.o \
- $(TMONITOR_INSTALLDIR)/wrkbuf.o \
- $(TMONITOR_INSTALLDIR)/sio.o \
- $(TMONITOR_INSTALLDIR)/flash.o \
- $(TMONITOR_INSTALLDIR)/memdisk.o
-
-LDLIBS = -lgcc
-
-LDFLAGS += -static -nostdlib -T $(LINKSCRIPT)
-
-ifneq ($(filter ram, $(options)), )
- # RAM version, for debug purpose
- LINKSCRIPT = monitor-ram.lnk
-else
- LINKSCRIPT = monitor.lnk
-endif
-
-# ----------------------------------------------------------------------------
-
-.PHONY: all clean install
-
-ALL = $(TARGET).mot $(TARGET).map
-
-all: hwdepend cmdsvc drivers $(ALL) install
-
-$(TARGET).mot: $(TARGET)
- $(OBJCOPY) -O srec --srec-forceS3 --srec-len 32 $< $@
-
-$(TARGET): $(M_OBJ) $(OBJ) version.o
- $(CC) $(TARGET_ARCH) $(LDFLAGS) $^ $(LDLIBS) $(OUTPUT_OPTION)
-
-version.c: Makefile $(OBJ) $(M_OBJ)
- echo "$$VERSION" > version.c
-
-hwdepend:
- ( cd $(HWDEPEND_PATH) ; $(MAKE) ; $(MAKE) install ; )
-
-cmdsvc:
- ( cd $(CMDSVC_PATH) ; $(MAKE) ; $(MAKE) install ; )
-
-drivers:
- ( cd $(DRV_SIO_PATH) ; $(MAKE) ; $(MAKE) install ; )
- ( cd $(DRV_FLASH_PATH) ; $(MAKE) ; $(MAKE) install ; )
- ( cd $(DRV_MEMDISK_PATH) ; $(MAKE) ; $(MAKE) install ; )
-
-clean:
- ( cd $(HWDEPEND_PATH) ; $(MAKE) clean )
- ( cd $(CMDSVC_PATH) ; $(MAKE) clean )
- ( cd $(DRV_SIO_PATH) ; $(MAKE) clean )
- ( cd $(DRV_FLASH_PATH) ; $(MAKE) clean )
- ( cd $(DRV_MEMDISK_PATH) ; $(MAKE) clean )
- $(RM) version.[co] $(OBJ) $(M_OBJ) $(TARGET) $(ALL) $(DEPS)
-
-install: $(addprefix $(EXE_INSTALLDIR)/, $(ALL))
-
-ifdef DEPENDENCIES_OUTPUT
- $(DEPS): ; touch $(DEPS)
-else
- $(DEPS): $(SRC) ; $(MAKEDEPS) $@ $?
-endif
--include $(DEPS)
-
-$(SRC.C):
diff --git a/tkernel_source/monitor/tmmain/build/tef_em1d/monitor.lnk b/tkernel_source/monitor/tmmain/build/tef_em1d/monitor.lnk
deleted file mode 100644
index 590651c..0000000
--- a/tkernel_source/monitor/tmmain/build/tef_em1d/monitor.lnk
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * monitor.lnk
- *
- * link specification for monitor
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-
-SECTIONS {
- __loadaddr = 0x70000000;
- _start = 0x70000000;
- .eitbra _start : AT(__loadaddr) {
- __eitbra_start = .;
- *(EITBRA)
- . = ALIGN(0x10);
- }
- .startup : {
- *(.startup)
- . = ALIGN(0x10);
- }
- __text_org = __loadaddr + SIZEOF(.startup) + SIZEOF(.eitbra);
- .text __text_org : {
- _stext = .;
- KEEP (*(.init))
- *(.text)
- *(.text.*)
- *(.stub)
- *(.glue_7t)
- *(.glue_7)
- KEEP (*(.fini))
- PROVIDE (__etext = .);
- PROVIDE (_etext = .);
- PROVIDE (etext = .);
- *(.rodata)
- *(.rodata.*)
- *(.rodata1)
- . = ALIGN(0x10);
- } =0
- __data_org = . ;
- .data 0x30004440 : AT(LOADADDR(.text) + SIZEOF(.text)) {
- __data_start = . ;
- *(flashwr.rodata)
- *(.data)
- *(.data.*)
- SORT(CONSTRUCTORS)
- *(.data1)
- KEEP (*(.eh_frame))
- *(.gcc_except_table)
- KEEP (*crtbegin.o(.ctors))
- KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- KEEP (*crtbegin.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- *(.got.plt)
- *(.got)
- *(.sdata)
- *(.sdata.*)
- . = ALIGN(0x10);
- _edata = .;
- PROVIDE (edata = .);
- }
- .bss (NOLOAD) : AT(LOADADDR(.data) + SIZEOF(.data)) {
- __bss_start = .;
- PROVIDE (__sbss_start = .);
- PROVIDE (___sbss_start = .);
- *(.sbss)
- *(.sbss.*)
- *(.scommon)
- PROVIDE (__sbss_end = .);
- PROVIDE (___sbss_end = .);
- *(.bss)
- *(.bss.*)
- *(EXCLUDE_FILE(*/wrkbuf.o) COMMON)
- . = ALIGN(0x10);
- _end = .;
- PROVIDE (end = .);
- }
- __flashwr_org = __data_org + SIZEOF(.data);
- OVERLAY : AT(LOADADDR(.bss)) {
- .flashwr {
- __flashwr_start = .;
- *(flashwr.text)
- __flashwr_end = .;
- }
- .wrkbuf {
- */wrkbuf.o(COMMON)
- }
- }
- .stack ALIGN(0x10) (NOLOAD) : {
- __stack_top = .;
- __stack_bottom = 0x30006000 - ABSOLUTE(.);
- }
-}
diff --git a/tkernel_source/monitor/tmmain/version.c b/tkernel_source/monitor/tmmain/version.c
new file mode 100644
index 0000000..8ca9705
--- /dev/null
+++ b/tkernel_source/monitor/tmmain/version.c
@@ -0,0 +1,6 @@
+char const Version[] = "2.01.00";
+char const * const Title[] = {
+ "T-Monitor/tef_em1d Version 2.01.00",
+ 0,
+ "@(#)Tue Oct 20 19:05:59 CST 2015"
+};
--
1.9.1
References
