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Track connectivity enhancement


Can you test this change with your borad.
The track connectivity computation takes in account tack or via width, and i believe its solvs your problem.

Geoff :
Please, remove all your last changes in via enhancement.
You are mistaken for via attributes.
*** Attribute is only what layer pair is allowed, not what layer pair is really used. ***

Via attributes can be THROUGH VIA, BURIED VIA or BLIND VIA.
Its is only a via attribute, not the real via type.

I mean :
if a via has THROUGH VIA attribute, it always connects all layers whenever track are connected. but if a via has BURIED VIA attribute, its can connects all layers, if it connects a tarck on copper layer ans a track on component layer.
The difference it:
suppose you have a 4 layers board.
you create a via which connects 4 tracks on 4 layers (copper, inner1, inner2, cmp). this via connects all layers.
If the via type is BURIED VIA:
its real type is a through hole via. But:
if you remove the track on copper layer, the via layer pair will be changed to connetc layers from inner1 to cmp.
f the via type is THROUGH VIA:
if you remove the track on copper layer, the via layer pair will be changed to connect layers from inner1 to cmp.
its real type is a blind via. but its attribut MUST remaind BURIED VIA.

I believe the BLIND VIA attribute is not usefull, and perhapes it will be removed in the future (THROUGH VIA and BURIED VIA are enought)

Of course, most of code must be written.
But some pieces of code exist ans this code must not be broken.
Because smd components are smaller and smaller, BURIED VIA must be used in a near future,
and we must work on this code.


Jean-Pierre CHARRAS

Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
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