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Re: zone fill with micro-vias


Tim Hanson a écrit :


I've been fiddling around with the new zones & filling, and I'm super

However, the zone fill algorithm does not know that it does not need
to avoid micro or laser-drilled vias from the component to layer 2
when filling a ground plane on layer 1.
Presumably the layer stack
is Component:Layer 2:Layer 1:Copper in this 4-layer board; i saw no
options to change the layer connections for these micro-vias(? ). Can
fix this if somebody points me in the right direction...


Also, shouldn't a zone fill eliminate ratsnest lines appropriately?
How to fix this?


This is the second step in zone redesign.
A reliable algorithm to calculate connectivity between pads considering zone outlines (i.e. polygons) is not easy to find. 2 pads can be in the same zone polygon and not connected, if there are tracks (or vias) in this polygon. These tracks and vias (+ isolation gap) can create obstacles which break connection between pads (or vias).
This is a very common case.
Currently, my main problem is :
- how to determine if pads (or pads + tracks + vias) are connecteds by zones when tracks and/or vias create holes in a given zone polygon.
- the algorithm must be reliable and reasonably fast.
(Pray to have a connection in all cases is *not* a good algorithm)
- less critical: how to determine if the remaining copper in a zone has no very narrow section and if the connection has everywhere a sufficient size

FreePCB does not detect insulated pads in a zone, and we can have inside a zone a pad not connected (if tracks encircle this pad)
I (or an other guy) must study gpcb code.

Unfortunately, currently i have a lot of work, and i must also finish some sections of code relative to the complex hierarchy implantation.
This is a complex code.
(Critical bugs i found were solved, but the code needs some work to be finished.),.
So i can't work very well on zones until end of april.
But it is always the **main** focus.

I tested the new code about delete track segment on a very large board (8 layers, 4000 pads 1350 vias...)
It is reasonably fast on my PC ( a low cost computer which is 4 years old).
An enhancement could be to redraw only the region modified in order to reduce the flicker (all kicad draw functions already use a clip box).

Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402 St Martin d'Heres Cedex

Recherche :
Grenoble Image Parole Signal Automatique (GIPSA - INPG)
46, Avenue Félix Viallet
38031 Grenoble Cedex

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