kicad-developers team mailing list archive

["Frank Bennett" <bennett78@...>]

--- In kicad-devel@xxxxxxxxxxxxxxx, "Tim Hanson" <tim@...> wrote:
>
> Hi Frank,
> Yes, that makes sense -- I'll make sure all the schematic files in the
> demos still work. They should, as most of them are eeschema version 1
> not 2.
Drop me some Email or post when you get around to this...I have
a netname change associated with power symbols I want to try before 
I check it in.

> It would be nice if pcbnew could generate a netlist; I'm not sure how
> big of a job this would be, though it seems pretty substantial!

Yes, pcbnew is missing a Net structure. The PCB123 XML I'm trying to 
import has the following structure:
<Net Nm='DEF0_1' Pln='0' Wid='0.008in' Spc='0.007in' Via='0.036in'
Drl='0.02in' Pri='0' Reconn='Min' Clr='-2147483648'
<Node Cmp='U1' Pin='16'>
<Node Cmp='R19' Pin='1'>
<Track Crns='15'
<Crn Idx='0' X='1.9567in' Y='-2.3047in' Wid='0.008in' Lyr='Top'
Fan='false'>
<Crn Idx='1' X='1.7677in' Y='-2.1158in' Wid='0.008in' Lyr='Top'
Fan='false'>
<Crn Idx='2' X='1.7677in' Y='-1.8425in' Wid='0.008in' Lyr='Top'
Fan='false'>
<Crn Idx='3' X='1.6575in' Y='-1.7205in' Wid='0.008in' Lyr='Top'
Fan='false'>
<Crn Idx='4' X='1.0118in' Y='-1.7205in' Wid='0.008in' Lyr='Top'
Fan='false'>
<Crn Idx='5' X='0.8661in' Y='-1.8386in' Wid='0.008in' Lyr='Top'
Fan='false'>
<Crn Idx='6' X='0.8661in' Y='-1.9449in' Wid='0.008in' Lyr='Bot'
Fan='true'>
<Crn Idx='12' X='0.6762in' Y='-2.5787in' Wid='0.008in'
Lyr='Top' Fan='false'>
<Crn Idx='13' X='0.6604in' Y='-2.563in' Wid='0.008in' Lyr='Top'
Fan='false'>
<Crn Idx='14' X='0.6604in' Y='-2.5118in' Wid='0.008in'
Lyr='Top' Fan='false'>>>

where a via is implied when a layer change occurs.

thanks,
Frank

> thanks,
> Tim
> 
> On Mon, Mar 17, 2008 at 1:46 PM, Frank Bennett
> <bennett78@...> wrote:
> >
> >
> >
> >
> >
> >
> > --- In kicad-devel@xxxxxxxxxxxxxxx, "Tim Hanson" <tim@> wrote:
> > >
> > > How should this be done?
> > Tim:
> >
> > I see this new scheme was checked in to svn:
> > /s/opt/svn/kicad/trunk/kicad# svn log eeschema/netlist.cpp |less
> > r758 | lifekidyeaa | 2008-02-14 22:32:33 -0700 (Thu, 14 Feb 2008) | 4
> > lines
> >
> > I would suggest in the demo directory that the netlists be
> > re-generated, reviewed (svn diff) and checked in...I assume you
> > did try to import some into cvpcb & pcbnew.
> >
> > Some day it would be nice to have a regression test suite to
> > make sure developers have not broken the PCB design flow :^)
> >
> > Thanks for the netlist improvements. This helps alot when designing
> > a PCB...which reminds me side note:
> >
> > Enhancement request: pcbnew should be able to generate a netlist
> > and compare it to the original eeschema netlist and report
differences
> > (other that an added footprint)? The eeschema netlist is redundant in
> > that the nets are listed by component and netname. The netname
> > list is broken (missing nets) but is for reference only.
> >
> > Frank Bennett
> > >
> > > I'm happy to code it up, just want some input.
> > >
> > > Also, is anyone else annoyed when, also in eeschema, you delete
a long
> > > straight line, and instead of the deletion terminating at the next
> > node or
> > > intersection, it deletes *everything*. This frequently forces
me to redo
> > > long lines.. worth a fix?
> > >
> > > thanks yall,
> > > Tim
> >
> >
>