kicad-developers team mailing list archive

["Frank Bennett" <bennett78@...>]

--- In kicad-devel@xxxxxxxxxxxxxxx, jean-pierre charras
<jean-pierre.charras@...> wrote:
>
> Frank Bennett a �crit :
> >   
> I saw your board.
> There is a lot of problems:
> 
> - Some examples: vias are flagged "through" (i.e. from layer 0 (copper) 
> to layer 15 (component) but the param m_Layer said from inner 1 to
inner 3.
> Such vias are blind or buried vias.
> 
> - at location 0.2400, 0.5300 there are 2 superimposed vias (a XOR mode 
> redraw could be have problems, and a board manufacturer also...))
> 
> And I found a lot of strange things (components layer is component and 
> layer pad is copper. This is possible for some components (like a PC
bus 
> , usually not for smd components)
> And their outlines are put on an adhesive layer ( this is possible, but 
> usually they are on silkscreen layers, an adhesive layer is intended to 
> draw components like sink heater)
> 
> This may be an explanation for some problems.

Thanks jean-pierre, 

I have checked in a better svn version for project XML4PCB
with a better layer assignments, $GENERAL, $SETUP and pin nets 
but I don't get any ratsnet or any network in the dsn export.  
Could you take a quick look to see what I am missing in the brd
file...examples/txpr.brd is a partially routed, simple example.

I also would propose we add a Net Name tag to the $TRACK
specification...should be backward compatible, might help simplify 
the ratsnet code and enable an export netlist from pcbnew.

thanks again,
Frank

> -- 
> 
> Jean-Pierre CHARRAS
> 
> Ma�tre de conf�rences
> Directeur d'�tudes 2ieme ann�e.
> G�nie Electrique et Informatique Industrielle 2
> Institut Universitaire de Technologie 1 de Grenoble
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> 
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