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Re: Re: EESchema XOR-Artifacts
Frank Bennett a écrit :
Actually you didn't look close enough. There is a component
trace from the U1-2 up to the Via. But the reason I respond
is that pcbnew does not draw the current layer last. This
is a handy feature while adding tracks, I was used to in PCB12
...someday, maybe somebody or I will add this feature to pcbnew!
I did an export specctra of my lcd.brd design and see I need to
add a feature that outputs the pin nets from XML4PCB inorder to
try the free-router.
I saw your board.
There is a lot of problems:
- Some examples: vias are flagged "through" (i.e. from layer 0 (copper)
to layer 15 (component) but the param m_Layer said from inner 1 to inner 3.
Such vias are blind or buried vias.
- at location 0.2400, 0.5300 there are 2 superimposed vias (a XOR mode
redraw could be have problems, and a board manufacturer also...))
And I found a lot of strange things (components layer is component and
layer pad is copper. This is possible for some components (like a PC bus
, usually not for smd components)
And their outlines are put on an adhesive layer ( this is possible, but
usually they are on silkscreen layers, an adhesive layer is intended to
draw components like sink heater)
This may be an explanation for some problems.
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