kicad-developers team mailing list archive

[Lorenzo Marcantonio <l.marcantonio@xxxxxxxxxxxx>]

On Mon, 14 Jun 2010, Werner Almesberger wrote:

> Hmm, but if you use it mainly for rework, adjacent components could
> share the courtyard, no ? After all, you'll inspect or (de)solder
> them one by one, not simultaneously.

It would be difficult to say 'how much' they can overlap... I think they
calculated them 'in-average', keeping in account this... for example for
the typical 0603-or-bigger chip package the nominal excess is 0,25mm
which is by itself insufficient for tweezers (the WTA-1 need 0,5mm to
fit in). But keeping *two* resistors side by side (0,25+0,05
intercourtyard clearance+0,25) allow access (in real world what happen
usually is: you want to desolder one resistor and the near four ones get
loose too :().

> Also, what do you do with components with a very non-rectangular
> shape, e.g., SOT-23 and friends ?

As a good layout rule of thumb you don't "nest" components, most of the
time, it's considered bad form:D also the standard is already
sufficiently complex, only using a bounding box!

> Sigh. I wish the standard was a bit more free ...

I agree... for professional use the price is trivial (about 60 EUR
IIRC), but for hobby use it a barrier to entry... (if you look around
you can find 'leaked' copies, anyway :P)

Also of 96 pages only 20 contains the needed data for calculations, the
other mostly contains explanation of how components are made (like:
a SOIC has a pitch of 1,27 ...) and manufacturing details (compliance
testing and tray/tape/reel formats).

> The problem with handwaving is that it's contagious. Make all your
> keep out zones pessimistic (i.e., large) and people will get into
> the habit of violating them because they know they can get away
> with it. Make them optimistic, and each will introduce their own
> "safety factor".

The main issue is that there's a lot of process dependant parameters
here... I can do a 6mil tech board without problem but if possible
I would make it in 8mil tech because yield is better (so it's cheaper).
Also some fabs have milling tolerances of 0,2mm instead of 0,1mm, so
what do you use for clearance to the edge of the board? (it only get
sicker from there, like 0,2mm on outer edges but 0,1mm on pockets, or
different tolerances depending on drill size!). You also have to keep
track of pick-and-place tolerances, how much boards will be 'shaken'
from site bombing and reflow and how much rework you can tolerate. The
'minimum/median/maximum' levels in the standard are a way to unificate
all these issues (and with the 'least' protrusion, i.e. high density,
you *must* do test runs to determine if process yield is acceptable).

> Same thing with disallowing overlapping keep out areas that can
> overlap in practice. (That's why I brought up that point.)

In my experience usually you can use that space to put some via and/or
difficult-to-route trace:D

> Hmm, wouldn't it be nice for making hobbyist-friendly layouts if
> we had the placement tolerance as a parameter, like we have the
> clearance right now ? Of course, changing it would also have to
> grow pads and such ...

Placement tolerances *are* a parameter in the IPC formulas (there is
a whole theory of minimum material conditions and so on, like doing the
RMS of the tolerances...). The defaults in the LP Calculator (it's free,
but you need to register) are 0,05mm (i.e. one point on the standard
grid) but you can change all of them in the preferences...

Also, a good operator with a suitable magnification tool can place
components even *better* than the site bomber (the trick is that during
reflow surface tension in solder realign the component - usually).

The ideal thing would be someone porting the IPC formulas for generating
.emp files (side note: the LP Calculator is free but they make you pay
big bucks for the cad export options!)

--
Lorenzo Marcantonio
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