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Re: Proposal for the courtyard/assembly layer issue


On Fri, 10 Sep 2010, Brian F. G. Bidulock wrote:

I too have been attempting proper plot-and-go legend handling now that
it is split from assembly drawings and placement courtyards.  Yes I know
that board fabricators keep saying that silk is unnecessary, but I don't
want to debug a prototype without one: too much chance for error when
moving my eyes from the assembly drawing to the unlabelled board.

In my experience silk is mostly for assembly... in a populated board
which little silk that remain is usually covered by component so you
learn really quick to 'eye-count' chip packages. Also, as a rule, I put
a metric ton of testpoints around (but I have not done yet
a designed-for-testing board where *every* net is accessible by probe or

The silkscreen process has the following parameters:  Registration,
minimum line width, minimum space between lines (to avoid bleeding),
minimum character height (subjective).

Exactly... that's usually reduced to the 'silk pitch' i.e. the minimum
feature size. Registration is usually about half of that value in my
experience (I work with only 3 fabs so your mileage may vary)

Legend must be kept off exposed pads, contacts, traces (bad), also
laminate (does not adhere well to dielectric), and the edges of holes
(holes only partially tented with primary mask).  Silkscreen has a
vertical dimension: it must be kept out from under components mounted
flush to the board to avoid drawbridging.  Fabricators want to clip the
legend to the primary mask so none of these overlaps happen (and have
the assembler point the finger at them).  Handling these overlaps
requires knowledge about primary mask registration and clearance.

Sorry, what's the problem with silk over (masked) traces? I've always
done it without problem (otherwise there would be no place for it:D).
This subtraction process is correctly done with the solder mask, but
*after* it has been enlarged for mask registration, too! (and gang
masking if it's the case).

We have a funny situation: solder masking has to be done at pad size
(and enlarged by fabricator), silk screening should be done so that
wouldn't be clipped *after* enlarging... they usually say 'keep all silk
at 0,25mm from pads and holes' (the 0,25 is the composite
registration of silk and mask, obviously). And anyway they prefer to
have it already clipped, too! These lazy fabs:P

Some fabricators take the approach of expanding the soldermask plot by
the legend registration and using it as a clear overlay on the legend.
This is not totally satisfactory as lines can be clipped in the middle,
so soldermask must be expanded by the legend registration and the
minimum line thickness.  That's the easy way, and we could do that when
generating Gerbers for silkscreen.

IMHO that's a crappy way to do it... but that's what I actually do:D
enlarge pads by 0,25 and subtract it from the silk (actually it's
gerbertool that does it; and most modern photoplotter could do it when
fed a negative sublayer). It's the only way to be sure that silk is as
you specify.

However, most of the gauge of the quality of the result is subjective:
that is, whether the resulting white goop on board is legible.  Some

My rule of thumb is as follows: lines can always be clipped. Polarity
marks and designators, never. And of course forget designators for
anything smaller than a 1206.

I propose a very-much simpler approach: when focusing on silk layer,
instead of electrical pad clearance show the 0,25 silk clearance. That's
where silk would be cut anyway by the fab. Then I can move references
and labels to go were they wouldn't be cut. A luxury function would be
a warning from the DRC, but that's not essential.

To handing the third dimension, it might be an idea to clip the legend
also as it passes under flush-mounted components.

That's not necessary; if it's away from a pad it can't do damage (unless
silk is actually thicker than solder paste, then it could result in
unsoldered leads).

For the actual clipping there are two approaches: simply clear overlay
an expanded soldermask layer, or remove actual segments or portions of
segments.  The first one is easier.  I have code for that.

How do you 'clear overlay' in gerber without resorting to knockouts or
negative planes? these are advanced features that no viewer or importer
would accept.

Clipping segments is actually easy: first of all you always have line
segments (because arc could be approximated in the case), then you just
have to intersect them with the pad enlarged by the silk registration
and half of the line width. In the worst case you have only to delete
a segment from the middle of the line (that's an easy proof since pads
are always convex). And anyway it's only needed on plot, it's usually
done as a post processing on the gerbers.

More display options.  I know that there is a patch for applying minimum
width and size character attributes to a board, but I want to add a
General Option to enforce character minimums or not.  When checked, text
would be displayed with the character width and height minimums
enforced.  That is, when text is narrower and taller than the minimums,
the it would simply be displayed with the minimum.  Unchecking the box
would display the actual values from the module.  (The same would be
true for PCB text on silk.)

I don't think it would be much useful, since you just have to click and
read in the status bar to see the component. Also it can mislead if
accidentally left turned on.

Two checkbox options will be added to the plot (post-processing) menus:

Mask silk: when checked, the simple approach of using an expanded mask
   layer as a clear overlay of the silk layer would be plotted.  This
   can be used independent of the "Clip silk" option below.

As I said above please explain how you would do this in rs274...

I have already generated code for the masking.  I have not generated
code for segment or character clipping.  There is a need to slice long
line segments that intersect mask openings into smaller segments so that
the unclipped portion can remain.

I've outlined the steps above, maybe kbool would help. It's an iterative
process, from each line in the plot set agaist a pad you can have 0,
1 or 2 resulting lines. Repeat for each pad and until you don't split
anymore. I could call it the 'bubble sort' of line clipping :D

Sure, it could be optimized, but it's a plot function, not to be done in

I think that the masking (which I have already done) is easier and
probably sufficient.  Also, it is what the fabricator does anyway.

Our fabricators actually clip the lines, they even send back the 'fixed'
gerber if you ask them (depending on the property of the resulting

Lorenzo Marcantonio
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