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Re: Sweet parser

 

Le 24/03/2011 14:51, Dick Hollenbeck a écrit :

Pin name is, in fact, actually a pin description, and currently is just a comment.

About pin "numbers" (currently a 4 characters identifier) I believe an enhancement in Eeschema could be the support of pins having
multiple pin numbers.
I see 2 cases:
-Power pins in large ICs:
   they have 100 or more GND, VCC .. pins.
   In schematic an enhancement could be: put only one pin having one pin name (or description) and a lot of pin numbers.
-"Bus pins"
   The is in fact a similar case: one pin having many pin numbers.
   Useful for components like memories and microprocessors to handle data bus and address bus with only 2 pins.
the difference between these pins is mainly for netlist generation.

In library files format and load/save functions, just allow the ability to store more than one pin number per pin.
The cost is low.

What we have now is:

(pinTYPE SHAPE (at X Y [ANGLE])

(length LENGTH)

(name“NAME” (font[FONT] (size HEIGHT WIDTH) [italic] [bold]) (visible YES))

(number“NUMBER” (font[FONT] (size HEIGHT WIDTH) [italic] [bold])

(visible YES))

(visible YES)

)



So a 3rd consideration is to do what Jean-Pierre suggested, handling
multiple (number....) elements.

Feedback on the 3 ideas is needed at this point. Without feedback I will not
change anything, since multiple pin 'number's can be added later relatively
easily.

Dick


I am thinking there are 3 levels of increasing complexity
(assuming level 0 for usual pins currently in use in Eeschema):

Level 1:
A pin connected to one net, but having more than one "number".
Such a pin is connected to a wire or an other pin.
Easy to add in Eeschema with few new code.
This is my first case and is suitable for power pins.
Having more than one line in pin description like
> (number“NUMBER” (font[FONT] (size HEIGHT WIDTH) [italic] [bold])
is OK.
the "pin name" is just a comment, and this pin just handle a lot of pads in the corresponding footprint.

Level 2:
"Bus pins:"
What I have in mind is a pin that is connected to a bus in eeschema, like a "pin sheet" is connected to a bus.
labels, hierarchical labels and "pin sheets" use a notation like mybus[0..n],
and labels and pins having all the same bus member number are connected together?
These pins can be only connected to a bus, and are similar to pin sheets.
in this case the "pin name" is not just a comment, but defines the min and max bus member value.
This means a pin named data[0..7] can be connected to a bus named mybus[0..7] (or mybus[0..15], but only mybus[0..7] will be connected)
A more flexible way to connect a "bus pin" is to allow a pin named data[0..7] to be connect to a bus named mybus[8..15],
(case frequently found), but is more complex to code.

Level 3:
your "pin_group"
I like it.
Powerful, but (due to the complexity) needs some brain storming.
Needs also to allow complex bus labels, and pin sheets.
For instance a bus label like
data[0..7],R/W,Adr[1..32]
(with the comma used here as "signal' separator)

Levels 1 and 2 seems for me not so difficult to add in eeschema.

I do not see and problem to change:
number -> name
name   -> net or signal
(signal seems better for me, "net" having other meaning in schematic)


--
Jean-Pierre CHARRAS




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