kicad-developers team mailing list archive

[Dick Hollenbeck <dick@xxxxxxxxxxx>]

> You had said that we can duplicate the notion of instantiation of sheets by
> using instantiation of parts as a reference.  I disagree.  Parts are wired
> by netlist.  The nestlist is separate from the parts.  I think we need to do
> better than that WRT sheets.   More like verilog, or an annotated binding on
> the sheet's I/O parameters.  I did something like this in a past life, I can
> dig it out if nothing comes to you.  This concept is reusable later because
> if taken far enough you can then "arbitrarily fragment" your schematic into
> reusable blocks, blocks which might not necessarily be "sheets".  Aw sheet,
> I just made a lot of work for somebody.
>
> Here's some verilog I just wrote today:
>
> off_delay #(5) od1(
>     .clk_i          ( clock ),
>     .rst_i          ( !enable ),
>     .bit_pulse_i    ( bit_pulse ),
>     .enable_i       ( state==STATE1 ),
>     .off_delay_o    ( enable1 )
> );
>
>
> The clk_i is an input parameter defined within module off_delay.  od1 is the
> instance name, and here we are binding od1's clk_i to our outer clock.  The
> conversation subject I think is best called "sheet bindings".


I may be wrong about the sheet instantiation being different than the part
instantiation, since I did not see what you were thinking on parts.


The above verilog fragment was the verilog "module instantiation", not the
module definition.  Again, we have this notion of

a) declaration/definition and then

b) instantiation of whatever was defined along with parameter or I/O bindings.


Here is an s-expression example for instantiation of a sheet:


# sheet instantiation proposal:

(use_sheet_OR_sheet_OR_better SHEETNAME
   (bind_OR_bindings
     (. SHEETPIN1 NETNAME1)
     (. SHEETPIN2 NETNAME2)
    )
)


or instead of dot . use equals = instead?


    (= SHEETPIN1 NETNAME1)


I think . or = will parse OK.

That sort of looks like verilog module instantiation, and better explains
what I was trying to say.  The wrapping bind_OR_bindings is not mandatory,
has minor value in tidiness.   Another idea, less obvious:

(bind
    SHEETPIN1 NETNAME1
    SHEETPIN2 NETNAME2
    :
)

Or

(= SHEETPIN1 NETNAME1)
(= SHEETPIN2 NETNAME2)


Probably possible also:

(bind
    (SHEETPIN1 NETNAME1)
    (SHEETPIN1 NETNAME2)
)


Probably also need sheet number or page number or something additional.

Verilog, in the module definition, conveys the type of each I/O parameter. 
In our sheet definition, maybe we can borrow the electrical types you
created for pins?

Dick