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Re: SWEET: multisheet schematic concerns


On 02/22/2013 05:56 AM, Solonen Vesa wrote:
> It may make sense to take a peek how gEDA doest it. I'm not saying they are doing it perfectly, but their main idea is that everything is

>  a reusable file 


> and the design is scripted together. 

(unnecessary, verilog and java don't require this.)

Icarus verilog is fun to play with, and is open C++ code.  Playing
with Java from the command prompt is easy to do.  Both these
environments simply use search paths to find dependencies.

No scripting is necessary in either environment to assemble the
internal RAM tree.

> Like a C++ project with headers and make scripts...

Sounds like way more setup time than what I envisioned to accomplish
the same end.

But certainly your suggestion to *have a look* could be helpful for
someone who wanted to spend the kind of time it would take to do this.

I have most of the pieces lying around on my servers, but it is simply
too big of a task IMO to tackle without funding, serious funding.

This is one of those rare cases where I don't think evolutionary
change will get it done, not if you bring in all the eeschema
blueprints lying all over the place.

It is a re-write, not a series of increment changes, IMO.

I am not optimistic about fueling the qualified man-hours needed to
make this new version of eeschema happen.  The cost of all the work
probably exceeds a couple hundred grand, so color me an observer at
this point.

Even the talk costs money.


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