kicad-developers team mailing list archive

[Dick Hollenbeck <dick@xxxxxxxxxxx>]

>>
>> Thomas,
>>
>> Sorry to say that I lost your patch during a computer upgrade.
>>
>> Can you regenerate something or resend it please.
>>
>> Thanks,
>>
>> Dick


> Dick,
>
> please find the modifications against pcbnew 4061 in the attached patch file.
>
> Thomas
>


Thanks Thomas.  I applied this patch to version 4061 and ran it against the attached
board.  The board could not be "specctra exported".

This is the most basic board I could think of to test against.  I also tried a board with
two inner circles on  Edge.Cuts.

Also, the patch is littered with unrelated _() to wxT() replacements, which could not be
accepted.  So even if it did work at all, this is a difficult starting point for me.

So I am not convinced there is anything here to work with at this point.  Is there
something wrong with my board file?  Or can you send me a board which will export with
this patch?

Thanks,

Dick


(kicad_pcb (version 3) (host pcbnew "(2013-04-28 BZR 4117)-testing")

  (general
    (links 0)
    (no_connects 0)
    (area 159.944999 119.304999 237.565001 172.795001)
    (thickness 1.6)
    (drawings 9)
    (tracks 0)
    (zones 0)
    (modules 0)
    (nets 1)
  )

  (page A3)
  (layers
    (15 F.Cu signal)
    (0 B.Cu signal)
    (16 B.Adhes user)
    (17 F.Adhes user)
    (18 B.Paste user)
    (19 F.Paste user)
    (20 B.SilkS user)
    (21 F.SilkS user)
    (22 B.Mask user)
    (23 F.Mask user)
    (24 Dwgs.User user)
    (25 Cmts.User user)
    (26 Eco1.User user)
    (27 Eco2.User user)
    (28 Edge.Cuts user)
  )

  (setup
    (last_trace_width 0.254)
    (trace_clearance 0.254)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.254)
    (segment_width 0.2)
    (edge_width 0.15)
    (via_size 0.889)
    (via_drill 0.635)
    (via_min_size 0.889)
    (via_min_drill 0.508)
    (uvia_size 0.508)
    (uvia_drill 0.127)
    (uvias_allowed no)
    (uvia_min_size 0.508)
    (uvia_min_drill 0.127)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1.5 1.5)
    (mod_text_width 0.15)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.2)
    (aux_axis_origin 0 0)
    (visible_elements FFFFFF7F)
    (pcbplotparams
      (layerselection 3178497)
      (usegerberextensions true)
      (excludeedgelayer true)
      (linewidth 100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (hpglpenoverlay 2)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotothertext true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
  )

  (net 0 "")

  (net_class Default "This is the default net class."
    (clearance 0.254)
    (trace_width 0.254)
    (via_dia 0.889)
    (via_drill 0.635)
    (uvia_dia 0.508)
    (uvia_drill 0.127)
    (add_net "")
  )

  (gr_line (start 232.41 125.73) (end 220.98 125.73) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 232.41 137.16) (end 232.41 125.73) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 220.98 137.16) (end 232.41 137.16) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 220.98 125.73) (end 220.98 137.16) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 160.02 172.72) (end 160.02 119.38) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 160.02 172.72) (end 237.49 172.72) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 237.49 172.72) (end 160.02 172.72) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 237.49 119.38) (end 237.49 172.72) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 160.02 119.38) (end 237.49 119.38) (angle 90) (layer Edge.Cuts) (width 0.15))

)