kicad-developers team mailing list archive

[Tomasz Wlostowski <tomasz.wlostowski@xxxxxxx>]

On 28.03.2015 07:55, jp charras wrote:
> Le 27/03/2015 22:39, John Beard a écrit :
> 
> John,
> Currently, vias not connected to a pads (by tracks) are considered as
> not connected (i.e. have the net 0) as soon as the board connections are
> recalculated
> 
> This is true also for tracks connected to nothing, and I am thinking
> this is the right way to handle not connected track segments (vias are
> also track segments) when the board connections are recalculated.

Hi Jean-Pierre,

The proprietary software that I used (Eagle, Altium, PADS) does not
change the nets of any item on the board without the user explicitly
allowing such a change. This - in my humble opinion - gives more control
over the design and reduces the chances of accidentally breaking it.

I find the current connectivity calculation algorithm a bit too invasive
- but this I could live with. The worse part is that net code
recalculation is silently called in many places without the agreement of
the user and cannot be undone. For example, when I design PCBs, I often
leave some 'snippets' (e.g. some trace/via patterns) aside, for later
use. I would prefer Kicad to not change or reset their nets unless I
tell it to...

The cases where the net of an item may be changed (except for editing it
in the item's properties) IMHO are:
1) Netlist update (propagated from the pads of the changed components,
just like the current algorithm does).
2) Removing net completely on the schematic causes removal of the
corresponding nets on the PCB.
3) Placing a pad (or module) over a set of board items (tracks, vias)
causes the latter to inherit the pads' nets only if not connected to
another pad.
4) Placing a set of board items (excluding components) over pads with
assigned nets causes the former to inherit the pads' nets. This one is
particularly useful for copying & pasting via fanouts under big BGAs
(route one row/side of a BGA, paste over other BGA pads)
5) Zone nets may be changed only if the net no longer exists in the
schematic.

> 
> Moreover, these tracks are removed by the board cleaning functions.
> 

> Via stitching is not a thing which is easy to add.
> Be sure this feature requires a lot of work (DRC, filling zone
> algorithms ... )

I agree we would need to modify the DRC (but AFAIK it only means
producing errors on vias that are not connected to anything instead of
removing them).

> and needs file format changes.
What file format changes would be required to support stitching vias if
the items' nets are changed only in the situations pointed above?

Cheers,
Tom