kicad-developers team mailing list archive

[Wayne Stambaugh <stambaughw@xxxxxxxxx>]

When I export the attached board to VRML.  The graphic text on the front
silk screen of the board is not shown.  It appears that the graphical
circle on the front silk screen is either obscuring the text or the text
on the front silk screen layer has been completely replaced by the
circle rather than added to it.  If you remove the circle from the front
silk screen layer, the front silk screen text magically reappears on the
vrml export.  Is this a bug in our vrml exporter or is this just a
weakness in the vrml file format?

Cheers,

Wayne

(kicad_pcb (version 4) (host pcbnew "(2015-09-08 BZR 6170)-product")

  (general
    (links 0)
    (no_connects 0)
    (area -6.374601 -6.374601 6.374601 5.829301)
    (thickness 1.6)
    (drawings 6)
    (tracks 0)
    (zones 0)
    (modules 0)
    (nets 1)
  )

  (page A4)
  (title_block
    (title "PCA180 Isolated Dual Channel Hall Effect Board")
    (date 2015-08-28)
    (rev NC)
    (company "Motion Sensors, Inc.")
    (comment 1 "768 Pitts Chapel Rd.")
    (comment 2 "Elizabeth City, NC 27909")
  )

  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )

  (setup
    (last_trace_width 0.2032)
    (trace_clearance 0.254)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.2)
    (segment_width 0.2)
    (edge_width 0.2)
    (via_size 0.635)
    (via_drill 0.381)
    (via_min_size 0.4)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 0.762 0.889)
    (mod_text_width 0.1524)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.2)
    (aux_axis_origin 0 0)
    (visible_elements 7FFFFF7F)
    (pcbplotparams
      (layerselection 0x00030_80000001)
      (usegerberextensions false)
      (excludeedgelayer true)
      (linewidth 0.050000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (hpglpenoverlay 2)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
  )

  (net 0 "")

  (net_class Default "This is the default net class."
    (clearance 0.254)
    (trace_width 0.2032)
    (via_dia 0.635)
    (via_drill 0.381)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
  )

  (gr_circle (center 0 0) (end 4.5974 0.254) (layer F.SilkS) (width 0.2))
  (gr_text FRONT (at 0 0) (layer F.SilkS)
    (effects (font (size 1.143 1.016) (thickness 0.2032)))
  )
  (gr_text BACK (at 0 0) (layer B.SilkS)
    (effects (font (size 1.143 1.016) (thickness 0.2032)) (justify mirror))
  )
  (gr_circle (center 0 0) (end 5.8166 0) (layer Dwgs.User) (width 0.0254))
  (gr_line (start -3.515125 5.2578) (end 3.515125 5.2578) (layer Edge.Cuts) (width 0.1))
  (gr_arc (start 0 0) (end 3.515125 5.2578) (angle -292.5) (layer Edge.Cuts) (width 0.1))

)