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Re: Improving SCM behaviour of kicad_pcb

 

I've noticed another annoying churn in eeschema, when annotating the
schematics power flags get re-annotated even if they already had refs
assigned from before and the annotate command is not set to overwrite. I
don't know if it does it all the time but it does it fairly often in my
experience.

On Mon, Jul 10, 2017 at 11:52 AM, Wayne Stambaugh <stambaughw@xxxxxxxxx>
wrote:

> Forward compatibility is highly unlikely given our limited manpower.
>
> There is a fundamental misunderstanding about net names.  Pcbnew does
> not have anything to do with naming them.  Pcbnew on reads the net names
> from the net list.  The net names are generated by Eeschema and passed
> to Pcbnew so the issue is with Eeschema.  Currently, Eeschema does not
> save undefined (unlabeled) net names.  It automatically renumbers them
> each time a new netlist is generated.  One work around is to label every
> net in Eeschema using some type of label.  I do this so I know which
> signals I'm routing.  I've never found net names such as N-##### very
> useful.
>
> I am considering saving automatically assigned net names in the new
> schematic file format but that is still uncertain at this point.
>
> On 7/10/2017 11:26 AM, José Ignacio wrote:
> > The problem is that you can't make old kicad read the new format, unless
> > a patch gets backported.
> >
> > On Mon, Jul 10, 2017 at 10:19 AM, Kristoffer Ödmark
> > <kristofferodmark90@xxxxxxxxx <mailto:kristofferodmark90@xxxxxxxxx>>
> wrote:
> >
> >     Could we not support reading both formats, but only write one format?
> >
> >     - Kristoffer
> >
> >
> >     On 2017-07-10 09:36, Maciej Sumiński wrote:
> >
> >         I think there is a lot of code that assumes consecutive net
> >         numbering.
> >         Instead, we could simply save net names instead of net numbers
> >         and let
> >         KiCad use net codes as convenient. One significant problem is it
> >         would
> >         cause the .kicad_pcb file format change, making it completely
> >         unreadable
> >         by the current stable.
> >
> >         Regards,
> >         Orson
> >
> >         On 07/01/2017 04:49 AM, hauptmech wrote:
> >
> >
> >             We have a fairly complex board that needs to be done
> >             yesterday. We've
> >             been experimenting with simultaneous editing of the pcb with
> >             moderate
> >             success.
> >
> >             We are using git. Each person works in a different area of
> >             the board,
> >             and we merge the results periodically.
> >
> >             Because of the time crunch, we are only focusing on what
> >             works in this
> >             process, and staying away from edits that do not work.
> >             Moving footprints
> >             and laying tracks works fine.
> >
> >             A couple things I've noticed that could improve things:
> >
> >             net indexes of nets are not stable. Maybe
> >             eeschema/netlist.cpp:369
> >             Maybe we could wait until we get close to running out of
> >             integers before
> >             we do this?
> >
> >             module order gets changed in some edits (Not sure but
> >             probably "fix
> >             module file details and update modules in pcb" type edits).
> >             Ordering
> >             modules by reference would fix this.
> >
> >
> >             We are getting enough benefit that we'll keep refining the
> >             technique.
> >
> >
> >
> >
> >
> >
> >
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> >
> >
> >
> >
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> >
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