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Message #32465
Re: [RFC] Eeschema bus upgrades and new connectivity algorithm
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To:
kicad-developers@xxxxxxxxxxxxxxxxxxx
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From:
Wayne Stambaugh <stambaughw@xxxxxxxxx>
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Date:
Fri, 15 Dec 2017 08:27:56 -0500
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In-reply-to:
<CA+qGbCD=zdBs-b6hFs9mLwUw_U7GnBJjnFWMTmi7aVbWEJpNWg@mail.gmail.com>
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User-agent:
Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0
Jon,
I finally had time to watch your video. The new bus connection work
looks great! Hopefully I'll be able to find some time in the not too
distant future to take a look at the code. I'm really interested in the
new real time connection algorithm. Keep up the great work.
Cheers,
Wayne
On 12/13/2017 11:15 PM, Jon Evans wrote:
> Hi all,
>
> As some of you know, I've been working on some new features for Eeschema
> that expand the capabilities of buses.
> These features are not yet complete, but I wanted to share my progress
> to get early feedback.
>
> Since there are a number of things, I have made a ~4 minute demo video,
> in which I walk through them and discuss:
>
> https://youtu.be/z6x0xiKgDIc
>
> In case you don't want to watch the video, here are the new features:
>
> * The existing style of bus is now referred to as a Bus Vector (for
> example: "A[7..0]")
> * New concept: Bus Groups, for adding arbitrary nets to a bus
> o Defined in a list, separated by spaces, enclosed in curly
> braces. For example: "{DP DM}"
> o Can contain bus vectors as well as plain nets, for example
> "{A[7..0] D[7..0] OE WE}"
> o Can have an optional name in front, like "MEMORY{A[7..0] D[7..0]}"
> o If you add a name, the resulting nets will have the name
> prefixed on the front, like "MEMORY.A7"
> * New concept: Bus Aliases
> o You can use aliases to define shortcuts for bus groups.
> o For example, you could create an alias called "USB" that refers
> to the nets "DP" and "DM"
> o Then, you can define a bus group as "{USB}" which will contain
> both of those nets.
> o You can also add a label, like "USB1{USB}" which will result in
> nets "USB1.DP" and "USB1.DM <http://USB1.DM>"
> o Bus Aliases are editable through a new dialog, and saved with
> the schematic file.
> * New tool: Bus Unfolding
> o Right click on a bus, and you can easily break out any of its
> members into a bus entry, label, and wire.
> o You place the label (and set the bus entry orientation) with the
> first click, and then can continue wiring.
>
> In order to support this work, I am also working on a new connectivity
> algorithm for Eeschema.
> This algorithm stores the resulting connectivity information with the
> graphical objects on the schematic, meaning that it's quite easy to look
> up what net any particular object is part of. The new algorithm is also
> significantly (i.e. an order of magnitude) faster at generating
> connectivity than the current netlisting algorithm in my testing so
> far. It will support partial updates of the connectivity when editing
> the schematic, so the net information will always be in sync when
> adding/removing/editing items in the schematic.
>
> The combination of a faster algorithm and caching of the connectivity
> results in dramatic speedups when working with large designs.
> For example, Chris' motherboard project (which is a great benchmark, by
> the way!) takes several seconds to highlight nets in the current master
> branch, and with my changes, you can highlight any net instantaneously.
>
> Although it is not yet far enough along to demonstrate this, I plan to
> use this new connectivity algorithm to generate netlists for export, and
> replace the existing algorithm entirely.
>
> You can check out the code in my branch here, but be warned that it is
> not yet complete, so I am not yet proposing that anyone do exhaustive
> testing of it and report bugs (because I already know about many of the
> bugs you will find :-)
>
> https://github.com/craftyjon/kicad/tree/bus_upgrades
>
> Thanks,
> Jon
>
>
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