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Re: Silk screens over pads and naming

 

On Mon, Jun 02, 2014 at 07:34:12PM +0100, John Beard wrote:
> button. What client do you use?

mutt. Obviously it doesn't handle it (but could be coerced...)

> What is the cost of the yellow layer? It seems to me to show some useful
> information (the nominal physical presence of the component, including
> the extent of pad overlap) without actually being printed onto the board
> and needing silkscreen, ink, etc. Unless you mean cost to the
> librarians, in which case I think this c/should be optional (assuming
> there was software support in the first place)?

The 'cost' of the fabrication layer is simply the full component outline
(99% of the times a rectangle) and a corner line for pin 1. But it's not
supported anyway.

> And maybe we could say the general silk screen border width is 0.2mm,
> if this a known constraint of fabricators using silk-screens to do the
> silk screen layer?

It's not really a constraint, they simply tell you: if it's smaller
I don't guarantee a thing (and proceed with a 0.2mm line:D). So small
refdes come out as ink blobs

> > some CAD system (the mentor ones, I guess, since they somewhat
> > invented it) actually do DRC on courtyard to avoid collision and such.
> 
> Physical-collison-detecting DRC sounds handy - I nearly put a resistor
> under a QFP on my first KiCad PCB!

It happens with very big components too (thing about heatsinks). Don't
worry it's a common mistake (however you can usefully nest the gate
resistor in the lower space of a D3PAK, right beside the pin...)

There is another reason for courtyard excess, namely reworking
clearance. BGAs have extra courtyard because the desoldering nozzle is
big!

-- 
Lorenzo Marcantonio
Logos Srl


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