kicad-lib-committers team mailing list archive

[John Beard <john.j.beard@xxxxxxxxx>]

On 02/06/14 20:18, Lorenzo Marcantonio wrote:
> On Mon, Jun 02, 2014 at 07:34:12PM +0100, John Beard wrote:
> > What is the cost of the yellow layer?
>
> The 'cost' of the fabrication layer is simply the full component outline
> (99% of the times a rectangle) and a corner line for pin 1. But it's not
> supported anyway.

But if it were, it wouldn't be part of the actual board, or have I
misunderstood? So it wouldn't increase the actual cost of a unit, but is
rather used for having a reference document to hand (presumably
partnered with the BOM)?

> It's not really a constraint, they simply tell you: if it's smaller
> I don't guarantee a thing (and proceed with a 0.2mm line:D). So small
> refdes come out as ink blobs

Well, a practical lower limit rather than constraint. But would that be
a good "default" value for the major silk lines and text? I used 0.2 for
the outline and 0.15mm for the text in my first attempt at the
PicoBlades. I think a lot of people using KiCad (like me) are not using
very advanced fabrication technologies!

> > Physical-collison-detecting DRC sounds handy - I nearly put a resistor
> > under a QFP on my first KiCad PCB!
>
> It happens with very big components too (thing about heatsinks). Don't
> worry it's a common mistake (however you can usefully nest the gate
> resistor in the lower space of a D3PAK, right beside the pin...)

Good to know, I'll keep that in mind!

> There is another reason for courtyard excess, namely reworking
> clearance. BGAs have extra courtyard because the desoldering nozzle is
> big!

I was thinking more of last time I tried to manually hot-air reflow a
joint that was too close to a plastic header and melted it out of shape.
Why make those out of such low-melting-temperature and combustible
material, I ask! ;-)

John