kicad-developers team mailing list archive

[jean-pierre charras - INPG <jean-pierre.charras@...>]

Dick Hollenbeck a écrit :

> > the m_Layer parametre is the layer for tracks only.
> > for vias, m_Layer is the layer pair: an a via is on all layers from a 
> > starting layer to an ending layer
> > 4 bits are for the starting layer and 4 bits are for the ending layer:
> > if m_Layer is 0x0F:
> > for a track, the meaning is : track is on layer 15 (component)
> > for a via, the meaning is : via is on all layers, FROM layer 0 
> > (copper) TO layer 15 (component)
> >
> >
> > Vias "through" connect All layers (for pcbnew from copper to component 
> > layer, because copper is the layer 0 and component is the layer 15).
> > And therefore the m_Layer param always is 0x0F ( or 0xF0 , which is 
> > equivalent)
> > The layer pair choice allows you only to switch easily from a layer to 
> > the other layer for the tracks.
> > But vias are from layer 0 to layer 15 (from copper to component).
> >
> > Only blind vias or buried vias must be from layer n to layer m (n and m 
> > = 0 ..15)
> >
> > But blind vias or buried vias are experimental features, not really 
> > tested, and excellon files do not support them.
> > (because only few manufacturers are able to made borads with these vias) 
> > and i don't made any board with thes vias.
> >
> > You *** MUST *** have all yours vias with layer from 0 to 15 (m_Layer = 
> > 15).
>
> Thank you. I was thinking the layer pair, obtainable using 
> ReturnLayerPair(), had to do with electrical continuity, not physical 
> extent. 
>
> But instead it sounds like the layer pair is more about physical extent 
> of the perpendicular physical hole, and nothing to do with electrical 
> continuity, correct? 
Correct, and via through have always the same extent (from layer 0 to 
layer 15), whenever the connected tracks.

> The electrical continuity seems to be dealt with by tracks attaching to 
> a via on a given layer, some of which will subsequently be overwritten 
> by zones, correct?
Correct again.

The electrical continuity exists for all layers and therefore for all tracks connected to a via through, whenever their layers


And i have removed your change in drc.cpp (seen drc.ccp, I hace 
translated comments in english ( in my english...))

Your problem is not due to a bug in drc.cpp ( perhaps you have 2 pads at 
the same location, or other problem)

With you change one can connect 2 pads with a netcode set to 0.
But when a pad has the netcode 0, it must *NOT* be connected (no net 
for this pad, or if you prefer, this is a not connected pin in schematic)
--
Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402 St Martin d'Heres Cedex

Recherche :
Grenoble Image Parole Signal Automatique (GIPSA - INPG)
46, Avenue Félix Viallet
38031 Grenoble Cedex