kicad-developers team mailing list archive

["Frank Bennett" <bennett78@...>]

--- In kicad-devel@xxxxxxxxxxxxxxx, "Tim Hanson" <tim@...> wrote:
> 
> How should this be done?
Tim:

I see this new scheme was checked in to svn:
/s/opt/svn/kicad/trunk/kicad# svn log eeschema/netlist.cpp |less
r758 | lifekidyeaa | 2008-02-14 22:32:33 -0700 (Thu, 14 Feb 2008) | 4
lines

I would suggest in the demo directory that the netlists be
re-generated, reviewed (svn diff) and checked in...I assume you
did try to import some into cvpcb & pcbnew.

Some day it would be nice to have a regression test suite to
make sure developers have not broken the PCB design flow :^)

Thanks for the netlist improvements. This helps alot when designing
a PCB...which reminds me side note:

Enhancement request: pcbnew should be able to generate a netlist 
and compare it to the original eeschema netlist and report differences
(other that an added footprint)? The eeschema netlist is redundant in
that the nets are listed by component and netname. The netname
list is broken (missing nets) but is for reference only.

Frank Bennett
> 
> I'm happy to code it up, just want some input.
> 
> Also, is anyone else annoyed when, also in eeschema, you delete a long
> straight line, and instead of the deletion terminating at the next
node or
> intersection, it deletes *everything*. This frequently forces me to redo
> long lines.. worth a fix?
> 
> thanks yall,
> Tim