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Re: Re: EESchema XOR-Artifacts



I don't think that is new behavior. The board I have been working on forever was positioned at the origin, and its been happening to me for over a year:

The yellow boarder is not drawn properly if it coincides with the origin.

This is not new behavior.

BTW, I don't know what "s/b" means.


Frank Bennett wrote:
*pcbnew Artifacts *(I don't recall seeing before)

In the following tx.brd the horizonal line @(0,0) cancels the bottom of the board outline, the vertical line @(0,0) is white s/b yellow and the TRACK up from U1-2 s/b red (component layer) This brd was generated by a xml4pcb parser I am creating as a project on sourceforge...I may be at fault for mis-interpreting the brd file format,
included as an attachment!

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