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Re: suggest and doubt


--- In kicad-devel@xxxxxxxxxxxxxxx, "seadistant" <seadistant@...> wrote:

> 1.pcb reuse(pads named) and protel named it "channel route " it just likeas "place hierarchical sheet" ,yeah if they have similar schematic diagram,why not similar pcb layout?

Uhmmm... something like macrocells in chip layout, then... never had any reason to need something like that (mostly because... well, if things are SO similar, we design only one PCB to be populated differently:D). But maybe for HF work it could be useful (but before that we should do striplines, balanced pairs, parallel routing and such more useful things :D)

> 2.why not combin "eeschema" and "cvpcb" ?we have to use a same 

This is actually a thing I never liked in the workflow... 
We do the schematic, export the netlist, cvpcb builds an annotated netlist,a component file and a stuff file... then we have to load back the stuff file in eeschema! It's crazy! Why not junk the component and stuff file and simply use the netlist to carry all the informations???

IIRC there are no extra info which can be obtained only from the component or the stuff file... even if you keep cvpcb around eeschema could pick up the chosen packages for backannotation simply from the netlist, right? (but anyway cvpcb has so few features that it could simply integrated in eeschema...)

Other question: why are there two mutually incompatible BOM listers? (anyway it's weird to do a BOM from the layout :D)

Ah, before I forget: the BOM generator has issues... the first time runs fine, the second one crashes (segv probably)...