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Re: Sweet parser


> Pin name is, in fact, actually a pin description, and currently is just a comment.
> About pin "numbers" (currently a 4 characters identifier) I believe an enhancement in Eeschema could be the support of pins having 
> multiple pin numbers.
> I see 2 cases:
> -Power pins in large ICs:
>   they have 100 or more GND, VCC .. pins.
>   In schematic an enhancement could be: put only one pin having one pin name (or description) and a lot of pin numbers.
> -"Bus pins"
>   The is in fact a similar case: one pin having many pin numbers.
>   Useful for components like memories and microprocessors to handle data bus and address bus with only 2 pins.
> the difference between these pins is mainly for netlist generation.
> In library files format and load/save functions, just allow the ability to store more than one pin number per pin.
> The cost is low.

You want to run an entire microprocessor on one wire?  Sounds like a traffic
jam to me, the electrons will end up with road rage.  :)

Thanks for the clarification and out of the box idea on bus/pins.  We can
spend a few emails embellishing the idea.

If I tie two such pins together with one wire, and these two bus-pins are on
two different chips, what ensures that the two pins hold all the same pin
numbers?  What if the second bus-pin only has 90% of the pin numbers in it? 
Do we have to have a public "class-definition" system for bus-pins?   Must
the two pins have all the same pin numbers in order to be tied together?

This is one to sleep on.   (Don't know if that is a known expression in
languages other than in English.  But in English it assumes that the
subconscious mind stays active solving problems even when you are not
spending conscious energy on them.)


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