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Re: Just shipped the first kiway-ed board

 

On Thu, Apr 10, 2014 at 09:40:58AM +0200, Tomasz Wlostowski wrote:
> the next release. BTW. vector/topological routers are usually gridless ;)

Only an aestethic thing of mine :D I prefer neat trackage, unless it
couples bad :P

> >  P&S for long range on mixed
> >signals would be madness anyway :D
> Could you elaborate more on that?

Board partitioning is rarely perfect, so if, even by mistake, you route
a signal near to noisy logic or, worse, power stages you have horrible
noise issues. Once had a gate drive track suffering interference from
a *shielded* inductor at more than 10mm from the track. Mosfets fired at
will from the inductor noise, had to reroute the whole stage. That the
inductor carried 5A pulses *could* have helped the noise :D

Not crossing split planes is another big problem with autorouters
(unless you implement route zones).

Another thing is that the current class clearance model doesn't model
some real life issues (IEC 60950 and related stuff). In fact I've never
seen an EDA tool handling them in full (for example where the mask is
removed, like on a pad, the clearance is different due to the different
creepage index... unless you coat the whole board).

> The new P&S will have that. Also a mark-DRC-errors-without-pushing mode will
> be available.

Like in 'be careful you are going too near'? Could be useful. I already
did a patch to better show the current 'head banging' behaviour of the
standard track tool (didn't get accepted:P). Using it all the day.

-- 
Lorenzo Marcantonio
Logos Srl


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