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Message #19047
Re: PNS diferential pair netnames update
> On Jun 30, 2015, at 11:14 AM, Simon Richter <Simon.Richter@xxxxxxxxxx> wrote:
>
> Hi,
>
> On 30.06.2015 19:29, Andy Peters wrote:
>
>>> Ideally, I'd like this as attributes on the component pins, and then
>>> either inherited directly or at least verified by the ERC.
>
>> One argument against making this a pin attribute rather than a net attribute: FPGA pins can be single-ended or differential depending on the particular design.
>
> I have an evil plan for that: per-instance configuration options.
I envision you in your lair, rubbing your hands together and cackling with glee!
> In the symbol, I'd like to allow alternative configurations for each
> pin, along with dependencies.
>
> This is most useful for connectors, which currently do not take part in
> ERC at all (by being declared "passive"); the per-instance configuration
> would allow pin types to be assigned without altering the component.
What I have done for connectors where I have a "standard usage” (JTAG connectors for Xilinx or Silicon Labs dongles) is to draw the symbols and give each pin the application-specific net name and pin type. The footprint matches the actual part, of course, and I have a “company part number” in the symbol which points to the right thing as well. The BOM, then, after processing, just calls out the proper vendor part number.
> For anything programmable, I/O lines can be narrowed down to "input" or
> "output"; I'd also like to give the user the option of using one of
> several names for the pin. E.g. if there is a dedicated SPI controller
> in the IC, there'd be a configuration "use the SPI controller", which
> sets up the pins as MISO (in), MOSI (out), SCLK (out) and CS (out), and
> a different configuration "use these pins as I/O", which would set them
> as "GPIO1" (bidi), "GPIO2" (bidi) etc., with the option of narrowing
> them down further. A differential pair would be another configuration.
Kicad would win a whole bunch of new converts if you (we, us, whomever) could do this. Basically, your suggestion is to add a “pin configurator” tool, which knows about some parts.
Say the part in question is an Atmel SAM3U4CA. Most I/O pins can be configured as just a standard I/O pin as well as being specific to one or two peripherals. This pin configurator tool would need to start at a higher level, then. You pick the peripherals you want to use, and then it “knows” how the pins in question should be configured, and sets the schematic symbol pin names (very helpful!) and port type appropriately. Pins not part of a peripheral but instead are GPIO can then be configured based on whether they’re in, out, or bidirectional, and the user should also be able to give them a name.
Some micro vendors offer peripheral configuration tools which set up the chip per user needs. If that configuration could be imported, then the user doesn’t really need to do any work at all.
FPGAs don’t have standard peripherals but the ability to edit pins for directional/type and give them a meaningful name would be welcome.
I recognize that there’s the small matter of programming necessary to make this all happen.
-a
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