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Re: Slow performance in pcbnew (PNS/GAL only) on high-fanout nets

 

On 02/02/2016 01:29 AM, Maciej Sumiński wrote:

Ok, then alternatively we should check the courtyard layers for
overlapping. Otherwise it is possible to put two components in the same
place, and that is an error as you will not able to solder both.

Actually I have intentionally located two footprints so they overlap.
Only one or the other (not both) are stuffed on a given board. One
board, two different BOMs, two different assembles. Very common trick.
Not really a DRC error. There needs to be a way to tag the two parts as
alternates.

--
Later,
Jeff


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