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Re: Slow performance in pcbnew (PNS/GAL only) on high-fanout nets

 

On 03.02.2016 07:33, Jeff Barlow wrote:
Actually I have intentionally located two footprints so they overlap. Only one or the other (not both) are stuffed on a given board. One board, two different BOMs, two different assembles. Very common trick. Not really a DRC error. There needs to be a way to tag the two parts as alternates.
Indeed a very common trick.
In the ZUKEN EDA tool this is realized in that way:
Components have a (IIRC) "multipitch" property.
If the argument of this property has the same content for all parts that need to be placed on the same PCB location it will cause no DRC error. e.g. if you want to be able to place either a resistor or a ferrite on the same footprint, both have a "multipitch=R100_L100" entry.

  André


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