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Message #26504
Re: Via Stitching
Hi,
Finally Via Stitching without tracks is at zone tool. I tested it little
bit, but more tests are needed. This patch replace all other patches. Do
not use them, use only this patch. I think this is worth of try. I am going
to use it anyway, even if it do not get any acceptance. First patch is for
Fedora users. It makes possible to build Kicad in Fedora release wxWidgets
libs whitout building wxWidget from source. I do not know has anybody else
that problem, but I had.
Heikki
On Tue, Sep 27, 2016 at 6:46 PM, Heikki Pulkkinen <hei6mail@xxxxxxxxx>
wrote:
> Hi
>
> And I really practice. I made improvement and forgot to copy all. So
> improvement is in these two patches. I hope this suggestion is accepted as
> a new feature.
>
> Heikki
>
> On Tue, Sep 27, 2016 at 2:31 PM, Heikki Pulkkinen <hei6mail@xxxxxxxxx>
> wrote:
>
>> Hi,
>>
>> As in practice, I made a patch file of my changes Not only diifs. It is
>> SHIFT-ALT-V hotkey whitch make buried and blind vias, as it is in routing
>> too.
>>
>>
>> Heikki
>>
>> On Sun, Sep 25, 2016 at 2:25 PM, Heikki Pulkkinen <hei6mail@xxxxxxxxx>
>> wrote:
>>
>>> Hi,
>>>
>>> I made some improvements to my patch of via stitching. Now you can just
>>> point copper pour place and press V, it make trough via. If you press
>>> SHIFT+CTRL+V it make buried or blind via.It does not change working layer.
>>> Only when you place buried or blind via from different layer than it's
>>> layer pair is. I think that it is quite easy to shoot board full of copper
>>> pours connecting vias. It is possible to remove connecting tracks from old
>>> designs. Just delete connection from pad and use clenup. Only have to
>>> remember that if there are not at least two copper pours in same netcode in
>>> different layers via is deleted too. Any support?
>>>
>>>
>>> Heikki
>>>
>>> On Sat, Sep 24, 2016 at 3:06 PM, Heikki Pulkkinen <hei6mail@xxxxxxxxx>
>>> wrote:
>>>
>>>> Hi everybody,
>>>>
>>>> This is my suggestion to via stitching without any tracks. It connects
>>>> unconnected vias in different copper pours witch has same netcode. Adding
>>>> vias is normal routing process without routing tracks. Start - Change Layer
>>>> - End. Tool that do those things automatically would be good, so you can
>>>> add all vias in same layer. After adding vias, run "Fill or Refill All
>>>> Zones" that "Clenup tracks and vias" do not remove partly connected vias.
>>>>
>>>>
>>>> Heikki
>>>>
>>>
>>>
>>
>
From d5af2b7d23f61e27fcb7e6944450fe9d2599f2c1 Mon Sep 17 00:00:00 2001
From: heikki <hei6mail@xxxxxxxxx>
Date: Sun, 2 Oct 2016 11:08:51 +0300
Subject: [PATCH 1/2] Fedora build against compat-wx libs
MIME-Version: 1.0
Content-Type: multipart/mixed; boundary="------------2.7.4"
This is a multi-part message in MIME format.
--------------2.7.4
Content-Type: text/plain; charset=UTF-8; format=fixed
Content-Transfer-Encoding: 8bit
---
CMakeModules/FindwxWidgets.cmake | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--------------2.7.4
Content-Type: text/x-patch; name="0001-Fedora-build-against-compat-wx-libs.patch"
Content-Transfer-Encoding: 8bit
Content-Disposition: attachment; filename="0001-Fedora-build-against-compat-wx-libs.patch"
diff --git a/CMakeModules/FindwxWidgets.cmake b/CMakeModules/FindwxWidgets.cmake
index 9a6e56f..60856a8 100644
--- a/CMakeModules/FindwxWidgets.cmake
+++ b/CMakeModules/FindwxWidgets.cmake
@@ -733,7 +733,8 @@ else()
#-----------------------------------------------------------------
# Support cross-compiling, only search in the target platform.
find_program(wxWidgets_CONFIG_EXECUTABLE
- NAMES wx-config wx-config-3.1 wx-config-3.0 wx-config-2.9 wx-config-2.8
+ #Fedora needs compat-wx* libs and wx-config-3.0-gtk2.
+ NAMES wx-config-3.0-gtk2 wx-config wx-config-3.1 wx-config-3.0 wx-config-2.9 wx-config-2.8
DOC "Location of wxWidgets library configuration provider binary (wx-config)."
ONLY_CMAKE_FIND_ROOT_PATH
)
--------------2.7.4--
From 25fa489829536661242b59def655876d9a06d3d9 Mon Sep 17 00:00:00 2001
From: heikki <hei6mail@xxxxxxxxx>
Date: Sun, 2 Oct 2016 11:19:28 +0300
Subject: [PATCH 2/2] Via Stitching tool
MIME-Version: 1.0
Content-Type: multipart/mixed; boundary="------------2.7.4"
This is a multi-part message in MIME format.
--------------2.7.4
Content-Type: text/plain; charset=UTF-8; format=fixed
Content-Transfer-Encoding: 8bit
---
pcbnew/connect.cpp | 72 +++++++++++++++++++++++++++++++++++++++++
pcbnew/edit.cpp | 33 +++++++++++++++++++
pcbnew/hotkeys_board_editor.cpp | 8 +++++
pcbnew/onrightclick.cpp | 12 +++++++
pcbnew/pcbnew_id.h | 2 ++
5 files changed, 127 insertions(+)
--------------2.7.4
Content-Type: text/x-patch; name="0002-Via-Stitching-tool.patch"
Content-Transfer-Encoding: 8bit
Content-Disposition: attachment; filename="0002-Via-Stitching-tool.patch"
diff --git a/pcbnew/connect.cpp b/pcbnew/connect.cpp
index 50c3805..f907f78 100644
--- a/pcbnew/connect.cpp
+++ b/pcbnew/connect.cpp
@@ -34,6 +34,7 @@
#include <wxBasePcbFrame.h>
#include <pcbnew.h>
+#include <class_zone.h>
// Helper classes to handle connection points
#include <connect.h>
@@ -946,6 +947,77 @@ void PCB_BASE_FRAME::RecalculateAllTracksNetcode()
for( TRACK* track = m_Pcb->m_Track; track; track = track->Next() )
track->ViewUpdate();
+ //Connect unconnected single vias in copper pours.
+ int num_areas = m_Pcb->GetAreaCount();
+ if(num_areas > 1)
+ {
+ for( TRACK* track = m_Pcb->m_Track; track; track = track->Next() )
+ {
+ int netcode = track->GetNetCode();
+ const VIA* via = dynamic_cast<const VIA*>( track );
+ if( !netcode && via )
+ {
+ LAYER_ID via_top_layer, via_bottom_layer;
+ via->LayerPair( &via_top_layer, &via_bottom_layer );
+ wxPoint via_point = via->GetEnd();
+
+ //Collect all areas that hits with via.
+ std::vector<ZONE_CONTAINER*> area_v;
+ int front_layer_netcode = 0, bottom_layer_netcode = 0;
+ for( int area_index = 0; area_index < num_areas; area_index++ )
+ {
+ ZONE_CONTAINER* area = m_Pcb->GetArea( area_index );
+ if(area)
+ {
+ LAYER_NUM area_layer = area->GetLayer();
+ if( (area_layer >= via_top_layer) && (area_layer <= via_bottom_layer) )
+ {
+ if( area->HitTestFilledArea( via_point ) )
+ {
+ area_v.push_back( area );
+ //Check front and bottom hits. For main rule.
+ if( area_layer == F_Cu)
+ front_layer_netcode = area->GetNetCode();
+ if( area_layer == B_Cu)
+ bottom_layer_netcode = area->GetNetCode();
+ }
+ }
+ }
+ }
+
+ //Main rule. If front and bottom layer hits with same net code.
+ if( ( ( front_layer_netcode && bottom_layer_netcode ) )
+ && ( front_layer_netcode == bottom_layer_netcode ) )
+ {
+ track->SetNetCode( front_layer_netcode );
+ }
+ else //Other rule(s).
+ {
+ //Connect first two different zones have a same net code.
+ bool hit = false;
+ for( ZONE_CONTAINER* area1 : area_v )
+ {
+ for( ZONE_CONTAINER* area2 : area_v )
+ {
+ if( area1 != area2 )
+ {
+ int net_code1 = area1->GetNetCode();
+ if( net_code1 == area2->GetNetCode() )
+ {
+ track->SetNetCode( net_code1 );
+ hit = true;
+ break;
+ }
+ }
+ }
+ if(hit)
+ break;
+ }
+ }
+ }
+ }
+ }
+
// Sort the track list by net codes:
RebuildTrackChain( m_Pcb );
}
diff --git a/pcbnew/edit.cpp b/pcbnew/edit.cpp
index 471da31..db5495f 100644
--- a/pcbnew/edit.cpp
+++ b/pcbnew/edit.cpp
@@ -107,6 +107,8 @@ void PCB_EDIT_FRAME::Process_Special_Functions( wxCommandEvent& event )
case ID_POPUP_PCB_FILL_ALL_ZONES:
case ID_POPUP_PCB_REMOVE_FILLED_AREAS_IN_ALL_ZONES:
case ID_POPUP_PCB_REMOVE_FILLED_AREAS_IN_CURRENT_ZONE:
+ case ID_POPUP_PCB_PLACE_ZONE_THROUGH_VIA:
+ case ID_POPUP_PCB_PLACE_ZONE_BLIND_BURIED_VIA:
case ID_POPUP_PCB_PLACE_ZONE_CORNER:
case ID_POPUP_PCB_PLACE_ZONE_OUTLINES:
case ID_POPUP_PCB_EDIT_ZONE_PARAMS:
@@ -671,6 +673,37 @@ void PCB_EDIT_FRAME::Process_Special_Functions( wxCommandEvent& event )
m_canvas->Refresh();
break;
+ case ID_POPUP_PCB_PLACE_ZONE_THROUGH_VIA:
+ case ID_POPUP_PCB_PLACE_ZONE_BLIND_BURIED_VIA:
+ {
+ if( GetBoard()->GetDesignSettings().m_BlindBuriedViaAllowed &&
+ id == ID_POPUP_PCB_PLACE_ZONE_BLIND_BURIED_VIA )
+ {
+ GetBoard()->GetDesignSettings().m_CurrentViaType = VIA_BLIND_BURIED;
+ //Set right layerpair.
+ Other_Layer_Route( NULL, &dc );
+ Other_Layer_Route( NULL, &dc );
+ }
+ else
+ GetBoard()->GetDesignSettings().m_CurrentViaType = VIA_THROUGH;
+
+ TRACK* track = Begin_Route( NULL, &dc );
+ if( track )
+ {
+ if( track->GetNetCode() )
+ {
+ Other_Layer_Route( track, &dc );
+ End_Route( track, &dc );
+ Other_Layer_Route( NULL, &dc );
+ }
+ else
+ {
+ End_Route( track, &dc );
+ }
+ }
+ }
+ break;
+
case ID_POPUP_PCB_MOVE_TEXTEPCB_REQUEST:
StartMoveTextePcb( (TEXTE_PCB*) GetCurItem(), &dc );
m_canvas->SetAutoPanRequest( true );
diff --git a/pcbnew/hotkeys_board_editor.cpp b/pcbnew/hotkeys_board_editor.cpp
index 516388d..1f152b9 100644
--- a/pcbnew/hotkeys_board_editor.cpp
+++ b/pcbnew/hotkeys_board_editor.cpp
@@ -372,6 +372,14 @@ bool PCB_EDIT_FRAME::OnHotKey( wxDC* aDC, int aHotkeyCode, const wxPoint& aPosit
if( !itemCurrentlyEdited ) // no track in progress: switch layer only
{
+ //Add via with stitching
+ if( GetToolId() == ID_PCB_ZONES_BUTT )
+ {
+ evt_type = hk_id == HK_ADD_BLIND_BURIED_VIA ?
+ ID_POPUP_PCB_PLACE_ZONE_BLIND_BURIED_VIA : ID_POPUP_PCB_PLACE_ZONE_THROUGH_VIA;
+ break;
+ }
+
Other_Layer_Route( NULL, aDC );
if( displ_opts->m_ContrastModeDisplay )
m_canvas->Refresh();
diff --git a/pcbnew/onrightclick.cpp b/pcbnew/onrightclick.cpp
index f5ed5d0..d3d6b90 100644
--- a/pcbnew/onrightclick.cpp
+++ b/pcbnew/onrightclick.cpp
@@ -367,6 +367,18 @@ bool PCB_EDIT_FRAME::OnRightClick( const wxPoint& aMousePos, wxMenu* aPopMenu )
g_Board_Editor_Hokeys_Descr, HK_ZONE_REMOVE_FILLED );
AddMenuItem( aPopMenu, ID_POPUP_PCB_REMOVE_FILLED_AREAS_IN_ALL_ZONES,
msg, KiBitmap( zone_unfill_xpm ) );
+
+ msg = AddHotkeyName( _( "Place Through Stitch Via" ), g_Board_Editor_Hokeys_Descr,
+ HK_ADD_THROUGH_VIA );
+ AddMenuItem( aPopMenu, ID_POPUP_PCB_PLACE_ZONE_THROUGH_VIA, msg, KiBitmap( via_xpm ) );
+ if( GetDesignSettings().m_BlindBuriedViaAllowed )
+ {
+ msg = AddHotkeyName( _( "Place Blind/Buried Stitch Via" ),
+ g_Board_Editor_Hokeys_Descr, HK_ADD_BLIND_BURIED_VIA );
+ AddMenuItem( aPopMenu, ID_POPUP_PCB_PLACE_ZONE_BLIND_BURIED_VIA,
+ msg, KiBitmap( via_buried_xpm ) );
+ }
+
aPopMenu->AppendSeparator();
}
diff --git a/pcbnew/pcbnew_id.h b/pcbnew/pcbnew_id.h
index 92201c4..6c16506 100644
--- a/pcbnew/pcbnew_id.h
+++ b/pcbnew/pcbnew_id.h
@@ -124,6 +124,8 @@ enum pcbnew_ids
ID_POPUP_PCB_PLACE_DRAGGED_ZONE_OUTLINE_SEGMENT,
ID_POPUP_PCB_REMOVE_FILLED_AREAS_IN_ALL_ZONES,
ID_POPUP_PCB_REMOVE_FILLED_AREAS_IN_CURRENT_ZONE,
+ ID_POPUP_PCB_PLACE_ZONE_THROUGH_VIA,
+ ID_POPUP_PCB_PLACE_ZONE_BLIND_BURIED_VIA,
ID_POPUP_PCB_DELETE_MARKER,
--------------2.7.4--
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