kicad-developers team mailing list archive

[Tomasz Wlostowski <tomasz.wlostowski@xxxxxxx>]

On 10.10.2016 07:25, Strontium wrote:
> On 09/10/16 23:11, Wayne Stambaugh wrote:
>> On 10/8/2016 1:20 PM, Nox wrote:
>>
>> There is nothing here that has not been discussed before.  The reason
>> that freely assigning nets to vias has not been implemented is that
>> every implementation is a compromise.  If we allow random net naming of
>> vias, all manner of bad things can happen that are completely out of the
>> control of kicad.  Instead of your wtf moment being some tracks and vias
>> with no associated net being ripped up when you import a new netlist,
>> your wtf moment is a stack useless pcbs that you just spend money on.  I
> Wayne, respectfully this is where I believe you have missed the point. 
> If a designer assigns a net to a via, then THEY are responsible for the
> WTF moment.  IF Kicad rips up the nets the designer assigned to vias
> then KICAD is responsible for the WTF moment.  In one case the designer
> screwed up and in the other Kicad screwed the designer over.
> 
> Its as simple as that.
> 
> My original patch, posted many moons ago, fixed this problem neatly.  It
> did not allow a user to assign arbitrary nets, but if you plonked a via
> on a GND fill, it had a GND net, and that via would ALWAYS have a GND
> net until you did something explicitly to change it.  

Don't shout man.... What if your board has more than two layers. For
instance, there's a full VCC plane on one internal layer and another
full GND plane on another internal layer? Which plane the via you place
would belong to if vias were to take their nets from copper fills?

Cheers,
Tom