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Re: pcbnew - enable editing of associated net for tracks&vias

 

Hello Torsten,

I can clearly understand why you went down this road.

The patch I proposed handles all kinds of vias, blind, buried and through. And doesn’t require a special component. The problem I had with the "special component" which I did try, possibly after reading one of your posts, is you either have tons of them matching on your Schematic, OR you have tons of manually placed components with no schematic representation. Neither of which feels like a great solution to me, I dont consider a via as a Component, regardless of if its stitching or not.

And lets put the problem into perspective for people who havent used stitching vias, when I say a "ton" of vias, I mean potentially hundreds of them in a very small area. Its not just one or two. RF Designs require them at small (tiny) intervals down the edges of fills as guards and regularly placed throughout your fill zones to reduce capacitance between the gnd layers. Its a HUGE problem for people who need to use them, not just some minor annoyance. And then you do something like move a resistor, and suddenly your gnd layer reflows around it, well now you have to restitch that new area. Its a whole lot easier to just move existing vias around.

Stront

On 10/10/16 20:59, "Torsten Hüter" wrote:
Hi Jean-Pierre,
I have done several designs with KiCad and stitch vias. The simplest way for me is to create a module with a single through hole pad. I've even written a python script to automate the placement of these stitch vias (see the mailing list archive). That was never a big problem and works well with the stable KiCad version, no issues with zone filling or net calculations. I'm guessing that Altium PCB using a special primitive for stitch vias as well.
See http://techdocs.altium.com/display/ADOH/Via+Stitching
Only blind vias or burried vias are not possible when using a single pad module; Altium uses the start and end layer as attribute for these purposes.
--
So maybe having free pads with similar attributes - like Altium is using - is here an alternative solution. Also for mounting holes as well (currently you need to create a module for them).
Thanks,
Torsten
When this entity is defined, netnames will be no more a problem.

So: first, define what is this entity (The best choice is not trivial for me, and deserves to think about it), how vias are linked to (or owned by) this entity, how they are taken in account by DRC and zone filling algorithms, and only after see if net names issues still exist.


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