kicad-developers team mailing list archive

[Ouabache Designworks <z3qmtr45@xxxxxxxxx>]

On Wed, Mar 7, 2018 at 3:08 PM, Tomasz Wlostowski <tomasz.wlostowski@xxxxxxx
> wrote:

>
> Which features you think should go to separate programs?
>

Export netlist for one. It is a simple addition as long as your design fits
completely
on the sheet that you are editing but what happens if you have a multisheet
design?
Now you have to locate and read  all those other sheets from files.  What
used to
be a graphics editor now has to deal with a lot of other problems that have
nothing
to do with placing and displaying graphics.

What happens if you edit a schematic, export the netlist and are
interrupted before
you can save the schematic?  That might only happen one time out of a
thousand
but you now have a corrupt database where the schematic file doesn't match
the
netlist. Kicad is getting enough users to make that a real problem. We need
to
go through and prevent that from every occurring in the first place. You can
do that by placing the netlister in a separate program that only operates
on
the outputed files.

DRC has the same problem in that it depends on data that has to be located
and
read in from other files.


>
> Bear in mind that most PCB designers don't like the 'unix-style'
> workflow, if by that you mean writing makefiles, shell scripts or other
> programming just to stitch different 'independent programs that do their
> particular jobs well' together.


The user doesn't do the stitching. The tool smith does. EEschema will call a
netlist or DRC program to operate on the schematic files rather than on the
design image in memory.


>
> > Create a Pad Mux tool that lets you codesign the IC package and pinout
> > as part of the IC design team. That is the ultimate in pin swapping
> > capability.
> >
> Kicad is a PCB design tool. We don't aim to become an IC design tool.
>
> Tom
>

I used to be a PCB design engineer until I switched over to design IC's. My
tools
did not change, all I did was change libraries. It was great. My
deliverable to the
board designer was the symbol that they used for my chip. It was easy to
work
together have them try out different pinouts before we had to release.

That was back in the 90's. 10 years later our tools had diverged enough
that on my
latest chips the tool that we used to collaborate between the IC and PCB
teams was
a spreadsheet. The system architects that used to use schematic capture to
create
their block diagrams had switched over to using microsoft visio. We can do
a lot  better.

EEschema would make a great engineering tool for a lot of engineers if it
only had two
additional features. The first is true hierarchy and the second is
heterogeneous buses.
I understand that Jon Evans has the bussing working and we could deal with
the hierarchy
by writing out the data and processing it in separate programs.


John Eaton