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Re: Proper way to report bugs on branches
Le 28/01/2020 à 17:15, jp charras a écrit :
> Le 28/01/2020 à 15:32, Seth Hillbrand a écrit :
>> No need. It has already been reported with reproduction steps here
>> If you find a bug, use the standard bug reporting procedure but only
>> report bugs there that reproduce in master.
>> If you find a bug that doesn't exist in master but does exist in the MR,
>> then add a thread to the MR with the reproduction steps.
> In fact, issue 3811 is the result of an other (much more annoying) issue.
> Each time you save your .sch files, the order of items inside the file
> is changed, even if you just load and save your schematic, without any
> actual change.
> The result is:
> - One cannot compare anymore the old and new file: they are very different.
> - Because the order of units of a given component in the file has
> changed, when the file is reloaded, the timestamp of the component in
> netlist changes (I am guessing this is the timestamp of the first unit
> found in list that is picked).
This issue was created when replacing DLIST in Eeschema.
>> On 2020-01-28 08:04, Brian Piccioni wrote:
>>> Actually, that is the bug: every time I hit F8 one or more of RN3,
>>> RN4, RN5, and RN6 are shown as new components on the PCB. It deletes
>>> the old RNs and put new ones with the same name.
>>> I got RN3, RN4 then RN3, RN4, RN5 and RN6, then RN3, etc.
>>> Every time I hit F8 the thing rips up those RNs.
>>> This schematic has only had one sheet ever.
>>> I shall recompile the master branch and try and boil down the
>>> schematic to something simple to test.