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Re: Adhesive for SMD components

 

What I mean is I want it to be as simple as possible for potential
contributors. I don't want to require them to read the IPC-7351 documents.

So from what I understand, C says:

Everything at 0.15, except BGA which is 0.25 for <0.3mm, 0.5 for <0.5mm,
and then progressive from 0.5mm to 1mm.

Right? Since, I believe, we don't have any CGA in our libraries, I say we
just don't write it until it happens.

On Mon, Sep 15, 2014 at 5:52 PM, Lorenzo Marcantonio <
l.marcantonio@xxxxxxxxxxxx> wrote:

> On Mon, Sep 15, 2014 at 02:10:39PM -0400, Carl Poirier wrote:
> > I want to avoid exceptions as much as possible. Thus, I suggest we put
> all
> > LGA, CGA and BGA at 0.5. Is QFN also at 0.15?
>
> Is not an exception thing, it is the rule which is 'proportional', like
> annulus size for THT... and also slightly changes with every 7351 revision.
>
> In B revision (the current published one) the 0.15 applies to chips
> smaller than 0603, SODFL and SOTFL, BGA have 1 mm, aluminum cap (and
> crystal cans) have 0.5; everything else uses 0.25
>
> The newer unpublished C revision (which is the one implemented by all
> the current calculators) instead changes *all* the chips, DFN and QFN
> (all the 'no-leads' in practice, with or without pullback) to 0.15 and
> add the progressive scaling (not all the calculator do this) from 1 to
> 0.5 mm (0.5 for balls up to 0.5mm, 0.25 for balls up to 0.3mm). CGA have
> bigger allowance (who uses CGA anyway?:P) The official (more or less
> since it's unpublished anyway!) nominal courtyard excess for BGA however
> is still 0.5.
>
> However the default for C revision (seems that it will be merged into
> the new CM-770) goes from nominal to least... so the 'new defaults'
> will be more for people building cellphones than industrial equipment.
> Also they change many roundings from 0.05 mm to 0.01 mm.
>
> For manufacturing yield I still prefer the old B revision tables,
> nominal sizes and 0.05 mm rounding. I don't know how is the default
> library in kicad parametrized (i.e. how did you calculate the pad sizes?
> which clearance and process tolerances?) but for general purpose non-HDI
> boards (usually 0.2 or 0.15 clearance) it's easier to use. I'd say that
> when you consistently place 0402 parts with 0.1 clearance the least
> spacing could be considered. I usually do most of the work with 0.2
> clearance (0.15 costs more :D). When you have to fan out modern BGAs
> however
> it's usually mandatory the 0.1 clearance (except when you have *really*
> a lot of pins to the power plane and you can fan out the remainder on
> the signal layer).
>
> Of course when *you* have to replace the component when necessary it's
> wise to leave a bit more of space :P when you do a cellphone who cares,
> it's mostly a throw-away board (maybe the gods of reworking can touch
> these)
>
> By the way, current default parametrization for the IPC calculators is
> 0.15 clearance (0.2 against thermal slug); rounding is quite
> complicated, depending on what you are rounding it goes from 0.01mm to
> 0.1mm.
>
> Also take care that this is only the 'excess courtyard'; the full
> courtyard depends on manufacturing process parameters, mainly placement
> tolerance (usually ±0.1mm but some processes also use ±0.2 or ±0.05...).
> The rule of thumb is to place components so that the courtyards don't
> "touch", i.e. with at least 0.05mm between courtyard lines.
>
> As usual you give the gerbers to the fabricator and he tells you what
> has to be changed; last week I had to move stuff from the border due to
> the width of the depanelizer blade :P also ceramics near the edges are
> prone to cracking and many other things that can't be standardized
> anyway.
>
> PS: you don't gain a lot having a smaller courtyard on QFNs... while the
> package is smaller and there are no leads, usually there is a thermal
> slug so you have to fan out on the outside! QFPs instead can fan out
> (and have routes) even under the body...
>
> --
> Lorenzo Marcantonio
> Logos Srl
>
> --
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