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Re: zone fill with micro-vias


Tim Hanson wrote:

> >
> Further research is desired before a solution is chosen. I for one am
> not in favor of tying the solution to the fill tracks a.k.a "class
> SEGZONE" instances, if we can find an alternative.
> We should start out with an objective of finding a solution based on the
> zone container and invasive tracks from other nets, and the clearance in
> play from those invasive nets, and any internal keepouts.
> Many folks are doing this now, including freerouting. net. Even the
> Specctra DSN file spec has no notion of "fill tracks", so that means
> CADENCE specctra, electra, etc., have all managed to do it without the
> ho-key fill tracks.
> Dick
Obviously, thinking in matter of polygons is the best solution.
When others softs use tracks to fill copper poor, this is only at plot
time (when creating gerber files).
So the focus is on using polygons to manage zones (including DRC and
Plot files).

Jean-Peirre, Dick & all --

Ok, I disagree on this point. Until we have a zone filler that uses
polygons, we *should not* test connectivity with anything other than
the *actual copper* that is laid out on the actual board using
algorithm that we have, the rasterized fill. If the user chooses a
coarse rasterization, whether or not a connection is made to a
nearly-isolated zone 'island' can be dependent on the alignment of
vias and tracks relative to the grid of the rasterization. I think
doing things with polygons is correct and better, but only if we have
zones that are filled with polygons.

Alternately (or equivalently), if the zone fill test connection based
on laying out hypothetical tracks to see if they can fit through any
gaps without DRC violations, then these tracks should be included in
the board.

I think that filling a zone, though it is done as the last step in
board production, should be treated like laying out any other track,
at least with the present zone filling algorithm: it connects all nets
only when there will be copper in the finalized board to connect them.
This means that we add a bit more code onto the zone-fill code to
test and connect vias, tracks, and pads. Zone fill on my board takes
a few seconds, so a few seconds more should not be bad if it gives me
peace-of-mind that all my grounds and VDDs are connected properly.

Of course, I agree with you that pcbnew should be able to determine if
it can connect a pad/via/track to a zone without actually filling the
zone, but that seems to be a much more complex problem (and seems
isomorphic to writing an autorouter)...still IMHO better to get
something practical (if slow and hokey) until we have a new
zone-filling algorithm.


Why don't you add DRC support to gerbview? If you are listening carefully, you may have heard that the zone filling may not even be in Kicad in the near future and that we might move it to gerber file generation time. What about the free DFM site to test for your worries using the gerber files?

It is not that I don't understand your concerns. I understand every last one of them. But as I weigh *all* the costs and benefits, your idea is a dead end. I have about 20 copper zones on my board. I do not think it is appropriate to refill each time I drop a via into one of them.

This disagreement it probably large enough to be justification for a fork.

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