kicad-developers team mailing list archive

["Simon Huwyler" <simon.huwyler@xxxxxxxxxx>]

> > > The first question I am thinking is:
> > > Why a by layer constraints.
> > > Why do not have only 2 min clearance values: one for outer layers, one
> > > for inner layers.
> >
> > I also thought about that. Would also be good, yes.
> It could fix some of issues created by multiple constraints.
> Because there is no more multiple constraints.

ok, I see that I didn't understand what you meant. Am i right that you mean 
that your idea is constraints for NETxxx on outer layers, NET xxx on inner 
layers, NETyyy on outer layer, NETyyy on inner layers... ?
This I think is not a good idea. I thought about just removing all numbers 
for each layer an having just a set for outer and one for inner layers.
When you say that it "fixes the issue of multiple constrains" i completely 
disagree. In this context, having "multiple constrains" is NOT an issue, but 
a feature. Or, put differently, it's in the nature of the physics behind it. 
I think, Lorenzo has also written about it.
We have to distinguish between the sources of the constrains, and we MUST 
NOT mix them.
Why do you place a net constraint? Because you want a NET to have certain 
constraints. Why? Because this net carries much current, has high voltage, 
whatsoever.
Now, why do you have layer constraints? Because your manufacturer wants 
them.

Therefore, it is a fact that we have to deal with "multiple constraints". 
This is in most cases not an issue, because we can create a "net" constraint 
for "all the rest". But actually, calling this a "net constraint" is wrong. 
It works well, but it's wrong. It's not a "net constrain", but it's a 
"physical constraint". Why does it work most of the time? Because there is 
only one set for all layers. But what if it's not? Then, trying to model 
this physical constraint by a set of net constraints (which are applicable 
to outer, or inner, or both layers) is not the right way to go, I think. 
That's why I put it in the layer stack dialog. The "constraint" dialog is 
really a "net constraint" dialog. And the "layer stack" dialog tells about 
the PCB itself. And therefore, the layer constraints are not so wrongly 
placed there, are they?



> Good programmers never sleep.
> (I am not a good programmer)

:-) so, neither am I.

> This is a DRC error.
> You have to match the impedance (otherwise the signal integrity is broken).
> Therefore you have to fix this issue:
> change PCB width constraint and board price (i.e. manufacturing limit), or 
> the track width and epoxy thickness ...
> but only the designer knows what is good or can be made.
> Pcbnew just should set a DRC error.

Right. It should (and does, when I have finished it) set a DRC error if one 
of the following is true:
1. the width or clearance is lower than the constrain on that layer.
--> The manufacturer will reject your design.
2. The width (or clearance) is lower (hmmm... or higher???) than it must be.
--> your impedance will be wrong


> Perhaps this is a good idea: you can show a demo or a proof of your idea.
> This is very important.
> With a demo, discussing about alternatives or enhancements is more 
> productive.
> More work, and more benefit.

I'm a bit reluctant sending a built pcbnew.exe, because it's huge, and it's 
only working on Windows.
So, I think, the patch is better.
Actually, the one I attached should be fine for this purpose. It's not 
finished yet, as I said, but you can try what the idea is.
I must say again, for my particular problem with different constraints on 
inner layers, this is the most intuitive and elegant way I could imagine. 
Mixing these constraints with layer constraints would seem couner-intuitive 
to me because it wouldn't reflect the problem to be solfed.