kicad-developers team mailing list archive

[Lorenzo Marcantonio <l.marcantonio@xxxxxxxxxxxx>]

On Sat, Apr 27, 2013 at 03:09:11PM +0200, Simon Huwyler wrote:
> "layer stack" dialog tells about the PCB itself. And therefore, the
> layer constraints are not so wrongly placed there, are they?

Ouch this is so much complicatea to explain :D

Now I'm about to go algebric and defing the 'intersection of
constraint'... something like:
- Netclass A has to be at least 1mm wide and at least 0.2 clearance
- Layer 1 needs at least 0.5 clearance
  ==>
- Netclass A on layer 1 has to be at least 1mm wide and at least 0.5
  clearance

(it's simple interval arithmetic)

- Netclass B has to be exactly 0.5mm wide and clearance of exactly 0.3mm
  ==>
- Netclass B can't live on layer 1 (due to conflicting rules)

(Empty intersection)

It's done that way in safety relevant systems... you get all the
conditions and they *all* need to be true. It works the same in fuzzy
logic too :P

The UI would be something like a QBE grid or a mail filter setup.

In fact it could everything done with intervals: 'lesser than y' becomes
'between -inf and y', 'equal to x' becomes 'between x - epsilon and
x + epsilon' for example. PLEASE NOTE that, for example, checking for
'maximum clearance' would be *very* difficult, so it's only an example!

Rule resolution would be done that way: given a set of rules (DRC
database or whatever) extract all the rules which apply to the current
check (a single track check of course would extract the track size
rules, while a track-to-track would ignore them, for example). This
involves browsing the database and 'filtering' on the conditions (i.e.
I'm checking a track of class B, the rules must apply to all classes or
at least to class B). Compute the intersection of all the constraint
from these rules. Check if everything fits.

Given an 'adequate' (i.e. to be thought about:D) predicate set I think
that all the conceivable (useful) constraints could be built. After that
we hit the turing limit i.e. need some user written python function (as
already proposed).

The minimal 'functional' constraint I would use are something like:
1) Width in (range)
2) Clearance in (range) (as said before most probably has to be thinked
   about)
3) Pad size in (range)
4) Thermal spoke width in (range)

'Manufacturing' constraint are like (I'll list the CAM350/gerbtool ones)

5) Track-to-track distance >(dist)
6) Track-to-pad distance >(dist)
7) Pad-to-pad distance >(dist)

(I have no idea if it's useful to differentiate clearances in this way.
IMHO copper-to-copper is the manufacturing limit to be checked i.e.
condition 2)

8) Pad-to-drill >(size) (annulus check)
9) Track width >=(size) (same as 1)
10) Pad width >=(size) (same as 3)
11) Plated holes to copper >(dist) (*other* copper)
12) Unplated holes to copper >(dist)
13) Copper to border >(dist) (milling tolerance)
14) Drill to border >(dist) (milling *and* drilling tolerance)
15) Border-to-border >(size) (minimum cutter size, especially for card
    egdes)
16) Plated drill size >(size)
17) Unplated drill size >(size)

We already do some of these, of course. There are others but not
applicable for pcbnew (like 'plated drills without a pad') or advanced
ones that are maybe too much CAM-specific (like copper slivers, acid
traps and pin holes). These are also very heavy to check since you need
to convert to a polygon a whole net (not a track!) and then analyze the
subpolygons and the angle between edges. Nice but I can live without
them :D

Plated and unplated drills are separated because they are often done on
different machines, maybe with different features (expecially embedded
vias which can be laser evaporated...). In a conventional (non-HDI) flow
the 'first drilling' i.e. the plated holes is sometimes more precise
than the 'second drilling' (unplated) which is sometimes done by the
same machine that does the edge milling or scoring. Buried and blind
vias are much more complicated to handle because it depends on the exact
stackup of the board (no experience with that).

There are also more specific checks for solder mask/paste and silkscreen
(like: you can't have paste without a mask and copper underneath) or
even modification (solder mask ganging for fine pitch, but then there is
a different clearance for the copper below since it has no more
damming). These are really, really, really CAM issues and often you
don't even know the reference values. You *could* add checks for silk
thickness and clearance to the mask if you wanted (well, it would be
better to enlarge the silk scraping during plot). Also, for example,
minimum/maximum pad size could be applied (with different values) to the
paste masks: I had to recut a mask since paste didn't detach properly,
for example (it's called design for fabrication: it must be fabricable
but it must be *easily* fabricable, to give better yield).

Conditions would be like:
A) In netclass (set of classes) (the set could be 'any class')
B) Between netclass (class1) and (class2) (where there
   could be an 'any class' indicator to mean 'between class A and
   anything else')
C) On layer (set of layers)
D) ??? what else?

Please not that a 'manufacturing' DRC only cares about the layer (gerber
has no netclass assignment!) so conditions A or B are only for
'functional' DRC. However there is *no* need to differentiate between
them... in fact condition 1 is the same as condition 9 and 3 is like
condition 10. Conditions 5-7 cover condition 2; just apply the due
filters. Usually per layer contraints are only specified for 'outer'
layers and for 'inner' layers, but you can always add a rule for
specific layers. CAM350 also allow to define 'zones' in which the rules
(they call them 'streams') apply.

At the end: a 'rule' is a (set of) constraints and a set of conditions (they
must be *all* true).

-- 
Lorenzo Marcantonio
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