kicad-developers team mailing list archive

[jp charras <jp.charras@xxxxxxxxxx>]

Le 27/04/2018 à 22:33, Eeli Kaikkonen a écrit :
> Do I see some kind of gap in communication here? I know what Rene is talking about because I have
> designed solder mask defined pads. Wayne talks about "tolerances". But this is not about
> tolerances.  It's about designing a mask-only (or paste-only) pad with certain dimensions and then
> those dimensions changing according to some global value which is not fitting for that pad. For
> example 0.3x0.3mm mask area becomes 0.4x0.4mm while the purpose was to always have 0.3x0.3mm. It's
> OK with copper pads which have solder mask and paste defined, but not for mask-only or paste-only.
> The problem is that mask-only pad is handled as if it was a normal copper pad: the mask area is
> changed because it has a value 0 and there's also a global value > 0.
> 
> Eeli Kaikkonen
> 
> 2018-04-27 23:15 GMT+03:00 Rene Pöschl <poeschlr@xxxxxxxxx <mailto:poeschlr@xxxxxxxxx>>:
> 
>     Forwarded as i accidentally pressed on "Answer" instead of "Answer mailing list":
> 
>     How would you then design a footprint where you need the paste not to be
>     centered on the copper area (0201 resistors need this.)?
>     How would you design a footprint for a part including an exposed pad?
>     There the paste needs to be split up. (And yes we know our 65% paste
>     coverage rule will not be right for everyone but it should be ok for
>     most users.)
> 
>     How would you design a footprint for a part with a large "exposed" pad
>     for thermal reasons that has a reduced are where the copper is actually
>     exposed. (such footprints typically require a different mask clearance
>     in x and y direction.)
> 
>     How would you design a part where the copper pad should be a circle but
>     the paste pad a square? (It seems BGA footprints should be made that way
>     as it results in better paste stencil separation behavior)
> 
>     How would you define mask defined pads for example for a BGA? (if 0 is
>     not a good idea for a clearance setting why should any other number be ok?)
> 
> 
> 
> 
>     On 27/04/18 21:36, Wayne Stambaugh wrote:
> 
>         The smallest unit in board file geometry is 1nm.  However, all
>         tolerances are really determined by the capabilities of the board
>         manufacturer.  I think setting all the default pad and footprint
>         tolerances to zero and using the user's global settings is the proper
>         way to go.  The problem I see with setting the tolerance on these paste
>         and/or mask pads is the user may not notice that the tolerances are too
>         small for the board manufacturer.  The best case scenario is the boards
>         will be rejected by the manufacturer's DRC or in the worst case the
>         boards will not reflect what the user had intended and possibly fail.
> 
>         On 04/27/2018 03:16 PM, Rene Pöschl wrote:
> 
>             We (the librarians) discovered that our workflow (or is it a workaround
>             for missing features) of defining special paste or mask areas does not
>             work as intended.
> 
>             We use paste or mask only pads (no copper, only past or mask selected,
>             no pin number assigned) to specify mask/paste areas if we can not use
>             the normal way of defining them. (example a large exposed pad needs
>             split up paste areas.) These pads naturally have a clearance setting of
>             0 which tells kicad that the project settings should be applied. (We did
>             not think about that.)
> 
>             To avoid this i assume we will need to set a small clearance in such
>             pads as a workaround. What is the smallest value possible that can be used?
> 
> 

Some info about these masks:

For custom shaped pads, building a solder mask shape with a negative margin can create issues
(unpredictable shape for non convex polygons).
So it is not allowed.

Margin in solder mask layers is needed because there are always registration issues between the
copper layers and the solder mask layer.

Therefore, because the X and Y registration position error, you need a actual mask size bigger than
the area defined by a pad, to be sure the actual solder mask does not cover the pad (the hole in
mask always covers the pad area).
X/Y max error depends on your board house, so this is the reason to have the registration tolerance
defined for the whole board (unless you know your board house, you cannot reliably use a defined
tolerance: it could be too small or too large)

I am guessing there are also similar registration problems for the solder mask, but I don't know them.

-- 
Jean-Pierre CHARRAS