kicad-lib-committers team mailing list archive

[Lorenzo Marcantonio <l.marcantonio@xxxxxxxxxxxx>]

On Sun, Jun 01, 2014 at 06:08:32PM +0100, John Beard wrote:
> OK, so what I did so far (with a "fancy" silk) is not really what we are
> after?

Never said so. Probably we never decided the standard for silks :P
AFAIK the C revision is the first industry standard about it (and it
isn't a standard yet, anyway). It all depends on what you need from the
silk. In these days it has 3 major purposes:

1) Helping for board connection and major component identification (i.e.
where is that connector and what is pin 1); this is post board assembly
and the important things are refdes and pin 1 marker for connectors (or
the little triangle/arrows/dots whatever)

2) Pre/during/post assembly inspection, when not completely automated.
AOI simply looks for fiducials and then look at each solder joint;
however usually it doesn't check for pin 1 orientation (could be
difficult or maybe there are other issues). Could happen that a tape was
programmed or mounted in the wrong direction, so at least for the first
piece after place checking orientation could be a good idea. In the past
there was a recommendation for the 'inspection dot' on pin 1; this
evolved in the inspection line (along pin 1) or boundary break which are
obviously more visible. The last thing silk is useful for is checking
registration of stenciling and placement; that's why they say that the
outline should be visible with the component placed: if it isn't it's
dropped badly (paste registration is usually checked on fiducials,
AFAIK)

3) Manual assembly or reworking/repair. This was in the past the main
purpose of silk screen. Even without all the refdes in place (usually
there is simply no place for all of them!), having the boundary brackets
and the pin 1 marker is actually all you need to do the work.

> Or, considering that there's no way to add the "body" information except
> on the silk, should I keep the fancy silk, which is mostly covered by

That's the real issue for kicad. Since they rejected the
assembly/fabrication layer (and courtyard, too), there is no way to show
the 'full' placement. For reference I attached how I do modules (with
the extra layer). Dark gray is courtyard, light cyan is silk (only two
bars), dark cyan is fabrication (full body with pin 1 indicated). As
a special case  during fabrication plot the refdes position is forced to
the module origin (since the refdes on silk usually is put on a more
visible place).

Without the assembly layer the only choice would be using the 'fancy'
silk, and trust silk erasure by solder mask. Really, the two layers
convey different information in different ways, I don't have a good idea
on how to fix this.

There could be also problems with component hanging over the board size
(like shaft potentiometers); these should go on fabrication but not on
silk: AFAIK pcbnew doesn't trim silk on board edges, the
fabricator/panelizer has to do that.

> the component when assembled, but add the uneven "U shape" as seen in
> the Library Expert screenshot? How would that work for the SMD variants,
> which have large "wings" for mechanical strength? Would the "U" go
> outside these, to the left and right?

Yep, a tipical SOIC only has silk bars on the short side, outside the
body, with the pin 1 side longer for inspection. See attachment, too.

> I also like the arrow method, or a dot, as you can see.

Just a stylistic preference. It's however useful since it actually
happened to me to receive ribbons crimped backwards... having the pin
1 triangle really help to see that the red wire is on the wrong side!
For other connectors (like D-sub) it's not very useful, for rectangular
non-polarized obviously it's mandatory.

-- 
Lorenzo Marcantonio
Logos Srl