kicad-lib-committers team mailing list archive

[John Beard <john.j.beard@xxxxxxxxx>]

On 01/06/14 20:01, Lorenzo Marcantonio wrote:
> On Sun, Jun 01, 2014 at 06:08:32PM +0100, John Beard wrote:
> > OK, so what I did so far (with a "fancy" silk) is not really what we are
> > after?
>
> Never said so. Probably we never decided the standard for silks :P

No time like the present. Any opinions? Personally, I quite like the
"fancy" silks (or fancy assembly layers), but I also would like to make
sure that there is something visible after assembly, if possible. I
realise the detailed silk is more work, so I don't think it should be
any sort of requirement.

> That's the real issue for kicad. Since they rejected the
> assembly/fabrication layer (and courtyard, too), there is no way to show
> the 'full' placement. For reference I attached how I do modules (with
> the extra layer). Dark gray is courtyard, light cyan is silk (only two
> bars), dark cyan is fabrication (full body with pin 1 indicated). As
> a special case  during fabrication plot the refdes position is forced to
> the module origin (since the refdes on silk usually is put on a more
> visible place).

I didn't see an attachment, could you re-send?

> Without the assembly layer the only choice would be using the 'fancy'
> silk, and trust silk erasure by solder mask. Really, the two layers
> convey different information in different ways, I don't have a good idea
> on how to fix this.

I have never registered erasure of silk over pads as a problem, no
fabricator has ever complained or delivered over-printed pads. Has
anyone seen this happen?

How about include an "outer" silk, which is the uneven-U shape and the
pin 1 identifier, along with, optionally, the "inner" silk, which is the
"fancy" outline and would be covered or mostly covered by the component
when assembled.  When hand assembled by hobbyists and amateurs (like
me!) at least, having a nice graphic of what is going in that spot
can be helpful.

> There could be also problems with component hanging over the board
> size (like shaft potentiometers); these should go on fabrication but
> not on silk: AFAIK pcbnew doesn't trim silk on board edges, the
> fabricator/panelizer has to do that.

I have never had a problem with fabricators and overhanging silk, I
imagine it's fairly easily dealt with as a matter of course?

> > the Library Expert screenshot? How would that work for the SMD
> > variants, which have large "wings" for mechanical strength? Would the
> > "U" go outside these, to the left and right?
>
> Yep, a tipical SOIC only has silk bars on the short side, outside the
> body, with the pin 1 side longer for inspection. See attachment, too.

I meant for these SMD connector headers. The Library Expert Lite
software doesn't seem to include these?

> > I also like the arrow method, or a dot, as you can see.

> Just a stylistic preference. It's however useful since it actually
> happened to me to receive ribbons crimped backwards... having the pin
> 1 triangle really help to see that the red wire is on the wrong side!
> For other connectors (like D-sub) it's not very useful, for
> rectangular non-polarized obviously it's mandatory.

Indeed. I would even put it on a D-sub, just so its right there when I
need it! The last thing needed when fiddling with cable harnesses is a
last-second self-doubt over the PCB pin location!

Cheers,

John